CN117317031A - DSRD structure for inhibiting large hole injection and preparation method thereof - Google Patents
DSRD structure for inhibiting large hole injection and preparation method thereof Download PDFInfo
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- 238000002347 injection Methods 0.000 title claims abstract description 31
- 239000007924 injection Substances 0.000 title claims abstract description 31
- 230000002401 inhibitory effect Effects 0.000 title abstract description 16
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims description 24
- 150000002500 ions Chemical class 0.000 claims description 8
- 239000002019 doping agent Substances 0.000 claims description 3
- 230000002829 reductive effect Effects 0.000 description 21
- 229910010271 silicon carbide Inorganic materials 0.000 description 14
- 230000008569 process Effects 0.000 description 13
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 13
- 239000000969 carrier Substances 0.000 description 12
- 238000011084 recovery Methods 0.000 description 12
- 238000000605 extraction Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- -1 nitrogen ions Chemical class 0.000 description 4
- 230000002441 reversible effect Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000036470 plasma concentration Effects 0.000 description 2
- 238000005086 pumping Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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Abstract
The invention relates to a DSRD structure for inhibiting large hole injection and a preparation method thereof, wherein the DSRD structure comprises a cathode, an N+ substrate layer, an N-drift region, a P-drift region, a bonding region and an anode which are sequentially stacked from bottom to top, wherein the bonding region comprises a plurality of P+ regions and a plurality of N+ regions, the P+ regions are respectively arranged on the P-drift region, one N+ region is arranged between two adjacent P+ regions, the adjacent P+ regions are mutually contacted, and the thicknesses of the P+ regions and the N+ regions are equal; ohmic contact is formed between the cathode and the N+ substrate layer, and ohmic contact is formed between the anode and the P+ region and between the anode and the N+ region. The invention can effectively reduce the holes injected into the N-drift region of the DSRD, reduce the large injection degree of the N-drift region and reduce the voltage of the platform region of the device, thereby reducing the power consumption of the device at the stage.
Description
Technical Field
The invention relates to the technical field of semiconductor processes, in particular to a DSRD structure for inhibiting large hole injection and a preparation method thereof.
Background
The drift step recovery diode (Drift Step Recovery Diodes, DSRD for short) is a semiconductor switching diode, proposed by Russian about fei physical technology research, generally applied to Ultra Wide Band (UWB for short) systems, used as a key device in various pulse signal sources, can achieve nanosecond or picosecond switching time, and has the characteristics of high peak power, high pulse repetition frequency, high time stability and the like.
Silicon-based DSRD has failed to meet the requirements of most high voltage pulse systems of several thousand volts or even tens of kilovolts due to the theoretical limitations of silicon materials. In a pulse system with the same voltage class requirement, the serial number of the silicon carbide-based DSRD is far smaller than that of the silicon-based DSRD, so that the volume of the system is greatly saved. Meanwhile, the reduction of the thickness of the drift region and the improvement of the saturation drift speed can reduce the turn-off time of the device, so that the silicon carbide-based DSRD can work in high-frequency and high-speed application scenes.
However, due to the influences of the low service life and mobility of the current carrier and incomplete ionization effect of impurities, the conventional silicon carbide-based DSRD locally deviates from the electroneutrality in the reverse pumping stage of pulse discharge to influence the carrier extraction speed, so that the voltage pulse has long front time, low voltage pulse peak value and high device power consumption, the advantages of the silicon carbide material are difficult to fully develop, and the performance of the device is limited.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a DSRD structure for inhibiting large hole injection and a preparation method thereof. The technical problems to be solved by the invention are realized by the following technical scheme:
a DSRD structure for suppressing large injection of holes, comprising a cathode, an N+ substrate layer, an N-drift region, a P-drift region, a junction region and an anode, which are sequentially stacked from bottom to top,
the combination region comprises a plurality of P+ regions and a plurality of N+ regions, the P+ regions are arranged on the P-drift region in a spaced mode, one N+ region is arranged between two adjacent P+ regions, the adjacent P+ regions are in contact with the N+ regions, and the thicknesses of the P+ regions and the N+ regions are equal;
ohmic contact is formed between the cathode and the N+ substrate layer, and ohmic contact is formed between the anode and the P+ region and between the anode and the N+ region.
In one embodiment of the invention, the doping concentrations of the p+ region and the n+ region are equal.
In one embodiment of the invention, the doping concentration of the p+ region and the n+ region is greater than the doping concentration of the P-drift region and the N-drift region.
In one embodiment of the invention, the doping concentration of the P-drift region is greater than the doping concentration of the N-drift region.
In one embodiment of the invention, the doping concentration of the p+ region and the n+ region is greater than the doping concentration of the n+ substrate layer, which is greater than the doping concentration of the P-drift region.
In one embodiment of the invention, the N+ substrate layer has a doping concentration of 5X 10 18 cm -3 The doping concentration of the N-drift region is 1×10 14 cm -3 -1×10 17 cm -3 The doping concentration of the P-drift region is 1×10 14 cm -3 -1×10 18 cm -3 The doping concentration of the P+ region and the N+ region is 1×10 19 cm -3 -1×10 20 cm -3 。
In one embodiment of the invention, the doping ions of the n+ substrate layer, the N-drift region and the n+ region are the same.
In one embodiment of the invention, the dopant ions of the P-drift region and the p+ region are the same.
In one embodiment of the invention, the thickness of the N-drift region is greater than the thickness of the P-drift region, which is greater than the thicknesses of the p+ and n+ regions.
One embodiment of the present invention also provides a method for preparing a DSRD structure for inhibiting hole large injection, the DSRD structure comprising:
selecting an N+ substrate layer;
preparing an N-drift region on the N+ substrate layer;
preparing a P-drift region on the N-drift region;
preparing a combination region on the P-drift region, wherein the combination region comprises a plurality of P+ regions and a plurality of N+ regions, the P+ regions are arranged on the P-drift region at intervals, one N+ region is arranged between two adjacent P+ regions, the adjacent P+ regions are contacted with the N+ regions, and the thicknesses of the P+ regions and the N+ regions are equal;
preparing anodes on the P+ region and the N+ region, wherein ohmic contact is formed between the anodes and the P+ region and the N+ region;
and preparing a cathode on the lower surface of the N+ substrate layer, wherein the cathode and the N+ substrate layer are in ohmic contact.
Compared with the prior art, the invention has the beneficial effects that:
in this embodiment, a combination region composed of a plurality of p+ regions and a plurality of n+ regions is disposed on the P-drift region, and the plurality of p+ regions and the plurality of n+ regions are alternately disposed therebetween, so that the combination region forms a doped region intersecting the p+ regions and the n+ regions, and therefore, in the forward current injection stage, since the n+ region is disposed between the two p+ regions, the effective area of the p+ region is reduced, holes injected into the N-drift region of the DSRD can be effectively reduced, the degree of large injection of the N-drift region is reduced, and the plateau region voltage of the device is reduced, thereby reducing the device power consumption in this stage. In the stage of rapid turn-off of the device, the structural design reduces the large injection degree of the N-drift region, so that the phenomenon of soft recovery presented by the N-drift region in the turn-off process is effectively relieved, the drift speed of majority carriers can be effectively improved, the expansion speed of a space charge region is accelerated, and the rise time of the device is reduced, so that the switching speed of the device is improved.
In the minority carrier extraction stage of the reverse pumping, the doping concentration in the P-drift region near the P+N+/P-junction of the DSRD structure is low, so that the complete ionization degree is high, the degree of partial deviation of the P-drift region from the electric neutrality is effectively reduced, the voltage of a platform region of the device is reduced, and the power consumption of the device in the stage is reduced.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of a DSRD structure for suppressing large hole injection provided by an embodiment of the present invention;
fig. 2 is a schematic flow chart of a method for preparing a DSRD structure for inhibiting hole large injection according to an embodiment of the present invention;
fig. 3 a-3 f are schematic process diagrams of a method for preparing a DSRD structure for inhibiting hole large injection according to an embodiment of the present invention;
fig. 4 a-4 f are process diagrams of a method for fabricating a DSRD structure for inhibiting hole large injection according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 1, fig. 1 is a schematic diagram of a DSRD structure for inhibiting hole large injection provided by an embodiment of the present invention, where the DSRD structure includes, from bottom to top, a cathode 6, an n+ substrate layer 1, an N-drift region 2, a P-drift region 3, a junction region, and an anode 7, which are sequentially stacked, wherein:
the bonding region comprises a plurality of P+ regions 4 and a plurality of N+ regions 5, the P+ regions 4 are arranged on the P-drift region 3 at intervals, an N+ region 5 is arranged between two adjacent P+ regions 4, the adjacent P+ regions 4 and N+ regions 5 are contacted with each other, and the thicknesses of the P+ regions 4 and the N+ regions 5 are equal;
ohmic contact is formed between the cathode 6 and the n+ substrate layer 1, and ohmic contact is formed between the anode 7 and the p+ region 4 and the n+ region 5.
In this embodiment, a junction region comprising a plurality of p+ regions 4 and a plurality of n+ regions 5 is disposed on the P-drift region 3, and the plurality of p+ regions 4 and the plurality of n+ regions 5 are alternately disposed at intervals, so that the junction region forms a doped region formed by crossing the p+ regions 4 and the n+ regions 5, and the current flows in the anode direction to the cathode, so that, in the forward current injection stage, since the n+ regions 5 are disposed between the two p+ regions 4, the effective area of the p+ regions 5 is reduced, during the forward injection, the number of charges flowing through the cross-sectional area of the p+ regions 5 is fixed, so that the number of charges flowing through the effective area of the p+ regions 5 can be reduced, and thus the unbalanced holes injected into the N-drift region 2 of the DSRD can be effectively reduced, so that the degree of the N-drift region 2 is greatly injected (the concentration of unbalanced carriers generated is greater than the balanced multi-carrier concentration), and the voltage of the platform region is greatly injected into the N-drift region 2 is related to the unbalanced carrier concentration, so that the voltage of the platform region is greatly reduced, i.e., the voltage drop device is greatly reduced when the voltage of the platform region is most d is greatly reduced.
In the process of DSRD backward extraction, electrons and holes of unbalanced carriers respectively move to two sides, and in 4H-SiC, the mobility of electrons is far greater than that of holes, so that the front of plasma concentration moves from one side of a P+ region 4 to one side of an N+ region 5. The off process presents "soft recovery" in the N-base device portion (i.e., P + N-N +) formed by P + region 4, N-drift region 2, and N + substrate layer 1 while the PN junction electric field is formed and spread (balanced multi-carrier and unbalanced carrier are simultaneously extracted); in the P-base device portion (i.e., p+p-n+) formed by the p+ region 4, the P-drift region 3, and the n+ substrate layer 1, when the unbalanced carriers are completely extracted, the plasma concentration front reaches the PN junction, where the electric field begins to form and spread (begin to extract balanced polynomials), and the shutdown process presents "hard recovery". In the rapid turn-off stage of the device, the structural design reduces the large injection degree of the N-drift region 2, so that the phenomenon of soft recovery presented by the N-drift region 2 in the turn-off process is effectively relieved.
I=nqvs, i.e. the reverse extraction current is equal to the concentration q drift velocity area, in "soft recovery" (simultaneous extraction of unbalanced carriers and peaces Heng Duozi) for the N-drift region 2; the P-drift region 3 is "hard-recovered" (balanced multi-carriers begin to be extracted after the non-balanced carriers are extracted), and the space charge region is developed. Therefore, when the current and the area are the same, the extraction concentration of the N-drift region 2 is equal to the balance carrier and the unbalance carrier, so that the concentration of the corresponding unbalance carrier is reduced due to the fact that the large injection degree is weakened, the drift speed of majority carriers can be effectively improved, the expansion speed of a space charge region is increased, the rise time of a device is reduced, the switching speed of the device is improved, and the soft recovery phenomenon of the N-drift region 2 in the turn-off process is relieved.
In the counter-pumped minority carrier extraction stage, the P-drift region 3 has a low doping concentration and a negative correlation between the ionization degree and the doping concentration, and thus the P-drift region 3 has a low doping concentration, so that the ionization degree becomes high, and thus the total ionization degree is high, and the N-drift region 3 has a high doping concentration A -N A - The reduction effectively reduces the extent to which the P-drift region 3 is locally offset from charge neutrality. Reducing the degree of local deviation of the P-drift region 3 from charge neutrality, N A -N A - The reduction reduces the large injection degree, reduces injected unbalanced carriers, and ensures that the platform region voltage and the unbalanced carrier concentration are positively correlated, so that the platform region voltage is reduced, the platform region voltage of the device is reduced, and the power consumption of the device at the stage is reduced.
Optionally, the material of the n+ substrate layer 1, the N-drift region 2, the P-drift region 3, the p+ region 4 and the n+ region 5 is the same.
Further, the materials of the n+ substrate layer 1, the N-drift region 2, the P-drift region 3, the p+ region 4 and the n+ region 5 all comprise SiC. Compared with silicon materials, the silicon carbide materials have higher forbidden band width, saturation drift speed, heat conductivity, critical breakdown electric field and irradiation resistance, so that the performance of the silicon carbide-based DSRD device is superior to that of the silicon-based DSRD.
In a specific embodiment, the doping concentrations of p+ region 4 and n+ region 5 are equal. And a metal layer is deposited on the P+ region 4 and the N+ region 5 to form ohmic contact, so that the P+ region 4 and the N+ region 5 are required to be doped with high concentration, and the doping concentrations are selected to be equal.
In a specific embodiment, the doping concentration of the p+ region 4 and the n+ region 5 is greater than the doping concentration of the P-drift region 3 and the N-drift region 2. This is because the DSRD device is essentially a PiN diode whose i-region is less concentrated than p+ region 4 and n+ region 5,i, which are responsible for high voltage endurance, and which consists of P-drift region 3 and N-drift region 2, thus requiring a lower concentration than p+ region 4 and n+ region 5.
In a specific embodiment, the doping concentration of the P-drift region 3 is greater than the doping concentration of the N-drift region 2. The DSRD device is essentially a Pin diode, the i area concentration of the PiN diode is lower than that of the P+ area 4 and the N+ area 5,i area, the i area comprises a P-drift area 3 and an N-drift area 2, but the i area is mainly subjected to voltage resistance by the N-drift area 2, so that the P-drift area 3 concentration is higher than that of the N-drift area 2, and a new small area abrupt junction Pin is formed.
In a specific embodiment, the doping concentration of the p+ region 4 and the n+ region 5 is greater than the doping concentration of the n+ substrate layer 1, and the doping concentration of the n+ substrate layer 1 is greater than the doping concentration of the P-drift region 3. Since the P-drift region 3 is responsible for the high voltage resistance, the doping concentration of the n+ substrate layer 1 is greater than the doping concentration of the P-drift region 3
Optionally, the doping concentration of the n+ substrate layer 1 is 5×10 18 cm -3 The doping concentration of the N-drift region 2 is 1×10 14 cm -3 -1×10 17 cm -3 The doping concentration of the P-drift region 3 is 1×10 14 cm -3 -1×10 18 cm -3 The doping concentration of the P+ region 4 and the N+ region 5 is 1×10 19 cm -3 -1×10 20 cm -3 。
Optionally, the doping ions of the n+ substrate layer 1, the N-drift region 2 and the n+ region 5 are the same.
Preferably, the doping ions of the n+ substrate layer 1, the N-drift region 2 and the n+ region 5 are all nitrogen ions.
Optionally, the doping ions of the P-drift region 3 and the p+ region 4 are identical.
Preferably, the doping ions of the P-drift region 3 and the p+ region 4 are both aluminum ions.
In a specific embodiment, the thickness of the N-drift region 2 is greater than the thickness of the P-drift region 3, and the thickness of the P-drift region 3 is greater than the thicknesses of the p+ region 4 and the n+ region 5. The PIN diode is voltage-resistant by the I region, the N-drift region 2 and the P-drift region 3 in the DSRD device belong to the I region, but the N-drift region 2 is voltage-resistant mainly, so that the N-drift region 2 is thicker than the P-drift region 3, and the thickness of the P-drift region 3 is thicker than the P+ region 4 and the N+ region 5.
According to the DSRD structure disclosed by the invention, by optimizing the structure of the silicon carbide drift step fast recovery diode, the P-drift region is provided with the combination region consisting of the plurality of P+ regions and the plurality of N+ regions, and the plurality of P+ regions and the plurality of N+ regions are alternately arranged to inhibit large injection of the N-drift region, so that the drift speed of carriers in the extraction process (soft recovery in the turn-off process is avoided), the reverse drift speed of the carriers is improved, the expansion of the space charge region is accelerated, the turn-off speed is accelerated, the pulse front edge of the silicon carbide-based DSRD is further shortened, the power consumption of a device is reduced, and the reliability of the device is improved.
Example two
The present invention further provides a method for preparing a DSRD structure for inhibiting hole large injection on the basis of the first embodiment, referring to fig. 2, fig. 2 is a schematic flow chart of a method for preparing a DSRD structure for inhibiting hole large injection provided in the embodiment of the present invention, where the method for preparing a DSRD structure specifically includes:
and 1, selecting an N+ substrate layer 1.
And 2, preparing an N-drift region 2 on the N+ substrate layer 2.
And 3, preparing a P-drift region 3 on the N-drift region 2.
And 4, preparing a bonding region on the P-drift region 3, wherein the bonding region comprises a plurality of P+ regions 4 and a plurality of N+ regions 5, the P+ regions 4 are arranged on the P-drift region 3 at intervals, an N+ region 5 is arranged between two adjacent P+ regions 4, the adjacent P+ regions 4 and the N+ regions 5 are contacted with each other, and the thicknesses of the P+ regions 4 and the N+ regions 5 are equal.
And 5, preparing an anode 7 on the P+ region 4 and the N+ region 5, wherein ohmic contact is formed between the anode 7 and the P+ region 4 and the N+ region 5.
And 6, preparing a cathode 6 on the lower surface of the N+ substrate layer 1, wherein the cathode 6 is in ohmic contact with the N+ substrate layer 1.
According to the DSRD structure disclosed by the invention, through optimizing the structure of the silicon carbide drift step fast recovery diode, a combination region consisting of a plurality of P+ regions and a plurality of N+ regions is arranged on a P-drift region, and the P+ regions and the N+ regions are alternately arranged to inhibit large injection of the N-drift region, so that the drift speed of carriers in the extraction process (soft recovery in the turn-off process is avoided), the pulse front of the silicon carbide-based DSRD is further shortened, the power consumption of a device is reduced, and the reliability of the device is improved.
Example III
The present invention provides a specific method for preparing a DSRD structure for inhibiting hole large injection on the basis of the second embodiment, please refer to fig. 3 a-3 f, and fig. 3 a-3 f are schematic process diagrams of the method for preparing a DSRD structure for inhibiting hole large injection according to the embodiment of the present invention, wherein the method for preparing a DSRD structure specifically includes:
step 1, for a thickness of 350 μm and a doping concentration of 5X 10 18 cm -3 The SiC substrate of (1) is subjected to RCA standard cleaning to form an n+ substrate layer.
Step 2, as shown in FIG. 3a, epitaxially grow a thickness of 10 μm and a doping concentration of 1×10 on the N+ substrate layer 1 14 cm -3 -1×10 17 cm -3 N-drift region 2 of (a).
Step 3, as shown in FIG. 3b, an epitaxial growth with a thickness of 6 μm and a doping concentration of 1X 10 is performed on the N-drift region 2 14 cm -3 -1×10 18 cm -3 P-drift region 3 of (a).
Step 4, as shown in FIG. 3c, epitaxially grown on the P-drift region 3 to a thickness of 2 μm and a doping concentration of 1×10 19 cm -3 -1×10 20 cm -3 P+ region 4 of (c).
Step 5, as shown in FIG. 3d, nitrogen ions are implanted into the P+ region 4 at intervals by ion implantation to form a doping concentration of 1×10 19 cm -3 -1×10 20 cm -3 Is provided, the plurality of n+ regions 5 are arranged at intervals.
And 6, as shown in fig. 3e, depositing Ni metal on the surface of the N+ substrate layer 1, and annealing to form N-type ohmic contact to form a cathode 6.
And 7, as shown in fig. 3f, depositing Ni metal on the surfaces of the P+ region 4 and the N+ region 5, and annealing to form P-type ohmic contact to form an anode 7.
Example IV
The present invention provides a preparation method of a DSRD structure for inhibiting hole large injection based on the second embodiment, referring to fig. 4a to fig. 4f, fig. 4a to fig. 4f are schematic process diagrams of a preparation method of a DSRD structure for inhibiting hole large injection according to the embodiment of the present invention, where the preparation method of a DSRD structure specifically includes:
step 1, for a thickness of 350 μm and a doping concentration of 5X 10 18 cm -3 The SiC substrate of (1) is subjected to RCA standard cleaning to form an n+ substrate layer.
Step 2, as shown in FIG. 3a, epitaxially grow a thickness of 10 μm and a doping concentration of 1×10 on the N+ substrate layer 1 14 cm -3 -1×10 17 cm -3 N-drift region 2 of (a).
Step 3, as shown in FIG. 3b, an epitaxial growth with a thickness of 6 μm and a doping concentration of 1X 10 is performed on the N-drift region 2 14 cm -3 -1×10 18 cm -3 P-drift region 3 of (a).
Step 4, as shown in FIG. 3c, epitaxially grown on the P-drift region 3 to a thickness of 2 μm and a doping concentration of 1×10 19 cm -3 -1×10 20 cm -3 N+ region 5 of (a).
Step 5, as shown in FIG. 3d, aluminum ions are implanted into the N+ region 5 at intervals by ion implantation to form a doping concentration of 1×10 19 cm -3 -1×10 20 cm -3 Is provided, the plurality of p+ regions 4 are arranged at intervals.
And 6, as shown in fig. 3e, depositing Ni metal on the surface of the N+ substrate layer 1, and annealing to form N-type ohmic contact to form a cathode 6.
And 7, as shown in fig. 3f, depositing Ni metal on the surfaces of the P+ region 4 and the N+ region 5, and annealing to form P-type ohmic contact to form an anode 7.
In the description of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
Although the invention is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. Modifications made by those skilled in the art without departing from the spirit of the invention should be considered as falling within the scope of the invention.
Claims (10)
1. A DSRD structure for suppressing large hole injection is characterized by comprising a cathode, an N+ substrate layer, an N-drift region, a P-drift region, a bonding region and an anode which are sequentially stacked from bottom to top,
the combination region comprises a plurality of P+ regions and a plurality of N+ regions, the P+ regions are arranged on the P-drift region in a spaced mode, one N+ region is arranged between two adjacent P+ regions, the adjacent P+ regions are in contact with the N+ regions, and the thicknesses of the P+ regions and the N+ regions are equal;
ohmic contact is formed between the cathode and the N+ substrate layer, and ohmic contact is formed between the anode and the P+ region and between the anode and the N+ region.
2. The DSRD structure of claim 1 wherein the p+ region and the n+ region are doped at equal concentrations.
3. The DSRD structure of claim 2 wherein the p+ region and the n+ region have a doping concentration greater than the P-drift region and the N-drift region.
4. The DSRD structure of claim 3, wherein the P-drift region has a doping concentration greater than the N-drift region.
5. The DSRD structure of claim 4, wherein the p+ region and the n+ region have a doping concentration greater than a doping concentration of the n+ substrate layer, the n+ substrate layer having a doping concentration greater than a doping concentration of the P-drift region.
6. The DSRD structure of claim 5, wherein the n+ substrate layer has a doping concentration of 5 x 10 18 cm -3 The doping concentration of the N-drift region is 1×10 14 cm -3 -1×10 17 cm -3 The P-drift region is doped with a heavy metalDegree of 1×10 14 cm -3 -1×10 18 cm -3 The doping concentration of the P+ region and the N+ region is 1×10 19 cm -3 -1×10 20 cm -3 。
7. The DSRD structure of claim 6 wherein the n+ substrate layer, the N-drift region, and the n+ region are the same dopant ions.
8. The DSRD structure of claim 6 wherein the P-drift region and the p+ region are the same dopant ions.
9. The DSRD structure of claim 1 wherein the N-drift region has a thickness greater than a thickness of the P-drift region, the P-drift region having a thickness greater than a thickness of the p+ region and the n+ region.
10. A method of preparing a DSRD structure that suppresses hole large injection, the DSRD structure comprising:
selecting an N+ substrate layer;
preparing an N-drift region on the N+ substrate layer;
preparing a P-drift region on the N-drift region;
preparing a combination region on the P-drift region, wherein the combination region comprises a plurality of P+ regions and a plurality of N+ regions, the P+ regions are arranged on the P-drift region at intervals, one N+ region is arranged between two adjacent P+ regions, the adjacent P+ regions are contacted with the N+ regions, and the thicknesses of the P+ regions and the N+ regions are equal;
preparing anodes on the P+ region and the N+ region, wherein ohmic contact is formed between the anodes and the P+ region and the N+ region;
and preparing a cathode on the lower surface of the N+ substrate layer, wherein the cathode and the N+ substrate layer are in ohmic contact.
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