JPH07273354A - Diode - Google Patents
DiodeInfo
- Publication number
- JPH07273354A JPH07273354A JP8800794A JP8800794A JPH07273354A JP H07273354 A JPH07273354 A JP H07273354A JP 8800794 A JP8800794 A JP 8800794A JP 8800794 A JP8800794 A JP 8800794A JP H07273354 A JPH07273354 A JP H07273354A
- Authority
- JP
- Japan
- Prior art keywords
- impurity concentration
- diode
- region
- layer
- concentration region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000012535 impurity Substances 0.000 claims abstract description 49
- 238000011084 recovery Methods 0.000 abstract description 20
- 238000010586 diagram Methods 0.000 description 11
- 239000000969 carrier Substances 0.000 description 10
- 230000007423 decrease Effects 0.000 description 10
- 238000009826 distribution Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 229910001385 heavy metal Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する分野の説明】本発明は整流用ダイオ−ド
特に高速ダイオ−ドの構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rectifying diode, and more particularly to a structure of a high speed diode.
【０００２】[0002]
【従来技術とその問題点】近年、電子機器の小型化、高
効率化のために、装置の高周波化が進んでおり、機器に組
み込まれる整流用のダイオ−ドに対しても高周波化の要
望が強い。高周波用のダイオ−ド（高速ダイオ−ド）に
必要な特性として、逆回復に要する時間が短いことが要
求される。これと共に近年問題となっているのが、ダイ
オ−ドの逆回復時の電流変化と、ダイオ−ドを組み込ん
だ回路に存在する浮遊インダクタンスとによる、スパイ
クノイズの問題である。2. Description of the Related Art In recent years, the frequency of devices has been increasing in order to reduce the size and increase the efficiency of electronic devices, and it is desired to increase the frequency of rectifying diodes incorporated in the devices. Is strong. As a characteristic required for a high frequency diode (high speed diode), a short time required for reverse recovery is required. Along with this, a problem in recent years is a spike noise problem due to a current change at the time of reverse recovery of the diode and a stray inductance existing in a circuit incorporating the diode.
【０００３】図３は従来構造図で図中１はＮ型シリコン
基体（高濃度不純物ｎ層）、２は （２） 低濃度不純物ｎ層（ｉ領域）、４は高濃度不純物ｐ層、
ＪはＰＮ接合である。図４はその不純物濃度分布図、図
５は逆回復時の電流、電圧波形を示す。FIG. 3 shows a conventional structure. In FIG. 3, 1 is an N-type silicon substrate (high concentration impurity n layer), 2 is (2) low concentration impurity n layer (i region), 4 is high concentration impurity p layer,
J is a PN junction. FIG. 4 shows the impurity concentration distribution diagram, and FIG. 5 shows current and voltage waveforms during reverse recovery.
【０００４】ダイオ−ドの逆回復時間Ｔｒｒは、大別し
て図示の様に２種類の期間からなりたっている。即ち
ダイオ−ドの電流が順方向のＩＦから０迄減少して逆方
向電流が流れ始めた時点から電流がその尖頭値IRPとな
るまでの期間Ｔ1 前記期間Ｔ1の後の、電流が減少して再び０になるま
での期間Ｔ2 ダイオ−ドの高速動作の為には逆回復時間Ｔｒｒが短い
ことが望ましい。しかし、ダイオ−ドの逆電流ＩＲがそ
の尖頭値IRPに達してから、電流が０になるまでの期間
Ｔ２があまりに短いと浮遊インダクタンス成分Ｌによる
Ｌ＊ｄｉ／ｄｔなる誘起起電力が大きくなり、いわゆる
スパイクノイズ発生の原因となる。この様なスパイクノ
イズを低減するためには、Ｔ２の期間の電流減少率ｄｉ
／ｄｔを小さくしてやればよい。しかし、単にＴ２の期
間の電流減少率ｄｉ／ｄｔを小さくするとダイオ−ドの
逆回復時間Ｔｒｒが長くなってしまう。ちなみに、電流
が順方向電流ＩＦから減少して、逆方向電流の尖頭値IR
Pへ向う場合の−ｄｉ／ｄｔは、ほぼ、回路側の条件で
決まっている。The reverse recovery time Trr of the diode is roughly divided into two types as shown in the figure. That is, the period T1 from the time when the current in the diode decreases from IF in the forward direction to 0 and the backward current starts to flow until the current reaches its peak value IRP, and the current decreases after the period T1. It is desirable that the reverse recovery time Trr is short for high-speed operation of the period T2 diode until it becomes 0 again. However, if the period T2 from when the reverse current IR of the diode reaches the peak value IRP to when the current becomes 0 is too short, the induced electromotive force L * di / dt due to the stray inductance component L becomes large. This causes so-called spike noise. In order to reduce such spike noise, the current decrease rate di during the period T2
It suffices to reduce / dt. However, if the current reduction rate di / dt in the period T2 is simply decreased, the reverse recovery time Trr of the diode becomes long. By the way, the current decreases from the forward current IF and the reverse current peak value IR
When going to P, -di / dt is almost determined by the conditions on the circuit side.
【０００５】ここで、ダイオ−ドの内部のキャリア−の
動きから逆回復時の様子を見るとＴ1の期間はさらに、
順方向バイアス時に蓄積されていたキャリア−が減少
し、ｐｎ接合が回復して逆バイアス電圧を持ち始める迄
の期間Ｔｊと、ひきつづいて接合近傍に空乏領域が広が
り、この領域に蓄積されていたキャリア−が吸い出され
る期間Ｔｋとに分けられる。Ｔ2の期間は、逆バイアス
電圧の増加にともなう空乏領域のさらなる増大により、
この領域に蓄積されていたキャリア−が吸い出される期
間である。勿論、各期間を通じて再結合によるキャリア
−の減少は起こっている。一般に、Ｔｒｒを短くするた
めには、重金属拡散等によりキャリア−のライフタイム
を短くする必要があるが、この場合、低濃度領域に蓄積
されたキャリア−量が減少すること、また、再結合によ
るキャリア−の減少速度が速くなる （３） 等によりＴ2も短くなりｄｉ／ｄｔが大きくなってしま
う。この様に、Ｔｒｒを短くし、かつ、電流減少率ｄｉ
／ｄｔの小さい、いわゆるソフトリカバリ−特性のダイ
オ−ドを作るのは困難であった。Looking at the state at the time of reverse recovery from the movement of the carrier inside the diode, the period of T1 is further
Carriers accumulated in the forward bias are reduced, a period Tj until the pn junction recovers and starts to have a reverse bias voltage, and a depletion region continuously spreads in the vicinity of the junction, and carriers accumulated in this region. -Is divided into a period Tk for being sucked out. During the period of T2, due to the further increase of the depletion region with the increase of the reverse bias voltage,
This is a period in which the carriers accumulated in this area are sucked out. Of course, the reduction of carriers due to recombination occurs during each period. In general, in order to shorten Trr, it is necessary to shorten the carrier lifetime by diffusion of heavy metals or the like. In this case, however, the amount of carriers accumulated in the low concentration region is reduced, and due to recombination. Due to the faster carrier reduction rate (3), T2 becomes shorter and di / dt becomes larger. In this way, Trr is shortened and the current decrease rate di
It was difficult to make a diode having a so-called soft recovery characteristic with a small / dt.
【０００６】[0006]
【発明の目的】本発明の目的は、ｐｉｎダイオ−ドに関
し、特に、逆回復時の逆方向電流の尖頭値ＩＲＰを小さ
くすることにより逆回復時間Ｔｒｒを長くしないで、Ｔ
2の期間のｄｉ／ｄｔを小さくし、ソフトリカバリ−特
性のダイオ−ドを提供する事にある。It is an object of the present invention to relate to a pin diode, and in particular, the reverse recovery time Trr is not increased by reducing the peak value IRP of the reverse current at the time of reverse recovery.
The purpose is to reduce the di / dt during the period of 2 and provide a diode with a soft recovery characteristic.
【０００７】[0007]
【課題を解決するための本発明の手段】本発明では、ｐ
ｉｎダイオ−ドにおいて、ｐ層とｎ層との間に設けられ
た低不純物濃度領域内に、これと同導電型で、かつこれ
よりも高不純物濃度の領域を、ｐｎ接合に隣接して設け
たことを特徴としている。According to the present invention, p
In the in-diode, a region of the same conductivity type and a higher impurity concentration than that is provided in the low impurity concentration region provided between the p layer and the n layer adjacent to the pn junction. It is characterized by that.
【０００８】[0008]
【実施例】ここでの説明は、不純物濃度の低いｉ層とし
てｎ型低不純物濃度層を持つダイオ−ドについて行う。
この構造を単にｐｉｎ（構造）とよぶ。図１は本発明の
一実施例を示す断面構造図、図２はその不純物濃度分布
図で従来例と同一符号は同等部分を示す。図において、
１はｎ層、２はｉ層、３はｉ層中に設けられたｎ層、４
はｐ層をそれぞれ示している。本実施例は、従来のｐｉ
ｎ構造ダイオ−ドのｉ層の中に、これと同じ導電型で、
かつ高不純物濃度の層をｐ型層に隣接して設けたことが
特徴となっている。DESCRIPTION OF THE PREFERRED EMBODIMENTS The description here will be made on a diode having an n-type low impurity concentration layer as an i layer having a low impurity concentration.
This structure is simply called a pin (structure). FIG. 1 is a sectional structural view showing an embodiment of the present invention, and FIG. 2 is an impurity concentration distribution diagram thereof. In the figure,
1 is an n layer, 2 is an i layer, 3 is an n layer provided in the i layer, 4
Indicates p layers, respectively. In this embodiment, the conventional pi
In the i-layer of the n-structure diode, with the same conductivity type,
Moreover, it is characterized in that a layer having a high impurity concentration is provided adjacent to the p-type layer.
【０００９】本発明構造では、接合が回復した直後の空
乏層は主に、ｐ型層に隣接して設けたｎ型高不純物濃度
領域に広がるので従来のｐｉｎダイオ−ドのｉ層に広が
る空乏層に比較して幅が狭く、又、広がる速度も遅い。
従って、空乏層の広 （４） がりにより吸い出されるキャリア−の量が少なく電流は
あまり増加しない。このため、尖頭逆電流ＩＲＰの値が
小さくＴｋの期間も短くなり、空乏化していないｉ層部
分に多くのキャリア−が残っている。そしてその後のＴ
２の期間はｉ層に空乏層が広がるようになりここでは空
乏層が広がり易いため、電流の急激な減少が起こりにく
く、従来構造のダイオ−ドに較べてソフトリカバリ−特
性となる。In the structure of the present invention, the depletion layer immediately after the junction is restored mainly spreads in the n-type high impurity concentration region provided adjacent to the p-type layer, so that the depletion spread in the i-layer of the conventional pin diode. It is narrower than the layers and spreads slowly.
Therefore, the amount of carriers absorbed by the wide (4) depletion layer is small and the current does not increase so much. For this reason, the value of the peak reverse current IRP is small, the period of Tk is also short, and many carriers remain in the i-layer portion which is not depleted. And then T
During the period of 2, the depletion layer spreads to the i layer, and the depletion layer easily spreads here, so that a rapid decrease in the current is less likely to occur and the soft recovery characteristic is obtained as compared with the diode having the conventional structure.
【００１０】図６は従来のｐｉｎ構造ダイオ−ドａ及
び、本実施例の構造を持つダイオ−ド（ｂ）の、逆回復
時の電流波形を示す。電流波形の時間変化は先ず時刻ｔ
1では、両方のダイオ−ドとも、ｐｎ接合付近のキャリ
ア−はまだかなり残っている。時刻ｔ2になるとｐｎ接
合の空乏化が始まっている。時刻ｔ3になると従来のダ
イオ−ド（ａ）では空乏層の広がり速度が速く、大量の
キャリア−が吸い出されるため、電流はまだ増加してい
る。一方、この時刻ｔ3において、本実施例のダイオ−
ド（ｂ）では空乏層の広がり速度が遅いため、電流が増
加し難く既にその尖頭値に達している。時刻ｔ4におい
て、従来のダイオ−ド（ａ）においても電流がその尖頭
値に達している。一方、本実施例のダイオ−ド（ｂ）で
は電流は徐々に減少し始めている。時刻ｔ5になると、
従来のダイオ−ド（ａ）においては電流が急激に減少し
始める、これは空乏層の広がり速度は既に広がった空乏
層幅に反比例する関係にあり、キャリア−の吸いだし量
が急減するためである。一方、本実施例のダイオ−ド
（ｂ）では空乏層幅が小さく電流は徐々に減少する。時
刻ｔ6になると、従来のダイオ−ド（ａ）においては電
流がほとんど０になっている。一方、本実施例のダイオ
−ド（ｂ）ではｉ層２内のキャリア−は未だ残っており
電流はゆるやかに減少する。以上のように、本実施例の
ダイオ−ドでは、従来のｐｉｎ構造のダイオ−ド （５） に較べてソフトリカバリ−特性となる。FIG. 6 shows current waveforms at the time of reverse recovery of the conventional pin structure diode a and the diode (b) having the structure of this embodiment. The time change of the current waveform is the time t
In 1, in both diodes, carriers near the pn junction still remain considerably. At time t2, depletion of the pn junction has started. At time t3, in the conventional diode (a), the depletion layer spreads at a high speed and a large amount of carriers are sucked out, so that the current is still increasing. On the other hand, at this time t3, the dio-
In (b), since the depletion layer spreads slowly, the current hardly increases and the peak value has already been reached. At time t4, the current reaches its peak value even in the conventional diode (a). On the other hand, in the diode (b) of this embodiment, the current is gradually decreasing. At time t5,
In the conventional diode (a), the current starts to decrease sharply because the speed of depletion layer spreading is inversely proportional to the already widened depletion layer width, and the amount of carrier drained sharply decreases. is there. On the other hand, in the diode (b) of this embodiment, the width of the depletion layer is small and the current gradually decreases. At time t6, the current is almost zero in the conventional diode (a). On the other hand, in the diode (b) of this embodiment, the carriers in the i layer 2 still remain, and the current gradually decreases. As described above, the diode of this embodiment has a soft recovery characteristic as compared with the conventional diode (5) of the pin structure.
【００１１】ダイオ−ドの諸特性のうち、この他の重要
な特性として逆方向耐圧が有る。一般にｉ層の不純物濃
度が高いとｐｎ接合の電界強度が高くなり易く耐圧が低
くなってしまう。しかし、本実施例においては、ｐ型層
に接した高不純物濃度領域の先に低不純物濃度のｉ層が
存在しており、この両領域の厚さ、不純物濃度を調節す
ることにより充分、必要な逆耐電圧を得ることが出来
る。このダイオ−ドの製造法は先ず、ウェファ−径１０
０ｍｍ、厚さ４００μｍ、抵抗率０.００３Ω・ｃｍ、面
方位（１１１）のｎ型シリコン基板ウェファ−１を用意
する。この基板ウェファ−１の主表面にｎ型高抵抗層、
すなわちｉ層２（２０Ω・ｃｍ）を、厚さ５０μｍだけ
エピタキシャル成長させる。次にエピタキシャル成長中
のド−バントの量を増加してｎ型の低抵抗層３（４.５
Ω・ｃｍ）を１０μｍ成長させる。次に、ウェファ−表
面に酸化膜を５００Å形成する、続いてｐ型層４を形成
するため、ボロンをイオン注入により打ち込む。その
後、１１５０℃で９００分間、窒素中でアニ−ル拡散を
行なう事により、表面濃度約８Ｅ１８／ｃｍ∧３、深さ
約７μｍのｐ型層４が形成される。この様にして接合形
成されたウェファ−にＰｔ、Ａｕ等の重金属を拡散して、
ライフタイムを短くした後、周知のフォトエッチング技
術を用いて、シリコンをメサ型に加工し、表面に保護膜
５を形成する。その後、電極金属Ａ1を表面に、Ｃｒ−
Ｎｉを裏面に形成し、ウェファ−を２ｍｍ□四方のチッ
プに分割して本実施例素子を完成した。Of the various characteristics of the diode, the reverse breakdown voltage is another important characteristic. Generally, when the impurity concentration of the i layer is high, the electric field strength of the pn junction is likely to be high, and the breakdown voltage is low. However, in this embodiment, the i-layer having a low impurity concentration exists ahead of the high impurity-concentration region in contact with the p-type layer, and it is sufficient to adjust the thickness and impurity concentration of both regions. It is possible to obtain a high reverse withstand voltage. The manufacturing method of this diode is as follows.
An n-type silicon substrate wafer-1 having a thickness of 0 mm, a thickness of 400 μm, a resistivity of 0.003 Ω · cm, and a plane orientation (111) is prepared. An n-type high resistance layer is formed on the main surface of the substrate wafer-1,
That is, the i layer 2 (20 Ω · cm) is epitaxially grown to a thickness of 50 μm. Next, the amount of dopant during epitaxial growth is increased to increase the n-type low resistance layer 3 (4.5).
Ω · cm) is grown to 10 μm. Next, an oxide film of 500 Å is formed on the surface of the wafer, and subsequently boron is implanted by ion implantation to form the p-type layer 4. After that, annealing is performed in nitrogen at 1150 ° C. for 900 minutes to form a p-type layer 4 having a surface concentration of about 8E18 / cm 3 and a depth of about 7 μm. Diffusion of heavy metals such as Pt and Au into the wafer thus formed by bonding,
After shortening the life time, silicon is processed into a mesa type by using a well-known photoetching technique to form a protective film 5 on the surface. Then, with the electrode metal A1 on the surface, Cr-
Ni was formed on the back surface, and the wafer was divided into 2 mm square chips to complete the device of this example.
【００１２】図７は、本発明の他の実施例の不純物濃度
分布を示す図である。本構造は、ｉ層の不純物濃度分布
をｐｎ接合に接した側を高く、ｎ型高不純物濃度層側を
低くなるように連続的に変化させたものである。これ
は、ｉ層のエピタキシャル成長中のド−パントの量を連
続的に変化させることで容易に実現できる。 （６） 図８は、本発明の他の実施例の断面構造を示す。これ
は、ｉ層中の高不純物濃度領域ならびにｐ型層領域を、
選択拡散技術を用いて作成した例である。図９は、本発
明の他の実施例の断面構造を示す。ｉ層中の高不純物濃
度領域を複数に分割して設けたものである。この様にｉ
層中の高不純物濃度領域は必ずしもダイオ−ドの断面全
体にある必要はなく断面の一部に設けた場合でも、本実
施例の原理からして同様の効果が得られる。図１０は、
本発明の他の実施例の断面構造を示す。これは、同一主
表面にｐ、ｎ高不純物濃度領域が存在する場合を示す。
以上の説明は低不純物濃度領域ｉ層がｎ型低不純物濃度
領域の場合について説明したが、低不純物濃度領域ｉ層
ｐ型低不純物濃度領域の場合でも同様の効果が得られる
ことは明らかである。FIG. 7 is a diagram showing the impurity concentration distribution of another embodiment of the present invention. In this structure, the impurity concentration distribution of the i layer is continuously changed so that it is higher on the side in contact with the pn junction and lower on the side of the n-type high impurity concentration layer. This can be easily achieved by continuously changing the amount of dopant during epitaxial growth of the i layer. (6) FIG. 8 shows a sectional structure of another embodiment of the present invention. This is because the high impurity concentration region in the i layer and the p-type layer region are
This is an example created using the selective diffusion technique. FIG. 9 shows a sectional structure of another embodiment of the present invention. The high impurity concentration region in the i layer is divided into a plurality of regions. I like this
The high impurity concentration region in the layer does not necessarily have to be in the entire cross section of the diode, and even if it is provided in a part of the cross section, the same effect can be obtained from the principle of this embodiment. Figure 10
5 shows a cross-sectional structure of another embodiment of the present invention. This shows the case where p and n high impurity concentration regions are present on the same main surface.
In the above description, the case where the low impurity concentration region i layer is the n-type low impurity concentration region is described, but it is clear that the same effect can be obtained even when the low impurity concentration region i layer is the p-type low impurity concentration region. .
【００１３】[0013]
【発明の効果】以上の説明から明らかなように本発明に
よればｐｉｎダイオ−ドに関し、特に、逆回復時の逆方
向電流の尖頭値ＩＲＰを小さくすることにより逆回復時
Ｔｒｒを長くしないで、Ｔ２の期間のｄｉ／ｄｔを小さ
くし、ソフトリカバリ−特性のダイオ−ドを提供できる
ので電源装置等に適用して装置の小型化、高効率化、高
周波化に好適である等実用上の効果は大きい。As is apparent from the above description, the present invention relates to a pin diode, and particularly, by reducing the peak value IRP of the reverse current at the time of reverse recovery, the Trr at reverse recovery is not lengthened. Therefore, since di / dt during the period of T2 can be reduced and a diode with a soft recovery characteristic can be provided, it can be applied to a power supply device and the like, which is suitable for downsizing, high efficiency, and high frequency of the device. Has a great effect.
【図１】本発明の一実施例構造図FIG. 1 is a structural diagram of an embodiment of the present invention
【図２】本発明実施例の不純物濃度分布図FIG. 2 is an impurity concentration distribution diagram of an example of the present invention.
【図３】従来構造図[Fig. 3] Conventional structure diagram
【図４】従来構造の不純物濃度分布図FIG. 4 is an impurity concentration distribution map of a conventional structure.
【図５】従来構造の動作説明用の電流、電圧波形図 （７）FIG. 5 is a current and voltage waveform diagram for explaining the operation of the conventional structure (7)
【図６】従来構造及び本発明実施例を比較した電流波形
図FIG. 6 is a current waveform diagram comparing a conventional structure and an example of the present invention.
【図７】本発明の他の実施例の不純物濃度分布図FIG. 7 is an impurity concentration distribution chart of another embodiment of the present invention.
【図８】本発明の他の実施例構造図FIG. 8 is a structural diagram of another embodiment of the present invention.
【図９】本発明の他の実施例構造図FIG. 9 is a structural diagram of another embodiment of the present invention.
【図１０】本発明の他の実施例構造図FIG. 10 is a structural diagram of another embodiment of the present invention.
１ Ｎ型半導体基体（高濃度ｎ型領域） ２ 低不純物濃度領域（真正領域） ３ 高不純物濃度領域 ４ Ｐ型高濃度領域 ５ 保護膜 Ｊ ＰＮ接合 1 N-type semiconductor substrate (high concentration n-type region) 2 Low impurity concentration region (authentic region) 3 High impurity concentration region 4 P-type high concentration region 5 Protective film J PN junction
Claims (3)
度領域及び、前記両領域の間に介在する低不純物濃度領
域よりなるダイオ−ドにおいて、低不純物濃度領域内
に、これと同導電型で、かつ高不純物濃度領域が少なく
とも一つ存在し、この低不純物濃度領域中の高不純物濃
度領域とｐｎ接合が隣接するように形成されたことを特
徴とするダイオ−ド。1. A diode comprising a p-type high impurity concentration region, an n-type high impurity concentration region, and a low impurity concentration region interposed between the both regions, and has the same conductivity in the low impurity concentration region. A diode characterized in that at least one high-impurity-concentration region exists, and the high-impurity-concentration region in the low-impurity-concentration region is formed to be adjacent to the pn junction.
の不純物濃度を、ｐｎ接合に近い側ほど高くした事を特
徴とする請求項１のダイオ−ド。2. The diode according to claim 1, wherein the impurity concentration of the high impurity concentration region in the low impurity concentration region is increased toward the side closer to the pn junction.
度領域及び、前記両領域の間に介在する低不純物濃度領
域よりなるダイオ−ドにおいて、低不純物濃度領域の不
純物濃度をｐｎ接合に近い側ほど高くした事を特徴とす
るダイオ−ド。3. A diode comprising a p-type high impurity concentration region, an n-type high impurity concentration region, and a low impurity concentration region interposed between the both regions, wherein the impurity concentration of the low impurity concentration region is a pn junction. A diode characterized in that the closer it is, the higher it is.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8800794A JPH07273354A (en) | 1994-03-31 | 1994-03-31 | Diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8800794A JPH07273354A (en) | 1994-03-31 | 1994-03-31 | Diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07273354A true JPH07273354A (en) | 1995-10-20 |
Family
ID=13930756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8800794A Pending JPH07273354A (en) | 1994-03-31 | 1994-03-31 | Diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07273354A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003318412A (en) * | 2002-02-20 | 2003-11-07 | Fuji Electric Co Ltd | Semiconductor device and manufacturing method therefor |
| US7102207B2 (en) | 2002-12-03 | 2006-09-05 | Kabushiki Kaisha Toshiba | Semiconductor device having rectifying action |
| KR100695306B1 (en) * | 2001-06-21 | 2007-03-14 | 삼성전자주식회사 | manufacturing method of PIN diode |
| JP2007123932A (en) * | 2001-02-23 | 2007-05-17 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
| WO2009022592A1 (en) * | 2007-08-13 | 2009-02-19 | The Kansai Electric Power Co., Inc. | Soft recovery diode |
| WO2010026653A1 (en) * | 2008-09-05 | 2010-03-11 | 株式会社 東芝 | Memory device |
| US8829519B2 (en) | 2007-09-20 | 2014-09-09 | Mitsubishi Electric Corporation | Semiconductor device |
| JP2016009871A (en) * | 2014-06-26 | 2016-01-18 | アーベーベー・テクノロジー・アーゲー | Reverse conducting power semiconductor device |
-
1994
- 1994-03-31 JP JP8800794A patent/JPH07273354A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007123932A (en) * | 2001-02-23 | 2007-05-17 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
| KR100695306B1 (en) * | 2001-06-21 | 2007-03-14 | 삼성전자주식회사 | manufacturing method of PIN diode |
| JP2003318412A (en) * | 2002-02-20 | 2003-11-07 | Fuji Electric Co Ltd | Semiconductor device and manufacturing method therefor |
| JP4539011B2 (en) * | 2002-02-20 | 2010-09-08 | 富士電機システムズ株式会社 | Semiconductor device |
| US7102207B2 (en) | 2002-12-03 | 2006-09-05 | Kabushiki Kaisha Toshiba | Semiconductor device having rectifying action |
| US7781869B2 (en) | 2002-12-03 | 2010-08-24 | Kabushiki Kaisha Toshiba | Semiconductor device having rectifying action |
| WO2009022592A1 (en) * | 2007-08-13 | 2009-02-19 | The Kansai Electric Power Co., Inc. | Soft recovery diode |
| JP2009049045A (en) * | 2007-08-13 | 2009-03-05 | Kansai Electric Power Co Inc:The | Soft recovery diode |
| US8829519B2 (en) | 2007-09-20 | 2014-09-09 | Mitsubishi Electric Corporation | Semiconductor device |
| WO2010026653A1 (en) * | 2008-09-05 | 2010-03-11 | 株式会社 東芝 | Memory device |
| JP2016009871A (en) * | 2014-06-26 | 2016-01-18 | アーベーベー・テクノロジー・アーゲー | Reverse conducting power semiconductor device |
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