CN111261724A - Layout method of SiC JBS device - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 65
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 62
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000151 deposition Methods 0.000 claims abstract description 17
- 150000002500 ions Chemical class 0.000 claims abstract description 17
- 239000013078 crystal Substances 0.000 claims abstract description 8
- 238000002513 implantation Methods 0.000 claims description 9
- 230000001681 protective effect Effects 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 5
- -1 aluminum ion Chemical class 0.000 claims description 4
- 238000005566 electron beam evaporation Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract description 13
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 210000003850 cellular structure Anatomy 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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Abstract
The invention provides a layout method of a SiC JBS device, which comprises the following steps: growing an epitaxial layer on a crystal face of a silicon carbide substrate, and dividing an active region with a rectangular structure on the epitaxial layer; arranging a terminal protection region at the periphery of the active region, arranging a plurality of P-type regions in the active region, wherein the P-type regions are staggered in multiple rows and columns, injecting ions into each P-type region, and arranging Schottky contact regions among the P-type regions; and depositing an ohmic contact metal layer on the back of the silicon carbide substrate to generate the SiC JBS device. According to the invention, the plurality of P-type regions are distributed in the SiC JBS device in a staggered arrangement of multiple rows and multiple columns, so that the reverse breakdown characteristic of the SiC JBS device is ensured, the area of a Schottky barrier region is increased, and the conduction capability is improved.
Description
Technical Field
The invention relates to the field of semiconductor devices and manufacturing thereof, in particular to a layout method of a SiC JBS device.
Background
The high power Diode is an important branch of semiconductor power electronic devices, and mainly includes Schottky Barrier Diode (SBD), Junction Barrier Schottky Diode (JBS), and PiN Diode. In the field of high-voltage and high-current silicon carbide (SiC), the SiC SBD diode has low forward conduction voltage drop, so the use is very wide, but the existence of the Schottky barrier enables the reverse leakage current ratio of the SBD diode to be larger, and the high-voltage application of the SBD diode is limited. Although the SiC PiN diode has a high blocking voltage, the energy loss is large when the SiC PiN diode is reversely recovered due to the conductance modulation effect.
Therefore, in order to solve the above problems, a junction barrier schottky diode structure is generally adopted internationally, wherein a PN junction is integrated in a SiC schottky diode, and the junction barrier schottky diode combines the low forward conduction voltage drop of the schottky diode and the high blocking voltage characteristic of a PiN diode, and has a low turn-on voltage, a high breakdown voltage, a low reverse leakage current, a high switching speed and the like, so that the junction barrier schottky diode structure has a wide application prospect in the field of high-voltage and high-speed SiC high-power diodes.
When the JBS diode is forward biased, because the turn-on voltage of the Schottky barrier is lower than the turn-on voltage of the PN junction, the Schottky region is firstly conducted, and current flows through the Schottky contact between the P + islands, so that forward conducting current is formed; with the increase of the forward bias voltage, the PN junction is conducted, and the conducting resistance of the JBS diode under the forward high current density is reduced by the conductivity modulation effect of the PN junction, so that the forward voltage drop of the device is reduced. When the JBS is reversely biased, a depletion region formed by the PN junction diffuses towards the Schottky contact region, the depletion region is communicated under certain reverse bias voltage, a potential barrier is formed in the Schottky contact region, so that the depletion region develops towards an N + substrate along with the increase of the reverse bias voltage, the Schottky junction is shielded outside a high electric field by the depletion layer to a certain extent, the Schottky barrier reduction effect is reduced, and the reverse leakage current is greatly reduced. At present, in order to increase the on-state current of a device, a multi-cell parallel connection mode is generally adopted, different cell shapes and layouts can affect breakdown voltage and on-state resistance, but the common square array cannot effectively reduce the Schottky surface electric field in the middle area due to the fact that the diagonal P + interval distance is larger than the adjacent P + interval distance, and the pinch-off capability of the common square array on the Schottky junction during reverse bias is affected; the strip-shaped structure is difficult to achieve an ideal uniformity degree from the aspect of processing technology, so that the SiC JBS device which is easy to realize in the aspect of technology and high in precision is worthy of research.
Disclosure of Invention
In order to solve the problem of effective shielding of a reverse bias time depletion layer on a Schottky junction in the prior art, the invention provides a layout method of a SiC JBS device, which can effectively ensure the reverse breakdown characteristic of the device, increase the area of a Schottky barrier region and improve the conducting capacity of unit chip area compared with the traditional strip-shaped cellular structure.
The technical scheme provided by the invention is as follows: a SiC JBS device, comprising:
the semiconductor device comprises an active region and a terminal protection region, wherein the terminal protection region is arranged on the periphery of the active region, and the active region comprises a plurality of P-type regions and Schottky contact regions; the active region is of a rectangular structure;
the plurality of P-type regions are arranged in a staggered manner in multiple rows and multiple columns, and the Schottky contact regions are filled among the P-type regions.
Preferably, the P-type region comprises a complete P-type region and a semi P-type region;
each complete P-type region has the same structure, equal area and equal height, and the geometric center distance between any adjacent complete P-type regions is equal;
the half P-type regions are distributed at the end parts of rows or columns, so that the active regions form a rectangular structure, and the interval between the half P-type regions and the adjacent complete P-type regions is consistent with that between the adjacent complete P-type regions.
Preferably, the shape of the complete P-type region is rectangular.
Preferably, the complete P-type region is square, and the staggered arrangement mode is a 'pin' -shaped arrangement.
Preferably, the side length of the square is between 0.1 and 100 mu m.
Preferably, the geometric center distance between any adjacent complete P-type regions is 0.3-300 μm.
Preferably, the structure of the half P-type region is a structure obtained by cutting out the whole P-type region structure along any edge in parallel.
Preferably, the SiC JBS device is based on a silicon carbide substrate.
Preferably, a Schottky metal layer is formed by depositing Ti5nm/Ni450nm/Al 3 μm on the Schottky contact region.
Preferably, the concentration of the implanted P-type region is 5 × 1018cm-3The aluminum ion of (2).
Based on the same inventive concept, the invention also provides a layout method of the SiC JBS device, which comprises the following steps:
growing an epitaxial layer on a crystal face of a silicon carbide substrate, and dividing an active region with a rectangular structure on the epitaxial layer;
arranging a terminal protection region at the periphery of the active region, arranging a plurality of P-type regions in the active region, wherein the P-type regions are staggered in multiple rows and columns, injecting ions into each P-type region, and arranging Schottky contact regions among the P-type regions;
and depositing an ohmic contact metal layer on the back of the silicon carbide substrate to generate the SiC JBS device.
Preferably, the implanting ions into each P-type region includes:
photoetching a P-type region injection window on the epitaxial layer;
and implanting ions into the P-type region based on the P-type region implantation window.
Preferably, the depth of the photoetching P-type region injection window is 0.8 μm.
Preferably, the implanting ions into the P-type region includes: the injection concentration is 5X 10 at 500 deg.C18cm-3The aluminum ion of (2).
Preferably, the implanting ions into each P-type region, and disposing schottky contact regions between the P-type regions, includes:
and after ions are injected into the P-type region, a Schottky metal layer is deposited on the epitaxial layer.
Preferably, the depositing a schottky metal layer on the epitaxial layer includes:
and depositing the Schottky metal layer on the epitaxial layer through an electron beam evaporation process, injecting the Schottky metal layer at the temperature of 300-800 ℃ under the protection of a protective mask and an inert atmosphere, and annealing for 5-10 minutes.
Preferably, the Schottky metal layer is Ti5nm/Ni450nm/Al 3 μm.
Preferably, the depositing an ohmic contact metal layer on the back of the silicon carbide substrate comprises:
and depositing an ohmic contact metal layer on the back surface of the silicon carbide substrate through a metal sputtering process, injecting the ohmic contact metal layer at 1500-2100 ℃ under the protection of a protective mask and inert atmosphere, and annealing for 5-30 minutes.
Preferably, the ohmic contact metal layer is Ti5nm/Ni450 nm.
Preferably, the silicon carbide substrate is nitrogen-doped 4H-SiC, the resistivity is 0.02 omega cm, and the doping concentration is 1 x 1019cm-3The thickness was 350. mu.m.
Preferably, the active region is provided with a plurality of P-type regions, and the P-type regions are staggered in multiple rows and multiple columns, and the P-type regions include:
on the active region: arranging complete P-type regions with equal geometric center distance and equal area in staggered arrangement in multiple rows and columns, and arranging semi-P-type regions at the ends of the rows or columns so that the active region forms a rectangular structure, wherein the interval between the semi-P-type region and the adjacent complete P-type region is consistent with the interval between the adjacent complete P-type regions;
wherein the complete P-type region and the semi P-type region are the P-type regions.
Preferably, the complete P-shaped area is arranged to be a square with the side length of 0.1-20 mu m, and the layout mode is a 'pin' shape.
Preferably, the geometric center distance of the arrangement is 0.3-40 μm.
Compared with the prior art, the invention has the beneficial effects that:
according to the technical scheme provided by the invention, an epitaxial layer grows on a crystal face of a silicon carbide substrate, and an active region with a rectangular structure is divided on the epitaxial layer; arranging a terminal protection region at the periphery of the active region, arranging a plurality of P-type regions in the active region, wherein the P-type regions are staggered in multiple rows and columns, injecting ions into each P-type region, and arranging Schottky contact regions among the P-type regions; the SiC JBS device is generated by depositing the ohmic contact metal layer on the back of the silicon carbide substrate, the SiC JBS device with a plurality of P-type regions arranged in a staggered manner in multiple rows and multiple columns can be manufactured by the layout method provided by the scheme, the process is better realized when the layout method is used, the layout method is in a circular or hexagonal structure relative to the P-type regions, the process uniformity is higher when the layout method is in a strip structure relative to the P-type regions, the area of a Schottky barrier region is increased, and the conduction capability of the unit chip area is improved; compared with a p-type region which is in a square array structure, the reverse breakdown characteristic of the device can be effectively ensured.
The technical scheme provided by the invention provides the P-type regions which are arranged in a staggered manner in multiple rows and multiple columns, the complete P-type regions adopt a square structure, especially a reversed-shaped array, the shielding effect of PN junctions on Schottky junctions when the device is reversely biased is ensured, the reverse breakdown voltage of the SiC JBS device is improved, the area of Schottky barrier regions is increased, and the forward conduction capability is improved.
According to the technical scheme provided by the invention, the Schottky contact area is increased to the greatest extent and the forward on-resistance is reduced on the premise of ensuring the effectiveness of a reverse shielding electric field in the active region of the SiC JBS device, so that low on-voltage drop is obtained while reverse leakage current is not increased.
Drawings
FIG. 1 is a flow chart of a layout method of a SiC JBS device provided by the invention;
FIG. 2 is a schematic view of the structure of a silicon carbide epitaxial wafer in an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an ion implanted P-type region according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a "PIN" type arrangement in an embodiment of the present invention;
FIG. 5 is a schematic diagram of a Schottky metal layer deposition according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of an ohmic contact metal layer deposited according to an embodiment of the present invention;
01-ohmic contact metal layer; 02-a silicon carbide substrate; 03-an epitaxial layer; a 04-P type region; 05-schottky contact layer.
Detailed Description
For a better understanding of the present invention, reference is made to the following description taken in conjunction with the accompanying drawings and examples.
Example 1:
the invention aims to provide a SiC JBS device, which mainly comprises an arrangement of a P-type region in an active region, and compared with the traditional layout method, the device reverse blocking voltage is ensured, meanwhile, the area of a Schottky contact region is increased as much as possible, the process is easy to realize, and the reasonable compromise among breakdown voltage, on-resistance characteristics and process difficulty is realized.
The semiconductor device comprises an active region and a terminal protection region, wherein the terminal protection region is arranged on the periphery of the active region, and the active region comprises a plurality of P-type regions and Schottky contact regions; the active region is of a rectangular structure;
the plurality of P-type regions are arranged in a staggered manner in multiple rows and multiple columns, and the Schottky contact regions are filled among the P-type regions.
The P-type region comprises a complete P-type region and a semi P-type region;
each complete P-type region has the same structure, equal area and equal height, and the geometric center distance between any adjacent complete P-type regions is equal;
the semi-P type regions are distributed at the ends of the rows or columns, so that the active regions form a rectangular structure, and the interval between the semi-P type region and the adjacent complete P type region is consistent with the interval between the adjacent complete P type regions.
The structure of the semi-P-type region is a structure which is obtained by cutting out the whole P-type region structure along any edge in parallel.
The shape of the complete P-type region is rectangular, the shape of the complete P-type region is preferably square, the side length w is 0.1-100 mu m, six P-type regions with the same area are uniformly distributed on the periphery of each complete P-type region, the geometric center distances of any adjacent ion implantation regions are equal and are all 0.3-200 mu m, and the best layout mode is in a shape of Chinese character pin;
all the P-type regions have the same implantation depth and doping concentration;
the SiC JBS device in this embodiment is based on a silicon carbide substrate.
And depositing Ti5nm/Ni450nm/Al 3 μm on the Schottky contact region to form a Schottky metal layer.
Implanted in the P-type region with a concentration of 5 × 1018cm-3The aluminum ion of (2).
Therefore, the invention provides a SiC JBS device which is provided with a plurality of rows and columns of P-type regions which are staggered, in particular to a pin-shaped array, wherein the complete P-type regions adopt a square structure, and the process is better realized compared with a circular structure and a hexagonal structure; compared with a strip-shaped structure, the process uniformity is higher, the area of a Schottky barrier region is increased, and the conducting capacity of the unit chip area is improved; compared with a square array, the reverse breakdown characteristic of the device can be effectively ensured.
Example 2
Based on the same inventive concept, the present embodiment further provides a layout method of a SiC JBS device, which is suitable for a manufacturing process, as shown in fig. 1, and includes:
step S1, growing an epitaxial layer on a crystal face of the silicon carbide substrate, and dividing an active region with a rectangular structure on the epitaxial layer;
step S2, arranging a plurality of P-type regions in the active region, wherein the P-type regions are staggered in multiple rows and multiple columns, injecting ions into each P-type region, and arranging Schottky contact regions among the P-type regions;
and step S3, depositing an ohmic contact metal layer on the back surface of the silicon carbide substrate to generate the SiC JBS device.
The specific layout method of the SiC JBS device specifically comprises the following steps:
step S1, growing an epitaxial layer on a crystal plane of the silicon carbide substrate, and dividing an active region of a rectangular structure on the epitaxial layer, including:
1) as shown in fig. 2, taking an n-type heavily doped silicon carbide substrate 02 as an example, an epitaxial wafer of an n-type silicon carbide epitaxial layer 03 is grown on the (0001) crystal plane thereof.
The silicon carbide substrate 101 was nitrogen (N) -doped 4H-SiC, had a resistivity of 0.02. omega. cm and a doping concentration of 1X 1019cm-3350 μm thick; the silicon carbide epitaxial layer 03 is N-type nitrogen (N) -doped 4H-SiC with the same crystal orientation as the substrate and the doping concentration of 3 multiplied by 1015cm-3The thickness of the epitaxial layer was 40 μm.
Step S2, disposing a plurality of P-type regions in the active region, the P-type regions being staggered in multiple rows and multiple columns, implanting ions into each P-type region, and disposing schottky contact regions between the P-type regions, includes:
the complete P-type region and the semi-P-type region are the P-type regions;
on the active region: arranging complete P-type regions with equal geometric center distance and equal area in staggered arrangement in multiple rows and columns, and arranging semi-P-type regions at the ends of the rows or columns so that the active region forms a rectangular structure, wherein the interval between the semi-P-type region and the adjacent complete P-type region is consistent with the interval between the adjacent complete P-type regions; the distance between the geometric centers of the arrangement is 0.3-40 μm.
And arranging the complete P-shaped area into a square with the side length of 0.1-20 mu m, wherein the layout mode is in a Chinese character pin shape. The structure of the semi-P-type region is a structure which is obtained by cutting out the whole P-type region structure along any edge in parallel.
2) As shown in fig. 3, a P-type region implantation window is photoetched on the epitaxial layer 03, and the P-type region implantation is aluminum (Al) ion implantation with the temperature of 500 ℃, the implantation depth of 0.8 μm and the implantation concentration of 5 × 1018cm-3. After the ion implantation process, all the P-type regions are implanted at 1500-2100 ℃ for 5-30 minutes under the protection of a protective mask and an inert atmosphere.
3) As shown in fig. 4, all the P-type regions 04 are equal in area and square in shape, the side length w is 0.1-100 μm, preferably 0.1-20 μm, six P-type regions with the same area are uniformly arranged on the periphery of each P-type region, the geometric center distances of any adjacent P-type regions are equal and are 0.3-200 μm, preferably 0.3-40 μm;
4) as shown in fig. 5, a schottky metal layer 05, which is Ti5nm/Ni450nm/Al 3 μm, is formed on the active region, and is implanted at 300-800 ℃ for 5-10 minutes under the protection of a protective mask and an inert atmosphere after an electron beam evaporation process.
Step S3, depositing an ohmic contact metal layer on the back of the silicon carbide substrate to generate the SiC JBS device, which comprises the following steps:
5) as shown in FIG. 6, an ohmic contact metal layer 01 of Ti5nm/Ni450nm is deposited on the back surface of the silicon carbide substrate, and after a metal sputtering process, implantation is performed at 1500-2100 ℃ under the protection of a protective mask and an inert atmosphere, and then annealing is performed for 5-30 minutes.
The SiC JBS device generated by the SiC JBS device layout method provided by the invention increases the Schottky contact area to the maximum extent and reduces the forward on-resistance on the premise of ensuring the effectiveness of a reverse shielding electric field, thereby obtaining low on-voltage drop without increasing reverse leakage current.
It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
For the sake of clarity and brevity, actual embodiments are not limited to the features described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with industry-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that the foregoing improved results, even if highly complex and time-consuming, will nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.
Claims (15)
1. A layout method of a SiC JBS device is characterized by comprising the following steps:
growing an epitaxial layer on a crystal face of a silicon carbide substrate, and dividing an active region with a rectangular structure on the epitaxial layer;
arranging a terminal protection region at the periphery of the active region, arranging a plurality of P-type regions in the active region, wherein the P-type regions are staggered in multiple rows and columns, injecting ions into each P-type region, and arranging Schottky contact regions among the P-type regions;
and depositing an ohmic contact metal layer on the back of the silicon carbide substrate to generate the SiC JBS device.
2. The method of claim 1, wherein the disposing a plurality of P-type regions within the active region, the plurality of P-type regions being staggered in rows and columns comprises:
on the active region: arranging complete P-type regions with equal geometric center distance and equal area in staggered arrangement in multiple rows and columns, and arranging semi-P-type regions at the ends of the rows or columns so that the active region forms a rectangular structure, wherein the interval between the semi-P-type region and the adjacent complete P-type region is consistent with the interval between the adjacent complete P-type regions;
wherein the complete P-type region and the semi P-type region are the P-type regions.
3. The method of claim 2, wherein the structure of the semi-P-type region is a structure taken in parallel along any edge in the complete P-type region structure.
4. The method as claimed in claim 2, wherein the complete P-shaped region is arranged in a square shape with a side length of 0.1-20 μm in a manner of a Chinese character pin.
5. The SiC JBS device of claim 4, wherein the square has sides arranged between 0.1 to 100 μm.
6. The method of claim 2, wherein the geometric center distance is arranged between 0.3 and 40 μm.
7. The method of claim 1, wherein said implanting ions into each P-type region comprises:
photoetching a P-type region injection window on the epitaxial layer;
and implanting ions into the P-type region based on the P-type region implantation window.
8. The method of claim 7, wherein the photolithographic P-type region implantation window has a depth of 0.8 μm.
9. The method of claim 7, wherein said implanting ions into said P-type region comprises: the injection concentration is 5X 10 at 500 deg.C18cm-3The aluminum ion of (2).
10. The method of claim 7, wherein implanting ions into each P-type region to dispose schottky contact regions between the P-type regions comprises:
and after ions are injected into the P-type region, a Schottky metal layer is deposited on the epitaxial layer.
11. The method of claim 10, wherein depositing the schottky metal layer on the epitaxial layer comprises:
and depositing the Schottky metal layer on the epitaxial layer through an electron beam evaporation process, injecting the Schottky metal layer at the temperature of 300-800 ℃ under the protection of a protective mask and an inert atmosphere, and annealing for 5-10 minutes.
12. The method of claim 11, wherein the schottky metal layer is Ti5nm/Ni450nm/Al 3 μ ι η.
13. The method of claim 1, wherein depositing an ohmic contact metal layer on the back side of the silicon carbide substrate comprises:
and depositing an ohmic contact metal layer on the back surface of the silicon carbide substrate through a metal sputtering process, injecting the ohmic contact metal layer at 1500-2100 ℃ under the protection of a protective mask and inert atmosphere, and annealing for 5-30 minutes.
14. The method of claim 13, wherein the ohmic contact metal layer is Ti5nm/Ni450 nm.
15. The method of claim 1, wherein the silicon carbide substrate is nitrogen doped 4H-SiC, has a resistivity of 0.02 Ω -cm and a doping concentration of 1 x 1019cm-3The thickness was 350. mu.m.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113990934A (en) * | 2021-10-29 | 2022-01-28 | 西安微电子技术研究所 | SiC JBS cellular structure and preparation method |
| CN114284343A (en) * | 2021-12-23 | 2022-04-05 | 电子科技大学 | Silicon carbide junction barrier Schottky diode suitable for high temperature environment |
| CN114284344A (en) * | 2021-12-23 | 2022-04-05 | 电子科技大学 | Silicon carbide junction barrier Schottky diode for optimizing current distribution |
| WO2024130915A1 (en) * | 2022-12-19 | 2024-06-27 | 深圳腾睿微电子科技有限公司 | Jbs square cell structure and corresponding silicon carbide device |
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2018
- 2018-11-30 CN CN201811453239.9A patent/CN111261724A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113990934A (en) * | 2021-10-29 | 2022-01-28 | 西安微电子技术研究所 | SiC JBS cellular structure and preparation method |
| CN113990934B (en) * | 2021-10-29 | 2023-07-28 | 西安微电子技术研究所 | SiC JBS cell structure and preparation method |
| CN114284343A (en) * | 2021-12-23 | 2022-04-05 | 电子科技大学 | Silicon carbide junction barrier Schottky diode suitable for high temperature environment |
| CN114284344A (en) * | 2021-12-23 | 2022-04-05 | 电子科技大学 | Silicon carbide junction barrier Schottky diode for optimizing current distribution |
| CN114284343B (en) * | 2021-12-23 | 2023-04-07 | 电子科技大学 | Silicon carbide junction barrier Schottky diode suitable for high temperature environment |
| CN114284344B (en) * | 2021-12-23 | 2023-04-28 | 电子科技大学 | Silicon carbide junction barrier Schottky diode for optimizing current distribution |
| WO2024130915A1 (en) * | 2022-12-19 | 2024-06-27 | 深圳腾睿微电子科技有限公司 | Jbs square cell structure and corresponding silicon carbide device |
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