CN117153855B - Semiconductor structure of back-illuminated image sensor and manufacturing method thereof - Google Patents
Semiconductor structure of back-illuminated image sensor and manufacturing method thereof Download PDFInfo
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- CN117153855B CN117153855B CN202311412417.4A CN202311412417A CN117153855B CN 117153855 B CN117153855 B CN 117153855B CN 202311412417 A CN202311412417 A CN 202311412417A CN 117153855 B CN117153855 B CN 117153855B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 83
- 238000000034 method Methods 0.000 claims description 60
- 238000005137 deposition process Methods 0.000 claims description 25
- 239000007789 gas Substances 0.000 claims description 12
- 238000006243 chemical reaction Methods 0.000 claims description 9
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 8
- 239000001307 helium Substances 0.000 claims description 8
- 229910052734 helium Inorganic materials 0.000 claims description 8
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 8
- 230000007547 defect Effects 0.000 abstract description 25
- 238000002955 isolation Methods 0.000 description 15
- 238000010586 diagram Methods 0.000 description 10
- 238000005530 etching Methods 0.000 description 10
- 238000000151 deposition Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 239000012459 cleaning agent Substances 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 1
- VKJLWXGJGDEGSO-UHFFFAOYSA-N barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[Ti+4].[Ba+2] VKJLWXGJGDEGSO-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical class [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a semiconductor structure of a back-illuminated image sensor and a manufacturing method thereof, belonging to the technical field of semiconductors. The semiconductor structure of the back-illuminated image sensor includes: a substrate; a plurality of deep trenches disposed within the substrate; a lining oxide layer arranged on the side wall and the bottom of the deep trench and the substrate; the high dielectric medium layer is arranged on the lining oxide layer; the first oxide layer is arranged on the high-dielectric medium layer, the first oxide layer is filled to the top of the deep trench, an air gap is formed in the deep trench by the first oxide layer, and the top of the air gap is lower than the top of the deep trench; and the second oxide layer is formed on the first oxide layer, and the pressure type after the first oxide layer and the second oxide layer are combined is compressive stress. The semiconductor structure of the back-illuminated image sensor and the manufacturing method thereof provided by the invention improve the bubble defects on the surfaces of the substrate and the film.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor structure of a back-illuminated image sensor and a manufacturing method thereof.
Background
With the continuous increase of the integration level of the internal components of the integrated circuit, the distance between the adjacent components is shortened, the possibility of electronic interference between the adjacent components is also increased, and the deep trench isolation technology is widely applied in the present semiconductor technology, so that various devices such as analog, digital, high voltage and the like are integrated together without causing interference. For example, in a back-illuminated image sensor, a deep trench isolation structure is used to isolate the pixel region, so as to obtain a better imaging effect. However, in the deep trench isolation technology, the problem of poor yield of deep trench isolation is easy to occur, so that the chip yield is low, and the development of the semiconductor technology is not facilitated.
Disclosure of Invention
The invention aims to provide a semiconductor structure of a back-illuminated image sensor and a manufacturing method thereof, which are used for reducing bubble defects in the formation process of deep trenches and improving the yield of the semiconductor structure, thereby improving the performance and yield of semiconductor devices.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention also provides a semiconductor structure of the back-illuminated image sensor, which at least comprises:
a substrate;
a plurality of deep trenches disposed within the substrate;
a lining oxide layer arranged on the side wall and the bottom of the deep trench and the substrate;
the high dielectric medium layer is arranged on the lining oxide layer;
the first oxide layer is arranged on the high-dielectric medium layer, the first oxide layer is filled to the top of the deep trench, an air gap is formed in the deep trench by the first oxide layer, and the top of the air gap is lower than the top of the deep trench;
the second oxide layer is formed on the first oxide layer, the stress types of the second oxide layer and the first oxide layer are opposite, and the pressure type after the first oxide layer and the second oxide layer are combined is compressive stress.
The stress type of the first oxide layer is tensile stress.
In an embodiment of the present invention, a stress type of the second oxide layer is compressive stress.
The invention also provides a manufacturing method of the semiconductor structure of the back-illuminated image sensor, which at least comprises the following steps:
providing a substrate;
forming a plurality of deep trenches within the substrate;
forming a liner oxide layer on the side wall and the bottom of the deep trench and the substrate;
forming a high dielectric layer on the lining oxide layer
Forming a first oxide layer on the high dielectric medium layer through a first deposition process, wherein the first oxide layer is filled to the top of the deep trench, and an air gap is formed in the deep trench by the first oxide layer;
baking the first oxide layer;
and forming a second oxide layer on the first oxide layer through a second deposition process, wherein the stress of the second oxide layer is opposite to that of the first oxide layer, and the pressure type after the first oxide layer and the second oxide layer are combined is compressive stress.
In an embodiment of the present invention, the first deposition process is a high aspect ratio process, and the reaction temperature of the first deposition process is 380 ℃ to 400 ℃.
In one embodiment of the present invention, the baking process includes: and introducing gas with set flow rate at a preset baking temperature, and finishing the baking process treatment of the first oxide layer after reacting for a preset time.
In an embodiment of the present invention, the baking temperature is 300 ℃ to 350 ℃.
In an embodiment of the present invention, the gas includes helium, and the flow rate of the gas is 8000sccm to 10000sccm.
In an embodiment of the present invention, the second deposition process is a deposition process of a plasma enhanced tetraethyl orthosilicate layer, and a reaction temperature of the second deposition process is 300 ℃ to 350 ℃.
In summary, the present invention provides a semiconductor structure of a backside illuminated image sensor and a method for manufacturing the same, which have the unexpected effects of reducing water-oxygen residues of a deposited film prepared by a high aspect ratio process, improving the quality of the deposited film prepared by the high aspect ratio process, avoiding the subsequent generation of bubble defects, and improving the performance of a semiconductor device prepared subsequently. The film stress can be expressed as compressive stress, so that the problem of poor adhesion between the film and the surface of the substrate due to tensile stress is avoided, and the generation of bubble defects of the film is reduced. The prepared deep trench isolation structure can improve optical and electrical isolation between adjacent components, reduce dark current crosstalk, parasitic light pollution and other conditions, and improve the reliability of the semiconductor structure. The waste of resources is reduced, the production time is saved, and the production efficiency is improved while the water and oxygen residues are better removed.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a substrate and a substrate oxide layer on the substrate in an embodiment of the invention.
FIG. 2 is a schematic diagram of a photoresist layer and an opening formed in an embodiment of the invention.
Fig. 3 is a schematic diagram of a deep trench formed in an embodiment of the invention.
FIG. 4 is a schematic diagram of removing an oxide layer of a substrate according to an embodiment of the invention.
FIG. 5 is a schematic illustration of forming a liner oxide layer in accordance with an embodiment of the present invention.
FIG. 6 is a schematic diagram illustrating a high dielectric layer formed according to an embodiment of the invention.
FIG. 7 is a schematic illustration of forming a first oxide layer and an air gap in accordance with an embodiment of the present invention.
FIG. 8 is a schematic diagram illustrating formation of a second oxide layer according to an embodiment of the invention.
Fig. 9 is a schematic view of a substrate defect after forming a first oxide layer on the substrate by a first deposition process only.
Fig. 10 is a bubble defect diagram of the process corresponding to the substrate in fig. 9.
Fig. 11 is a schematic view of a substrate defect after forming a first oxide layer on a substrate by a first deposition process and directly after forming a second oxide layer by a second deposition process.
Fig. 12 is a bubble defect diagram of the process corresponding to the substrate in fig. 11.
FIG. 13 is a schematic diagram of a substrate defect prepared by the method for fabricating a semiconductor structure of a backside illuminated image sensor according to an embodiment of the present invention
FIG. 14 is a diagram of bubble defects corresponding to the substrate of FIG. 13 according to an embodiment of the present invention.
FIG. 15 is a graph showing the stress variation lines after bonding the first oxide layer and the second oxide layer under different baking process conditions according to various embodiments of the present invention.
Description of the reference numerals:
10. a substrate; 11. a substrate oxide layer; 12. a photoresist layer; 13. an opening; 20. deep trenches; 21. lining an oxide layer; 22. a high dielectric layer; 23. a first oxide layer; 24. an air gap; 25. and a second oxide layer.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the present invention, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the indicated apparatus or element must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.
Referring to fig. 1 to 8, the present invention provides a semiconductor structure of a backside illuminated image sensor and a method for manufacturing the same, wherein the semiconductor structure of the backside illuminated image sensor includes a substrate 10, an inner liner oxide layer 21, a high dielectric layer 22, a first oxide layer 23, a second oxide layer 25, and the like. Wherein the liner oxide layer 21 covers, for example, the sidewalls and bottom of the deep trench 20 and the substrate 10, and the high dielectric layer 22 is disposed, for example, on the liner oxide layer 21. The first oxide layer 23 is disposed in the substrate 10 and the deep trench 20, for example, fills the deep trench 20, and an air gap 24 is disposed in the first oxide layer 23, the second oxide layer 25 is covered on the first oxide layer 23, and the first oxide layer 23 and the second oxide layer 25 are opposite in stress, so that film bubble defects in the deep trench isolation structure are reduced. The semiconductor structure of the back-illuminated image sensor and the manufacturing method thereof provided by the invention have the advantages that the performance of a semiconductor device can be improved, the semiconductor structure can be widely applied to chips of different types, and the manufacturing yield of the chips is improved.
Referring to fig. 1, in an embodiment of the present invention, a plurality of semiconductor devices are disposed on a substrate 10, and the present invention is not limited to the types of semiconductor devices. The semiconductor device is one or several semiconductor devices such as a field effect transistor (Field Effect Transistor, FET), a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a complementary Metal Oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS), an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), a Thyristor (Thyristor), a charge-coupled device (Charge Coupled Device, CCD image sensor), a constant voltage Diode, a high frequency Diode, a Light-Emitting Diode (LED), a gate-Light-closing Thyristor (Gate Turn off Thyristor, GTO), a digital signal processing device (Digital Signal Processor, DSP), a high-speed recovery Diode (Fast Recovery Diode, FRD), a high-speed high-efficiency rectifier Diode (Figh Efficiency Diode, HED), a Light triggering Thyristor (Light Triggered Thyristor, LTT), a Photo Relay (Photo Relay), or a microprocessor (Micro Processor), and the like, and the semiconductor device can be specifically selected during the manufacturing process. In this embodiment, the semiconductor device is, for example, a CMOS image sensor, and the photosensitive region in the CMOS image sensor is isolated by a deep trench isolation structure.
Referring to fig. 1, in an embodiment of the present invention, a substrate 10 is provided, and the material of the substrate 10 may be any material suitable for forming a CMOS image sensor, for example, a semiconductor material formed by silicon carbide (SiC), indium phosphide (InP), gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon germanium (GeSi), sapphire, silicon wafer or other III/V compounds, and the like, and further includes a stacked structure formed by these semiconductor materials, or a silicon on insulator, a silicon on insulator stacked, a silicon germanium on insulator, a germanium on insulator, and the like. The present invention is not limited to the kind, shape and thickness of the substrate 10, and may be flexibly set according to the requirements, and the substrate 10 is set according to the type of semiconductor device and actual production conditions, for example. In this embodiment, the substrate 10 is, for example, a doped epitaxial layer silicon wafer, and the doping type may be P-type or N-type.
Referring to fig. 1, in an embodiment of the present invention, a substrate oxide layer 11 is formed on a substrate 10, where the substrate oxide layer 11 is made of a dense silicon oxide, and in this embodiment, the substrate 10 is placed in a reaction chamber with a temperature of 300 ℃ to 400 ℃ and a pressure of 10mT to 100mT, for example, and a radio frequency power of 1KW to 3KW, for example, and oxygen is introduced, and the flow rate of the oxygen is 120mL/min to 330mL/min, for example, by selectively decoupling plasma oxidation (Decoupled Plasma Oxidation, DPO) to form the substrate oxide layer 11. The surface of the substrate 10 reacts with the oxygen radicals formed to form decoupled plasma oxide, i.e., the oxygen radicals react with silicon to form a silicon dioxide substrate oxide layer 11. The thickness of the substrate oxide layer 11 is, for example, 10nm to 50nm, specifically, 12nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, or the like. By forming the substrate oxide layer 11 on the substrate 10, the substrate 10 is prevented from being damaged during subsequent removal or etching operations, etc., as a protective structure for the substrate 10.
Referring to fig. 1 to 3, in an embodiment of the present invention, after forming a substrate oxide layer 11, a photoresist layer 12 is formed on the substrate oxide layer 11, the photoresist layer 12 is formed by spin coating or auto spraying, and a plurality of openings 13 are formed on the photoresist layer 12 through an exposure and development process, and the openings 13 are used to locate the deep trenches 20. The substrate 10 is then etched, for example, by selecting a dry etching process, a wet etching process, or an etching method in which the dry etching process and the wet etching process are combined. In this embodiment, for example, the substrate 10 and the substrate oxide layer 11 are etched by using one-step etching, the substrate oxide layer 11 is etched by using the photoresist layer 12 as a mask, and after the etching of the substrate oxide layer 11 is completed, the substrate 10 is etched by changing etching gas or wet etching liquid. After the etching is completed, the photoresist layer 12 is removed to form the deep trench 20, the depth-to-width ratio of the deep trench 20 is (2-30): 1, and the specific depth-to-width ratio of the deep trench 20 is set according to actual production conditions.
Referring to fig. 2 to 4, after forming the deep trench 20, the photoresist layer 12 is removed, and the substrate oxide layer 11 is removed, for example, by a dry etching process or a wet etching process. In this embodiment, for example, a wet etching process is selected for removal, and the etching solution is selected from phosphoric acid, hydrofluoric acid, a buffer etchant, an aluminum etchant, nitric acid, or the like, for example, and a dilute hydrofluoric acid etching solution is selected for etching for a predetermined time to remove the substrate oxide layer 11. In other embodiments, the substrate oxide layer 11 is removed, again for example, by selective dry etching. After removing the substrate oxide layer 11, the substrate 10 is cleaned with a cleaning agent, for example, a sulfuric acid cleaning agent is selected, and the sulfuric acid cleaning agent is a mixture of sulfuric acid and hydrogen peroxide, wherein the ratio of the sulfuric acid to the hydrogen peroxide is, for example, 5:1. The substrate 10 is reacted at a temperature of, for example, 125 c for a predetermined time to remove the photoresist or organic matter remaining on the surface of the substrate 10.
Referring to fig. 4 to 5, in an embodiment of the present invention, after removing the substrate oxide layer 11, a liner oxide layer 21 is formed on the sidewall, top and substrate 10 of the deep trench 20, and the liner oxide layer 21 is made of a material such as silicon oxide, in this embodiment, a decoupling plasma oxidation process is selected to form the liner oxide layer 21, specifically, the substrate 10 is placed in a reaction chamber with a temperature of 300 ℃ to 400 ℃ and a pressure of 10mT to 100mT, for example, and a radio frequency power of 1KW to 3KW, and oxygen is introduced, for example, with a flow rate of 120mL/min to 330mL/min. The substrate 10 and the surface of the deep trench 20 react with the formed oxygen radicals to form decoupling plasma oxide, namely, the oxygen radicals react with silicon to form a silicon dioxide lining oxide layer 21, and by the method, purer oxygen radicals can be formed, the quality of the generated lining oxide layer 21 is better, and the defects of the surface of the deep trench 20 are repaired. The thickness of the liner oxide layer 21 is set according to the specific production situation, for example. By forming the liner oxide layer 21 on the side wall, the top and the substrate 10 of the deep trench 20, the defects generated by etching when the substrate 10 forms the deep trench 20 are repaired, and the performance of the semiconductor device manufactured later is improved.
Referring to fig. 5 to 6, in an embodiment of the present invention, after forming the liner oxide layer 21, a high dielectric layer 22 is further formed on the liner oxide layer 21, wherein the high dielectric layer 22 is a high-K dielectric material such as hafnium oxide, zirconium oxide, hafnium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or oxide. In the present embodiment, the material of the high dielectric layer 22 is, for example, tantalum oxide material. The present invention is not limited to the method of forming the high dielectric layer 22, and in this embodiment, for example, atomic deposition (Atomic Layer Deposition, ALD), metal organic vapor deposition (Metal-Oraganic Vapor Deposition, MOCVD), or chemical vapor deposition (Chemical Vapor Deposition, CVD) is selected. The high dielectric layer 22 has a thickness of, for example, 30 a to 150 a, specifically, 30 a, 60 a, 90 a, 120 a, or 150 a. By forming the high dielectric layer 22 on the liner oxide layer 21, positive charges can be accumulated on the surface of the semiconductor substrate 10 and the surfaces of the bottom and the side walls of the deep trench 20 to generate potential barriers, so that free electrons on the surface of the semiconductor substrate 10 and the surfaces of the bottom and the side walls of the deep trench 20 are adsorbed, cannot move and recombine, the generation of dark current is reduced, and meanwhile, the side walls of the deep trench 20 are protected.
Referring to fig. 6 to 7, in an embodiment of the present invention, after forming the high dielectric layer 22, the substrate 10 is processed to form the first oxide layer 23 on the high dielectric layer 22. The first oxide layer 23 covers the surface of the substrate 10 and the side walls and bottom of the deep trench 20, for example, and fills the deep trench 20, a seal is formed at one end of the deep trench 20 near the surface of the substrate 10, and the first oxide layer 23 forms an air gap 24 within the deep trench 20. Wherein, the seal of the air gap 24 is lower than the height of the deep trench 20, i.e. the top of the air gap 24 is lower than the top of the deep trench 20, so as to avoid reducing the isolation effect of the deep trench 20 or reducing the stability of the isolation structure. The thickness of the first oxide layer 23 is, for example, 1200 a to 1800 a, and the stress of the deposited first oxide layer 23 is, for example, a tensile stress of, for example, 20mpa to 40mpa. By filling the first oxide layer 23 with the air gap 24 in the deep trench 20, the electrical and optical isolation between adjacent components is enhanced, and the performance of the semiconductor device is improved. In this embodiment, the first oxide layer 23 is formed, for example, by a first deposition process, such as a high aspect ratio process (High Aspect Ratio Process, HARP), i.e., a thermochemical reaction using ozone and tetraethoxysilane to form an oxide film. Specifically, a reactant gas is introduced at a predetermined process temperature and a predetermined pressure to form a first oxide layer 23 on the high dielectric layer 22 through a high aspect ratio process. Wherein the preset process temperature is 380 ℃ to 400 ℃ and the preset pressure is 20MPa to 40MPa.
Referring to fig. 7, in an embodiment of the invention, after forming the first oxide layer 23, a baking process is performed on the first oxide layer 23, and the water-oxygen residues generated in the first oxide layer 23 deposited by the high aspect ratio process are removed by the baking process, so as to improve the density of the first oxide layer 23, and avoid the difficulty in removing the water-oxygen residues after the subsequent annealing treatment, thereby causing the bubble defect of the water-oxygen residues in the subsequent process. Specifically, the substrate 10 is subjected to a baking process at a predetermined temperature and a predetermined flow of helium gas is introduced for a predetermined time. Wherein the baking temperature is 300 ℃ to 350 ℃, the flow rate of helium is 8000sccm to 10000sccm, and the baking time is 300s to 400s. In the embodiment of the present invention, the purpose of better removing the water oxygen residues in the first oxide layer 23 is achieved by changing the helium flow and the baking time of the baking process within the set ranges, so as to avoid the bubble defect caused by the water oxygen residues.
Referring to fig. 7 to 8, in an embodiment of the present invention, after the first oxide layer 23 is baked, the second oxide layer 25 is deposited on the first oxide layer 23, and the second oxide layer 25 covers the first oxide layer 23, i.e. covers the substrate 10 and the deep trench 20, so as to form a deep trench isolation structure. The thickness of the second oxide layer 25 is, for example, 1000 a to 1200 a, and the stress of the deposited second oxide layer 25 is, for example, compressive stress, and the magnitude of the compressive stress is, for example, from-150 MPa to-250 MPa. The second oxide layer 25 is formed, for example, by a second deposition process, such as a plasma enhanced tetraethyl orthosilicate layer deposition (Plasma enhanced deposition process of ethyl orthosilicate layer, PETEOS) process, in this embodiment, for example, forming the second oxide layer 25 at a set temperature and pressure. Specifically, the reaction temperature is 300 ℃ to 350 ℃, and the reaction pressure is 20MPa to 40MPa, for example. In this embodiment, in the process of depositing the second oxide layer 25, for example, the stress of the first oxide layer 23 and the stress of the second oxide layer 25 are optimally matched, so that the stress after the first oxide layer 23 and the second oxide layer 25 are combined is a compressive stress, and the compressive stress is, for example, -110MPa to-230 MPa. By depositing the second oxide layer 25 on the first oxide layer 23, the isolation performance and stability of the deep trench isolation structure are enhanced, and meanwhile, the stress of the first oxide layer 23 and the stress of the second oxide layer 25 are optimally matched, so that the whole film layer is expressed as compressive stress, the problem that the adhesion between silicon and the surface of the film layer is poor due to tensile stress is avoided, and the problem of bubble defects is integrally improved.
Referring to fig. 8 to 14, in an embodiment of the present invention, fig. 9 and 10 show the appearance of bubble defects on the substrate 10 after the first oxide layer 23 is deposited only by the high aspect ratio process. Fig. 11 and 12 show the appearance of bubble defects on the substrate 10 after depositing the first oxide layer 23 by a high aspect ratio process, and after depositing the second oxide layer 25 directly on the first oxide layer 23 by a plasma enhanced tetraethyl orthosilicate layer deposition process. Fig. 13 and 14 show the appearance of bubble defects on the substrate 10 after the deposition of the first oxide layer 23 by a high aspect ratio process, the baking process, and the deposition of the second oxide layer 25 on the first oxide layer 23 by a plasma enhanced tetraethyl orthosilicate layer deposition process. As can be seen from fig. 9 to 14, in the first oxide layer 23 deposited by the high aspect ratio process, there are more bubble defects, and after the second oxide layer 25 is deposited on the first oxide layer 23 by the plasma enhanced tetraethyl orthosilicate layer deposition process, the bubble defects on the substrate 10 are reduced, but still there are more bubble defects. In the film structure formed by the preparation method of the semiconductor structure of the back-illuminated image sensor provided by the invention, namely, before the second oxide layer 25 is formed, the first oxide layer 23 is subjected to baking process treatment, so that the bubble defect between the substrate 10 and the film is greatly reduced, the bubble defect problem is greatly improved, and the performance of the semiconductor device is improved.
Referring to fig. 8 and 15, in an embodiment of the present invention, the stress of the first oxide layer 23 formed by the first deposition process is 20MPa to 40MPa, the stress of the second oxide layer 25 formed by the second deposition process is-150 MPa to-250 MPa, and the stress performance of the first oxide layer 23 and the second oxide layer 25 after being combined under different baking conditions is different during the baking process, wherein fig. 15 is the stress performance of the first oxide layer 23 and the second oxide layer 25 after being combined under different baking conditions in different embodiments. Specifically, for example, the flow rate of helium gas is changed to 7000sccm or 8000sccm, and the baking time is changed to 270s, 300s or 330s, for example. As can be seen from the figure, the magnitudes of the compressive stresses exhibited by the first oxide layer 23 and the second oxide layer 25 gradually decrease and tend to stabilize as the flow rate of helium gas increases and the baking time increases after baking. It has been found that controlling the flow of helium gas, for example, at 8000sccm and the baking time, for example, at 300s, during the baking process can achieve a better removal of water oxygen residues from the first oxide layer 23 deposited by the high aspect ratio process. The method for forming the deep trench isolation structure can also be applied to the preparation of other semiconductor structures, and the quality of the manufactured semiconductor device is improved.
In summary, the present invention provides a semiconductor structure of a backside illuminated image sensor and a method for fabricating the same, wherein a baking process is used to treat a first oxide layer deposited by a high aspect ratio process, which unexpectedly has the effect of removing water-oxygen residues in the first oxide layer and avoiding the subsequent generation of bubble defects. And forming a second oxide layer on the first oxide layer, wherein the stress of the film layer is expressed as compressive stress through a stress matching optimization process, so that the problem of poor adhesion between the film layer and the surface of the substrate due to tensile stress is avoided. Meanwhile, the deposition mode and the preparation condition of the film layer are selected, so that the waste of resources is reduced, the production time is saved, and the production efficiency is improved.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (6)
1. A method for fabricating a semiconductor structure of a backside illuminated image sensor, comprising at least the steps of:
providing a substrate;
forming a plurality of deep trenches within the substrate;
forming a liner oxide layer on the side wall and the bottom of the deep trench and the substrate;
forming a high dielectric medium layer on the lining oxide layer;
forming a first oxide layer on the high dielectric medium layer through a first deposition process, wherein the first oxide layer is filled to the top of the deep trench, and an air gap is formed in the deep trench by the first oxide layer;
baking the first oxide layer;
forming a second oxide layer on the first oxide layer through a second deposition process, wherein the stress of the second oxide layer is opposite to that of the first oxide layer, and the pressure type after the first oxide layer and the second oxide layer are combined is compressive stress;
wherein, the baking process comprises the following steps: introducing a gas with a set flow rate at a preset baking temperature, and completing the baking process treatment of the first oxide layer after reacting for a preset time;
the gas comprises helium, and the flow rate of the gas is 8000-10000 sccm.
2. The method of claim 1, wherein the stress type of the first oxide layer is tensile stress.
3. The method of claim 1, wherein the second oxide layer has a compressive stress.
4. The method of claim 1, wherein the first deposition process is a high aspect ratio process and the reaction temperature of the first deposition process is 380 ℃ to 400 ℃.
5. The method for fabricating a semiconductor structure of a backside illuminated image sensor according to claim 1, wherein the baking temperature is 300 ℃ to 350 ℃.
6. The method of claim 1, wherein the second deposition process is a plasma enhanced ethyl orthosilicate layer deposition process, and the reaction temperature of the second deposition process is 300-350 ℃.
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