CN101996923A - Method for forming shallow trench isolation structure - Google Patents
Method for forming shallow trench isolation structure Download PDFInfo
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- CN101996923A CN101996923A CN2009101946217A CN200910194621A CN101996923A CN 101996923 A CN101996923 A CN 101996923A CN 2009101946217 A CN2009101946217 A CN 2009101946217A CN 200910194621 A CN200910194621 A CN 200910194621A CN 101996923 A CN101996923 A CN 101996923A
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- oxide layer
- isolation structure
- semiconductor substrate
- formation method
- fleet plough
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Abstract
The invention discloses a method for forming a shallow trench isolation structure, which comprises the following steps of: forming a buffer oxidation layer on a semiconductor substrate; etching the buffer oxidation layer and the semiconductor substrate to form a trench; forming an isolation oxidation layer filling in the trench and covering the buffer oxidation layer; and flattening the isolation oxidation layer and the buffer oxidation layer until the semiconductor substrate is exposed by adopting a chemically mechanical polishing process. The method can avoid filling defects of the isolation oxidation layer filled in the trench.
Description
Technical field
The present invention relates to the manufacture of semiconductor technical field, particularly a kind of formation method of fleet plough groove isolation structure.
Background technology
Semiconductor integrated circuit includes source region and the isolated area between active area usually, and these isolated areas formed before making active device.Along with semiconductor technology enters the deep-submicron epoch, the device that 0.18 μ m is following, for example the active area isolation layer of MOS circuit adopts shallow ditch groove separation process (STI) to make mostly.
Fig. 1 a to 1f is the generalized section that forms fleet plough groove isolation structure according to conventional method.At first, with reference to figure 1a, on semiconductor substrate 100, form buffer oxide layer 110 and corrosion barrier layer 120, on corrosion barrier layer 120, form the photoresist of patterning, and be mask with the photoresist of patterning, etch buffer oxide layer 110 and corrosion barrier layer 120 are to semiconductor substrate 100; With reference to figure 1b, be mask with corrosion barrier layer 120, etching semiconductor substrate 100 to one set depths form shallow trench 130.
Then, with reference to figure 1c, form lining oxide layer 140 on the surface of groove 130, lining oxide layer 140 can be insulating material such as silicon dioxide; With reference to figure 1d, megohmite insulant (as silicon dioxide) is inserted in the groove 130, and covered lining oxide layer 140 sidewalls and whole corrosion barrier layer 120, form isolating oxide layer 150; The method that forms described megohmite insulant adopts high density plasma CVD method (Highdensity plasma Chemical Vapor Deposition) usually, then, with reference to figure 1e, the isolating oxide layer of inserting 150 is carried out planarization, as adopt CMP (Chemical Mechanical Polishing) process to remove isolating oxide layer 150 on the corrosion barrier layer 120, last, with reference to figure 1f, remove corrosion barrier layer 120 and buffering oxide layer 110, the fleet plough groove isolation structure of formation.
Along with further dwindling of semiconductor device, the depth-to-width ratio of groove constantly increases, adopt the technology of high density plasma CVD method filling groove more and more to be difficult to control, at present, the depth-to-width ratio of groove is increased to greater than 10 from original 4～5, in the technology that adopts high density plasma CVD method filling groove, can produce following problem: in the isolating oxide layer of filling groove, produce cavity (Void) or/and slit (seam), because the existence in cavity and slit in the isolating oxide layer, when the described isolating oxide layer of following adopted CMP (Chemical Mechanical Polishing) process planarization, cause CMP (Chemical Mechanical Polishing) process to be difficult to control, and have a strong impact on the quality of the isolating oxide layer of final formation.
Therefore, how to improve the manufacture craft of fleet plough groove isolation structure, improve the filling capacity of groove,, become an important research project with the more and more littler trend of reply semiconductor device critical dimension.
Summary of the invention
The problem that the present invention solves is that the depth-to-width ratio of groove is increasing along with semiconductor device critical dimension is more and more littler, and defective appears in trench fill in the shallow ditch groove separation process of prior art.
The invention provides a kind of formation method of groove isolation construction, comprise the steps: on semiconductor substrate, to form buffer oxide layer; Etching buffer oxide layer and semiconductor substrate form groove; Formation is filled up groove and is covered the isolating oxide layer of buffer oxide layer; Adopt the described isolating oxide layer of CMP (Chemical Mechanical Polishing) process planarization, buffer oxide layer to exposing semiconductor substrate.
Optionally, the formation method of described fleet plough groove isolation structure also comprises the described semiconductor substrate of etching, to adjust the step of isolating oxide layer and semiconductor substrate difference in height.
Optionally, the formation method of described fleet plough groove isolation structure forms after the groove, forms before the isolating oxide layer, also is included in the step that trench wall forms lining oxide layer.
Optionally, the main component of polishing fluid is CeO in the described CMP (Chemical Mechanical Polishing) process
2Particle.
Optionally, the technology of formation isolating oxide layer is high density plasma CVD technology.
Optionally, the thickness of described buffer oxide layer is 300 dust to 500 dusts; Etching buffer oxide layer and semiconductor substrate, the thickness of described buffer oxide layer is less than 100 dusts behind the formation groove.
Optionally, described buffer oxide layer is silicon dioxide or silicon oxynitride.Described isolation oxidation layer material is a silicon dioxide.
Owing to adopted technique scheme, compared with prior art, the present invention has the following advantages:
Relative prior art, removed corrosion barrier layer in the technical solutions according to the invention, therefore, corresponding the increasing to of depth-to-width ratio of the groove that forms less than 5, in the technology of subsequent deposition isolating oxide layer, because the depth-to-width ratio of groove increases, therefore, the various filling defects that when the groove depth-to-width ratio is big, occur have been avoided.
Further, process of the present invention is by selecting the polishing fluid of chemico-mechanical polishing, make CMP (Chemical Mechanical Polishing) process stop on the semiconductor substrate automatically, not only solved owing to the change of removing the CMP technology of bringing after the corrosion barrier layer (existing technology CMP technology all stops on the corrosion barrier layer), and simplified technical process.
Description of drawings
Fig. 1 a to Fig. 1 f is the cross-sectional view of the sti structure of existing shallow ditch groove separation process formation;
Fig. 2 a to Fig. 2 f is the cross-sectional view of the sti structure of shallow ditch groove separation process formation of the present invention.
Embodiment
The invention provides a kind of formation method of groove isolation construction, in a specific embodiment of the present invention, comprise the steps: on semiconductor substrate, to form buffer oxide layer; Etching buffer oxide layer and semiconductor substrate form groove; Formation is filled up groove and is covered the isolating oxide layer of buffer oxide layer; Adopt the described isolating oxide layer of chemical vapor deposition method planarization, buffer oxide layer to exposing semiconductor substrate.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
At first, with reference to figure 2a, on semiconductor substrate 400, form buffer oxide layer 410.Described semiconductor substrate 400 is silicon or silicon-on-insulator.The material of described buffer oxide layer 410 can be a silicon dioxide etc., generally adopts the technology of thermal oxidation to form, and can also be silicon oxynitride layer, generally adopts low-pressure chemical vapor deposition or plasma auxiliary chemical vapor deposition method to form.The thickness of described buffer oxide layer 410 for example is 300 dusts～500 dusts.
With reference to figure 2b, on buffer oxide layer 410, spray photoresist, and utilize technologies such as exposure, development to form the photoresist opening.Wherein the zone corresponding with the photoresist aperture position is isolated area on semiconductor substrate 400, all the other are active area, be mask again with the photoresist, adopt anisotropic etching method etch buffer oxide layer 410, until exposing the pre-zone that forms isolated groove on the semiconductor substrate 400, continue etching semiconductor substrate 400 to one set depths, form groove 430.
The technology of etch buffer oxide layer 410 and semiconductor substrate 400 can be the anisotropic etching method, as reactive ion-etching (reactive ion etching, RIR).Owing to lacked corrosion barrier layer, the degree of depth of groove reduces, and therefore, the depth-to-width ratio of the groove 430 of formation reduces, and generally speaking, the depth-to-width ratio scope of groove 430 is less than 5.
Remove the photoresist layer on the buffer oxide layer 410 at last.Owing among reactive ion-etching, have the loss of buffer oxide layer 410, therefore through described technology, the thickness of described buffer oxide layer 410 is less than 100 dusts.
Optionally, with reference to figure 2c, described embodiment can also comprise following technology: the inner surface at groove 430 forms lining oxide layer 440, and the material of lining oxide layer 440 can be a silicon dioxide, perhaps the composite bed of silicon dioxide and silicon oxynitride.
With reference to figure 2d, megohmite insulant to be inserted in the groove 430, and formed isolating oxide layer 450, the material of described isolating oxide layer can be a silicon dioxide etc., isolating oxide layer 450 fills up groove 430 and covers whole buffer oxide layer 410, shown in Fig. 2 d.
The technology of deposition isolating oxide layer 450 can adopt chemical vapour deposition technique in groove 430 and on the buffer oxide layer 410, and relatively the technical scheme of You Huaing is for example with oxygen (O
2) and monosilane (silane; SiH
4) be reacting gas, with high density plasma chemical vapor deposition method (HDPCVD; High-density plasmachemical vapor deposition), deposition layer of silicon dioxide insulating barrier in groove 430 and on the surface of buffer oxide layer 410.
Then, with reference to figure 2e, the isolating oxide layer of inserting 450 is carried out planarization, described flatening process is chemical mechanical polishing method for example, until semiconductor substrate 400.
In a specific embodiment of the present invention, the main component of the polishing fluid that adopts in the described CMP (Chemical Mechanical Polishing) process is CeO
2Particle in CMP (Chemical Mechanical Polishing) process, is adjusted CeO in the described polishing fluid
2The concentration of particle, make described polishing fluid for the rate that removes of polysilicon (Removal Rate, RR)＜20 dust/minute, therefore, adopt described polishing fluid, described CMP (Chemical Mechanical Polishing) process can stop at semiconductor substrate surface automatically.
The employing main component is CeO
2The process conditions that the polishing fluid of particle carries out chemico-mechanical polishing are for example: the rotating speed of grinding head is that 50rpm (revolutions per) is to 120rpm; The downward pressure of grinding head be 1.5psi to 4psi, wherein, 1psi=0.0069Mpa.
At last, optionally, with reference to figure 2f, according to the difference of designs, the described semiconductor substrate of etching is to adjust the step of isolating oxide layer and semiconductor substrate difference in height.Described processing step leaks electricity between the active area between the fleet plough groove isolation structure.
The described technology of present embodiment has been removed corrosion barrier layer, and therefore, the depth-to-width ratio of the groove of formation is corresponding to be increased to less than 5, in the technology of subsequent deposition isolating oxide layer, because the depth-to-width ratio of groove increases, therefore, the various filling defects that when the groove depth-to-width ratio is big, occur have been avoided.
Further, process of the present invention is by selecting the polishing fluid of chemico-mechanical polishing, make CMP (Chemical Mechanical Polishing) process stop on the semiconductor substrate automatically, not only solved owing to the change of removing the CMP technology of bringing after the corrosion barrier layer (existing technology CMP technology all stops on the corrosion barrier layer), and simplified technical process.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (9)
1. the formation method of a fleet plough groove isolation structure comprises the steps:
On semiconductor substrate, form buffer oxide layer;
Etching buffer oxide layer and semiconductor substrate form groove;
Formation is filled up groove and is covered the isolating oxide layer of buffer oxide layer;
Adopt the described isolating oxide layer of CMP (Chemical Mechanical Polishing) process planarization, buffer oxide layer to exposing semiconductor substrate.
2. the formation method of fleet plough groove isolation structure according to claim 1 is characterized in that, also comprises the described semiconductor substrate of etching, to adjust the step of isolating oxide layer and semiconductor substrate difference in height.
3. the formation method of fleet plough groove isolation structure according to claim 1 is characterized in that, forms after the groove, forms before the isolating oxide layer, also is included in the step that trench wall forms lining oxide layer.
4. according to the formation method of each described fleet plough groove isolation structure in the claim 1 to 3, it is characterized in that the main component of polishing fluid is CeO in the described CMP (Chemical Mechanical Polishing) process
2Particle.
5. according to the formation method of each described fleet plough groove isolation structure in the claim 1 to 3, it is characterized in that the technology that forms isolating oxide layer is high density plasma CVD technology.
6. according to the formation method of each described fleet plough groove isolation structure in the claim 1 to 3, it is characterized in that the thickness of described buffer oxide layer is 300 dust to 500 dusts.
7. the formation method of fleet plough groove isolation structure according to claim 6 is characterized in that, etching buffer oxide layer and semiconductor substrate, and the thickness of described buffer oxide layer is less than 100 dusts behind the formation groove.
8. the formation method of fleet plough groove isolation structure according to claim 1 is characterized in that, described buffer oxide layer is silicon dioxide or silicon oxynitride.
9. the formation method of fleet plough groove isolation structure according to claim 1 is characterized in that, described isolation oxidation layer material is a silicon dioxide.
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| CN2009101946217A CN101996923A (en) | 2009-08-26 | 2009-08-26 | Method for forming shallow trench isolation structure |
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| CN2009101946217A CN101996923A (en) | 2009-08-26 | 2009-08-26 | Method for forming shallow trench isolation structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117153855A (en) * | 2023-10-30 | 2023-12-01 | 合肥晶合集成电路股份有限公司 | Semiconductor structure of back-illuminated image sensor and manufacturing method thereof |
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2009
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117153855A (en) * | 2023-10-30 | 2023-12-01 | 合肥晶合集成电路股份有限公司 | Semiconductor structure of back-illuminated image sensor and manufacturing method thereof |
| CN117153855B (en) * | 2023-10-30 | 2024-03-01 | 合肥晶合集成电路股份有限公司 | Semiconductor structure of back-illuminated image sensor and manufacturing method thereof |
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Application publication date: 20110330 |