CN108281444A - Imaging sensor and forming method thereof - Google Patents
Imaging sensor and forming method thereof Download PDFInfo
- Publication number
- CN108281444A CN108281444A CN201810083564.4A CN201810083564A CN108281444A CN 108281444 A CN108281444 A CN 108281444A CN 201810083564 A CN201810083564 A CN 201810083564A CN 108281444 A CN108281444 A CN 108281444A
- Authority
- CN
- China
- Prior art keywords
- layer
- tensile stress
- imaging sensor
- metal barrier
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003384 imaging method Methods 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 49
- 229910052751 metal Inorganic materials 0.000 claims abstract description 152
- 239000002184 metal Substances 0.000 claims abstract description 152
- 230000004888 barrier function Effects 0.000 claims abstract description 107
- 239000004065 semiconductor Substances 0.000 claims abstract description 107
- 239000000758 substrate Substances 0.000 claims abstract description 98
- 239000000463 material Substances 0.000 claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 37
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 17
- 239000004020 conductor Substances 0.000 claims description 15
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 10
- 229910052796 boron Inorganic materials 0.000 claims description 10
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 abstract description 12
- 230000006835 compression Effects 0.000 abstract description 9
- 238000007906 compression Methods 0.000 abstract description 9
- 238000012856 packing Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 212
- 239000011241 protective layer Substances 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 238000003949 trap density measurement Methods 0.000 description 9
- 229910052721 tungsten Inorganic materials 0.000 description 9
- 239000010937 tungsten Substances 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 230000005527 interface trap Effects 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 6
- 239000000956 alloy Substances 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000007667 floating Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 230000002401 inhibitory effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000001151 other effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000005516 deep trap Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Element Separation (AREA)
Abstract
A kind of imaging sensor and forming method thereof, the method includes：Semiconductor substrate is provided；The semiconductor substrate is performed etching, to form isolated groove；Dielectric film is formed, the dielectric film covers the inner wall of the isolated groove；Metal barrier is formed, the metal barrier covers the dielectric film；Tensile stress layer is formed, the tensile stress layer fills at least part for the groove space that the metal barrier surrounds.The present invention program can reduce the compression that the packing material in deep trench isolation generates semiconductor substrate.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of imaging sensor and forming method thereof.
Background technology
Imaging sensor is the core component of picture pick-up device, and image taking work(is realized by converting optical signals into electric signal
Energy.By taking cmos image sensor (CMOS Image Sensors, CIS) device as an example, in a manufacturing process, to prevent not same district
The photo-generated carrier in domain is diffused into adjacent area, needs to form deep trench isolation (Deep Trench in the inside of semiconductor substrate
Isolation, DTI).
Specifically, deep trench isolation can potentially inhibit blooming (blooming), and for rear illuminated (Back-
Side Illumination, abbreviation BSI) CIS, fills isolated groove using metal material, forms deep trench isolation, can inhibit
Optical crosstalk.Wherein, the rear illuminated CIS is referred to as back-illuminated type CIS.
In the prior art, deep trench isolation generally use titanium nitride (TiN) film is as packing material, or uses titanium nitride
Laminated construction with tungsten (W) is as packing material.It is answered however, titanium nitride and tungsten can generate higher machinery to semiconductor substrate
Power, for example, compression (Compressive Stress) may cause the medium layer film in isolated groove to be served as a contrast with semiconductor
The increase of interface trap density between bottom influences the performance of semiconductor devices.
There is an urgent need for a kind of imaging sensor and forming method thereof, the packing material that can be reduced in deep trench isolation serves as a contrast semiconductor
The compression that bottom generates.
Invention content
The technical problem to be solved by the present invention is to provide a kind of imaging sensors and forming method thereof, can reduce deep trench isolation
In packing material compression that semiconductor substrate is generated.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of forming method of imaging sensor, including it is following
Step：Semiconductor substrate is provided；The semiconductor substrate is performed etching, to form isolated groove；Dielectric film is formed, it is described
Dielectric film covers the inner wall of the isolated groove；Metal barrier is formed, the metal barrier covers the dielectric film；
Tensile stress layer is formed, the tensile stress layer fills at least part for the groove space that the metal barrier surrounds.
Optionally, the tensile stress layer fills the whole for the groove space that the metal barrier surrounds.
Optionally, the forming method of described image sensor further includes：Etching removes the tensile stress in the isolated groove
A part for layer and metal barrier；First medium layer is formed, the first medium layer fills the isolated groove and covers institute
State tensile stress layer and metal barrier.
Optionally, the material of the tensile stress layer is conductive material, and the method further includes：Form second dielectric layer, institute
It states second dielectric layer and covers the semiconductor substrate and first medium layer surface；To the second dielectric layer and first medium layer into
Row etching, to form contact hole, the bottom-exposed of the contact hole goes out the tensile stress layer；Filling is inserted in the contact hole
Plug.
Optionally, the formation tensile stress layer includes：Metal is filled in the groove space that the metal barrier surrounds
Layer；Etching removes a part for the metal layer and metal barrier, and the layer on surface of metal after etching has recess；It is formed to draw and be answered
Power layer, the tensile stress layer fill the recess and cover the layer on surface of metal other than the recess.
Optionally, the forming method of the imaging sensor further includes：The drawing that etching removes in the isolated groove is answered
A part for power layer；Third dielectric layer is formed, the third dielectric layer fills the isolated groove and covers the tensile stress layer.
Optionally, the material of the tensile stress layer is conductive material, and the method further includes：Form the 4th dielectric layer, institute
It states the 4th dielectric layer and covers the semiconductor substrate and third dielectric layer surface；To the 4th dielectric layer and third dielectric layer into
Row etching, to form contact hole, the bottom-exposed of the contact hole goes out the tensile stress layer；Filling is inserted in the contact hole
Plug.
Optionally, the material of the tensile stress layer is boron doped SiGe.
Optionally, the material of the metal barrier is titanium nitride or tantalum nitride.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of imaging sensor, including：Semiconductor substrate；Every
From groove, it is located in the semiconductor substrate；Dielectric film covers the inner wall of the isolated groove；Metal barrier covers institute
State dielectric film；Tensile stress layer fills at least part for the groove space that the metal barrier surrounds.
Optionally, the tensile stress layer fills the whole for the groove space that the metal barrier surrounds.
Optionally, the imaging sensor further includes：First medium layer fills the isolated groove and covers the drawing
Stressor layers and metal barrier.
Optionally, the material of the tensile stress layer is conductive material, and the imaging sensor further includes：Second medium
Layer, covers the semiconductor substrate and first medium layer surface；Contact hole is located at the second dielectric layer and first medium layer
It is interior, and the bottom-exposed of the contact hole goes out the tensile stress layer；Plug is filled in the contact hole.
Optionally, the imaging sensor further includes：It is empty to be filled in the groove that the metal barrier surrounds for metal layer
In, and the layer on surface of metal has recess；Wherein, the tensile stress layer filling is described is recessed and covers other than the recess
Layer on surface of metal.
Optionally, the imaging sensor further includes：Third dielectric layer fills the isolated groove and covers the drawing
Stressor layers.
Optionally, the material of the tensile stress layer is conductive material, and the imaging sensor further includes：4th medium
Layer, covers the semiconductor substrate and third dielectric layer surface；Contact hole is located at the 4th dielectric layer and third dielectric layer
It is interior, and the bottom-exposed of the contact hole goes out the tensile stress layer；Plug is filled in the contact hole.
Optionally, the material of the tensile stress layer is boron doped SiGe.
Optionally, the material of the metal barrier is titanium nitride or tantalum nitride.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that：
In embodiments of the present invention, semiconductor substrate is provided；The semiconductor substrate is performed etching, to form isolating trenches
Slot；Dielectric film is formed, the dielectric film covers the inner wall of the isolated groove；Form metal barrier, the metal resistance
Barrier covers the dielectric film；Tensile stress layer is formed, it is empty that the tensile stress layer fills the groove that the metal barrier surrounds
Between at least part.Using the above scheme, metal barrier and tensile stress layer are sequentially formed in isolated groove, and are drawn and answered
Power layer fills at least part for the groove space that the metal barrier surrounds, since tensile stress layer generates semiconductor substrate
Mechanical stress and the metal barrier stress types of mechanical stress that semiconductor substrate is generated hindered on the contrary, metal can be reduced
Influence of the barrier to the stress of semiconductor substrate, to the boundary for reducing the dielectric film in isolated groove and between semiconductor substrate
Face trap density improves the performance of semiconductor devices.
Further, it is possible to the whole that the tensile stress layer fills the groove space that the metal barrier surrounds is set, from
And improve the interface trap density caused by entire metal barrier between dielectric film and semiconductor substrate, improve semiconductor device
The performance of part.
Further, it is possible to fill metal layer in the groove space that metal barrier surrounds, and have using layer on surface of metal
Some recess are arranged the tensile stress layer and fill the recess and cover the layer on surface of metal other than the recess, so as to improve
Interface trap density caused by metal layer and metal barrier between dielectric film and semiconductor substrate improves semiconductor device
The performance of part.
Further, go out the contact hole of the tensile stress layer by forming bottom-exposed, and fill plug in the contact hole,
Can be by the voltage of the application appropriate type on plug, such as apply negative voltage when carrier is electronics, make isolated groove
Carrier between photodiode helps to improve carrier moving speed, improves the speed of device far from isolated groove
Performance.
Description of the drawings
Fig. 1 is a kind of cross-sectional view of imaging sensor in the prior art；
Fig. 2 is a kind of flow chart of the forming method of imaging sensor in the embodiment of the present invention；
Fig. 3 to Figure 11 is that each step respective devices are cutd open in a kind of forming method of imaging sensor in the embodiment of the present invention
Face structural schematic diagram；
Figure 12 to Figure 16 is each step respective devices in the forming method of another imaging sensor in the embodiment of the present invention
Cross-sectional view.
Specific implementation mode
In the prior art, blooming is potentially inhibited using deep trench isolation, and inhibits optical crosstalk.The deep trouth
Generally use titanium nitride film is isolated as packing material, or using the laminated construction of titanium nitride and tungsten as packing material.
Referring to Fig.1, Fig. 1 is a kind of cross-sectional view of imaging sensor in the prior art.Described image sensor
May include semiconductor substrate 100, protective layer 102, isolated groove 110, dielectric film 120 and alloy material layer 130.
Specifically, protective layer 102 is formed on the surface of semiconductor substrate 100, then in the surface shape of the protective layer 102
At patterned mask layer, using the patterned mask layer as mask, to the protective layer 102 and semiconductor substrate 100
It performs etching, to form the isolated groove 110.
Further, dielectric film 120 is formed in the isolated groove 110, and surrounded in the dielectric film 120
Alloy material layer 130 is formed in groove space.
Wherein, the material of the alloy material layer 130 generally includes titanium nitride, or the lamination knot with titanium nitride and tungsten
Structure.
The present inventor passes through the study found that in the prior art, titanium nitride and tungsten can produce semiconductor substrate
Raw higher compression, the compression may cause the dielectric film in isolated groove and the interface between semiconductor substrate to fall into
The increase of trap density, and then influence the performance of semiconductor devices.
In embodiments of the present invention, semiconductor substrate is provided；The semiconductor substrate is performed etching, to form isolating trenches
Slot；Dielectric film is formed, the dielectric film covers the inner wall of the isolated groove；Form metal barrier, the metal resistance
Barrier covers the dielectric film；Tensile stress layer is formed, it is empty that the tensile stress layer fills the groove that the metal barrier surrounds
Between at least part.Using the above scheme, metal barrier and tensile stress layer are sequentially formed in isolated groove, and are drawn and answered
Power layer fills at least part for the groove space that the metal barrier surrounds, since tensile stress layer generates semiconductor substrate
Mechanical stress and the metal barrier stress types of mechanical stress that semiconductor substrate is generated hindered on the contrary, metal can be reduced
Influence of the barrier to the stress of semiconductor substrate, to the boundary for reducing the dielectric film in isolated groove and between semiconductor substrate
Face trap density improves the performance of semiconductor devices.
It is understandable to enable above-mentioned purpose, feature and the advantageous effect of the present invention to become apparent, below in conjunction with the accompanying drawings to this
The specific embodiment of invention is described in detail.
With reference to Fig. 2, Fig. 2 is a kind of flow chart of the forming method of imaging sensor in the embodiment of the present invention.Described image
The forming method of sensor may include step S21 to step S25：
Step S21：Semiconductor substrate is provided；
Step S22：The semiconductor substrate is performed etching, to form isolated groove；
Step S23：Dielectric film is formed, the dielectric film covers the inner wall of the isolated groove；
Step S24：Metal barrier is formed, the metal barrier covers the dielectric film；
Step S25：Tensile stress layer is formed, the tensile stress layer fills the groove space of the metal barrier encirclement extremely
A few part.
Above-mentioned each step is illustrated with reference to Fig. 3 to Figure 11.
Fig. 3 to Figure 11 is that each step respective devices are cutd open in a kind of forming method of imaging sensor in the embodiment of the present invention
Face structural schematic diagram.
With reference to Fig. 3, semiconductor substrate 200 is provided, protective layer 202 is formed on the surface of the semiconductor substrate 200, in institute
The surface for stating protective layer 202 is formed with patterned mask layer 206.
In specific implementation, the semiconductor substrate 200 can be silicon substrate or the material of the semiconductor substrate 200
Material can also be the materials appropriate applied to imaging sensor such as germanium, SiGe, silicon carbide, GaAs or gallium indium, described
Semiconductor substrate 200 can also have outside for the silicon substrate of insulator surface or the germanium substrate of insulator surface, or growth
Prolong the substrate of layer (Epitaxy layer, Epi layer).Preferably, the semiconductor substrate 200 can be half be lightly doped
Conductor substrate, and doping type is opposite with drain region.Specifically, can by the semiconductor substrate 200 carry out ion implanting,
Realize deep trap doping (Deep Well Implant).
Wherein, the protective layer 202 can be used for protect semiconductor substrate 200, to avoid formed in the subsequent process every
Semiconductor substrate 200 is formed when from groove and is injured.The material of the protective layer 202 may include：Silica, silicon nitride, nothing
Shape carbon (Amorphous Carbon) layer and anti-reflection coating (Anti-Reflective Coating, ARC).Wherein, institute
It can be SiO to state silica for example2, the silicon nitride for example can be Si3N4。
With reference to Fig. 4, with the patterned mask layer 206 (with reference to Fig. 3) for mask, to the protective layer 202 and described
Semiconductor substrate 200 performs etching, to form isolated groove 210.
Wherein, can be dry etching to the technique that the protective layer 202 and the semiconductor substrate 200 perform etching
(Dry Etch)。
It is understood that the semiconductor substrate 200 between the isolated groove 210 is used to form photodiode etc. half
Conductor device, therefore, the depth of the isolated groove 210 should not be excessively shallow, is otherwise difficult to realize partly lead photodiode etc.
The isolation effect of body device；The depth of the isolated groove 210 should not be too deep, otherwise can improve process complexity, be added to
This.As a unrestricted example, the depth of the isolated groove 210 can be 2 μm to 2.5 μm.
Specifically, the internal diameter that the isolated groove 210 may be used indicates the size of the isolated groove 210.It can
With understanding, the internal diameter of the isolated groove 210 should not be too small, is otherwise difficult to realize to semiconductor devices such as photodiodes
The isolation effect of part；The internal diameter of the isolated groove 210 should not be excessive, otherwise can occupy excessive space, increases image sensing
The size of device improves production cost.As a unrestricted example, the internal diameter of the isolated groove 210 can be 0.15 μ
M to 0.25 μm, preferably 0.2 μm.
With reference to Fig. 5, dielectric film 220 is formed, the dielectric film 220 covers the inner wall of the isolated groove 210.
Specifically, the dielectric material of the dielectric film 220 can be silica and/or silicon nitride.
In a kind of specific implementation mode of the embodiment of the present invention, individually silica can be used as dielectric film 220,
Compared to silicon nitride is individually used, since the stress of silica is less than the stress of silicon nitride.Device quality can be improved.
Specifically, the formation process of the dielectric film 220 may be used insitu moisture and generate (In-situ Steam
Generation, ISSG), atom layer deposition process (Atomic Layer Deposition, ALD), fluid chemistry gas phase it is heavy
Product, plasma activated chemical vapour deposition, sub- aumospheric pressure cvd or low-pressure chemical vapor deposition.
In embodiments of the present invention, it is preferable that insitu moisture may be used and generate (In-situ Steam
Generation, ISSG) technique forms the dielectric film 220.The ISSG techniques are considered as a kind of quick heat of oxidation of low pressure
Annealing technology compensates oxidation growth while carrying out thermal annealing to the film of deposit, contribute to form consistency higher,
Dielectric film 220 evenly.
Can also the dielectric film 220 be formed using atom layer deposition process.Since atom layer deposition process is usually used
In carrying out the controllable film growth of atomic scale, the uniformity of dielectric film 220 is controlled more preferably, also, due to atomic layer deposition
Product technique is to deposit to form film in layer with monatomic form membrane, compared to other depositing operations, has stronger calking
Ability can meet the demand of the depth-to-width ratio in deeper groove.
It is understood that the dielectric film 220 should not be excessively thin, otherwise it is difficult to realize partly lead photodiode etc.
The isolation effect of body device；The dielectric film 220 should not be blocked up, the premise otherwise being had determined in the size of isolated groove
Under, the thickness of metal barrier in subsequent technique, tensile stress layer can be influenced.As a unrestricted example, the medium
The thickness of film 220 can be 10nm to 12nm.
With reference to Fig. 6, metal barrier 230 is formed, the metal barrier 230 covers the dielectric film 220, is formed and is drawn
Stressor layers 240, the tensile stress layer 240 fill at least part of the groove space of the encirclement of the metal barrier 230.
Specifically, in the embodiment of the present invention shown in Fig. 6, the tensile stress layer 240 fills the metal barrier 230
The whole of the groove space of encirclement.
Wherein, the metal barrier 230 can be used as reflecting layer, for inhibiting crosstalk, the metal barrier 230
Material can be titanium nitride or tantalum nitride (TaN).
It is understood that the metal barrier 230 should not be excessively thin, otherwise it is difficult to realize inhibit the inhibition effect of crosstalk
Fruit；The metal barrier 230 should not be blocked up, otherwise under the premise of the size of isolated groove has determined, after influencing
The thickness of tensile stress layer in continuous technique.As a unrestricted example, the thickness of the metal barrier 230 can be
5nm to 10nm.
The material of the tensile stress layer 240 can be boron doped SiGe (Boron doped-SiGe), can also be
Other materials appropriate for providing tensile stress.
In embodiments of the present invention, the mechanical stress that 240 pairs of semiconductor substrate 200 of tensile stress layer generates is tensile stress, gold
It is compression to the mechanical stress that semiconductor substrate 200 generates to belong to barrier layer 230, since the stress types of the two are answered on the contrary, drawing
Power layer 240 can reduce influence of the metal barrier 230 to the stress of semiconductor substrate 200.
As a unrestricted example, the depositing temperature of the tensile stress layer 240 can be 400 degrees Celsius to 500
Degree Celsius, preferably 450 degrees Celsius.
With reference to Fig. 7, etching removes the tensile stress layer 240 and metal barrier in the isolated groove 210 (with reference to Fig. 5)
230 part.
In embodiments of the present invention, due to coming from electric field (E-field) meeting of metal barrier 230 (be, for example, titanium nitride)
The device performance of pixel transistor (Pixel Transistors) is influenced, one of removal metal barrier 230 can be passed through
Point, increase the physical distance between metal barrier 230 and pixel transistor, helps to reduce the influence to device performance.
It is understood that the upper surface of the tensile stress layer 240 and metal barrier 230 after etching is apart from semiconductor substrate
The distance on 200 surface should not too far, and the tensile stress layer 240 and metal barrier 230 otherwise formed is very few, it is difficult to realize suppression
Crosstalk processed and other effects；Table of the upper surface of tensile stress layer 240 and metal barrier 230 after etching apart from semiconductor substrate 200
The distance in face should not be excessively close, otherwise may influence the device performance of pixel transistor.As a unrestricted example,
Distance of the upper surface of tensile stress layer 240 and metal barrier 230 after etching apart from the surface of semiconductor substrate 200 can be
0.2 μm to 0.3 μm, preferably 0.25 μm.
With reference to Fig. 8, first medium layer 252 is formed, the first medium layer 252 fills the isolated groove 210 (with reference to figure
5) and the tensile stress layer 240 and metal barrier 230 are covered.
Wherein, the material of the first medium layer 252 can be selected from silica and/or silicon nitride.
Further, flat using chemically mechanical polishing (Chemical Mechanical Polishing, CMP) technique
Change the first medium layer 252.
Further, ion implanting is carried out to the semiconductor substrate 200, with the shape in the semiconductor substrate 200
At photodiode (Photo Diode, PD) doped region 280.
It should be pointed out that in specific implementation, can also be formed in the semiconductor substrate 200 according to specific requirements
Ion implanting drain region (Lightly is lightly doped in other doped regions, for example, floating diffusion region (Floating Diffusion, FD)
Doped Drain, LDD), source region, drain region, pixel device (Pixel Device) doped region etc..In embodiments of the present invention, right
It is not limited in the type of the doped region specifically formed, specific Doped ions and its doping parameters.
With reference to Fig. 9, second dielectric layer 254 is formed, the second dielectric layer 254 covers the semiconductor substrate and first and is situated between
The surface of matter layer 252.
Wherein, the material of the second dielectric layer 254 can be selected from silica and/or silicon nitride.
Further, the second dielectric layer 254 is planarized using CMP process.
Referring to Fig.1 0, the second dielectric layer 254 and first medium layer 252 are performed etching, to form contact hole 262,
The bottom-exposed of the contact hole 262 goes out the tensile stress layer 240.
Wherein, the material of the tensile stress layer 240 can be conductive material.
Referring to Fig.1 1, plug 264 is filled in the contact hole 262.
Specifically, since the material of the tensile stress layer 240 is conductive material, apply voltage on plug 264, then draw and answer
Power layer 240 and metal barrier 230 can conduct the voltage.
Further, the material of the plug 264 can be tungsten, can also be other conductive metals appropriate.
In embodiments of the present invention, go out the contact hole 262 of tensile stress layer 240 by forming bottom-exposed, and contacting
In hole 262 fill plug 264, can by plug 264 apply appropriate type voltage (such as when carrier be electronics when
Apply negative voltage), make carrier of the isolated groove 210 (with reference to Fig. 5) between photodiode 280 far from isolated groove 210,
Carrier moving speed is helped to improve, to improve the speed ability of device.
In embodiments of the present invention, metal barrier 230 and tensile stress layer 240 are sequentially formed in isolated groove 210,
And tensile stress layer 240 fills at least part of the groove space of the encirclement of the metal barrier 230, due to tensile stress layer 240
The mechanical stress that mechanical stress and the metal barrier 230 generated to semiconductor substrate 200 generates semiconductor substrate 200 is answered
Power type is on the contrary, influence of the metal barrier 230 to the stress of semiconductor substrate 200 can be reduced, to reduce isolated groove
Interface trap density between dielectric film 220 in 210 and semiconductor substrate 200 improves the performance of semiconductor devices.
Further, the groove space of the metal barrier 230 encirclement is filled by the way that the tensile stress layer 240 is arranged
All, the interface trap between dielectric film 220 and semiconductor substrate 200 caused by entire metal barrier 230 can be improved
Density improves the performance of semiconductor devices.
Figure 12 to Figure 16 is each step respective devices in the forming method of another imaging sensor in the embodiment of the present invention
Cross-sectional view.
Referring to Fig.1 2, semiconductor substrate 300 is provided, protective layer 302 is formed on the surface of the semiconductor substrate 300, it is right
The protective layer 302 and the semiconductor substrate 300 perform etching, to form isolated groove 310.
Dielectric film 320 is formed, the dielectric film 320 covers the inner wall of the isolated groove 310, forms metal barrier
Layer 330, the metal barrier 330 covers the dielectric film 320.
Metal layer 332 is filled in the groove space that the metal barrier 330 surrounds.
Specifically, the step of being performed etching to the protective layer 302 and the semiconductor substrate 300 may include：Institute
The surface for stating protective layer 302 is formed with patterned mask layer, using the patterned mask layer as mask, to the protective layer
302 and the semiconductor substrate 300 perform etching, to form isolated groove 310.
Wherein, the metal barrier 330 can be used as reflecting layer, for inhibiting crosstalk, the metal barrier 330
Material can be titanium nitride or tantalum nitride.
The metal layer 332 can be conventional conductive metal, such as selected from tungsten, aluminium, copper, silver, gold etc., it is preferable that can
To use tungsten as the metal layer 332.
Principle, specific implementation and the advantageous effect of semiconductor devices shown in related Figure 12 please refer to above and Fig. 3 to Fig. 6
The associated description of the semiconductor devices shown, details are not described herein again.
Referring to Fig.1 3, etching removes a part for the metal layer 332 and metal barrier 330, the metal layer after etching
332 surfaces have recess 334.
Specifically, the recess 334 can be self-assembling formation during forming metal layer 332.For example, by using tungsten
When as the metal layer 332, since the Step Coverage performance of tungsten is weaker (Poor Step Coverage), metal layer is being formed
Recess 334 can be formed during 332.
It should be pointed out that when using other metals as the metal layer 332, it can also be by forming metal layer
Adjusting process parameter during 332 either performs etching or uses other processes, shape after forming metal layer 332
At recess 334.
In embodiments of the present invention, since 332 surface of metal layer has recess 334, the tensile stress layer being subsequently formed
240 can cover the recess 334 helps compensate for gold to form tensile stress to the dielectric film 320 around recess 334
Belong to the compression that layer 332 and metal barrier 330 form dielectric film 320.
Referring to Fig.1 4, tensile stress layer 340 is formed, the tensile stress layer 340 is filled 334 (referring to Fig.1 3) of the recess and covered
332 surface of metal layer other than the recess 334 is covered, then etching removes the drawing in the isolated groove 310 (referring to Fig.1 2)
A part for stressor layers 340.
In embodiments of the present invention, the tensile stress layer 340 can cover the recess 334, around to recess 334
Dielectric film 320 and tensile stress layer 340 around dielectric film 320 formed tensile stress, help compensate for metal layer 332 with
And the compression that metal barrier 330 forms dielectric film 320.
The material of the tensile stress layer 340 can be boron doped SiGe (Boron doped-SiGe), can also be
Other materials appropriate for providing tensile stress.
It is understood that distance of the upper surface of the tensile stress layer 340 after etching apart from the surface of semiconductor substrate 300
Should not too far, tensile stress layer 340, metal barrier 330 and the metal layer 332 otherwise formed is very few, it is difficult to realize and inhibit
Crosstalk and other effects；Distance of the upper surface of tensile stress layer 340 after etching apart from the surface of semiconductor substrate 300 should not mistake
Closely, the device performance of pixel transistor may otherwise be influenced.As a unrestricted example, the tensile stress layer after etching
Distance of 340 upper surface apart from the surface of semiconductor substrate 300 can be 0.2 μm to 0.3 μm, preferably 0.25 μm.
Referring to Fig.1 5, third dielectric layer 352 is formed, the third dielectric layer 352 fills 310 (reference of the isolated groove
Figure 12) and the tensile stress layer 340 is covered, ion implanting is carried out to the semiconductor substrate 300, in the semiconductor substrate
Photodiode doped region 380 is formed in 300.
Further, the 4th dielectric layer 354 is formed, the 4th dielectric layer 354 covers the semiconductor substrate 300 and the
Three dielectric layers, 352 surface.
Wherein, the material of the tensile stress layer 340 can be conductive material.
It in specific implementation, can also be flat using CMP process after forming the third dielectric layer 352
The smoothization third dielectric layer 352.
It should be pointed out that in specific implementation, can also be formed in the semiconductor substrate 300 according to specific requirements
Other doped regions.In embodiments of the present invention, for the type of the doped region specifically formed, specific Doped ions and its doping
Parameter is not limited.
It in specific implementation, can also be flat using CMP process after forming the 4th dielectric layer 354
Smoothization 4th dielectric layer 354.
Referring to Fig.1 6, the 4th dielectric layer 354 and third dielectric layer 352 are performed etching, to form contact hole 362,
The bottom-exposed of the contact hole 362 goes out the tensile stress layer 340, and plug 364 is filled in the contact hole 362.
Specifically, since the material of the tensile stress layer 340 is conductive material, apply voltage on plug 364, then draw and answer
Power layer 340 and metal barrier 330 can conduct the voltage.
In embodiments of the present invention, go out the contact hole 362 of tensile stress layer 340 by forming bottom-exposed, and contacting
In hole 362 fill plug 364, can by plug 364 apply appropriate type voltage (such as when carrier be electronics when
Apply negative voltage), make carrier of the isolated groove 310 (referring to Fig.1 2) between photodiode 380 far from isolated groove
310, carrier moving speed is helped to improve, to improve the speed ability of device.
In embodiments of the present invention, metal barrier 330 and tensile stress layer 340 are sequentially formed in isolated groove 310,
And tensile stress layer 340 fills at least part for the groove space that the metal barrier 330 and metal layer 332 surround, by
In the mechanical stress that 340 pairs of semiconductor substrate 300 of tensile stress layer generates with metal barrier 330 and metal layer 332 to partly leading
The stress types for the mechanical stress that body substrate 300 generates are on the contrary, metal barrier 330 and metal layer 332 can be reduced to half
The influence of the stress of conductor substrate 300, to reduce between the dielectric film 320 in isolated groove 310 and semiconductor substrate 300
Interface trap density, improve the performance of semiconductor devices.
It is possible to further fill metal layer 332 in the groove space that metal barrier 330 surrounds, and utilize metal
The recess 334 (referring to Fig.1 3) that 330 surface of layer have is arranged the tensile stress layer 340 and fills described in the recess 334 and covering
332 surface of metal layer other than recess 334, so as to improve dielectric film caused by metal layer 332 and metal barrier 330
Interface trap density between 320 and semiconductor substrate 300 improves the performance of semiconductor devices.
The principle of each step respective devices in forming method in relation to another imaging sensor shown in Figure 12 to Figure 16,
Specific implementation and advantageous effect please refer to each step in the forming method of the imaging sensor above and shown in Fig. 2 to Figure 11 and correspond to
The associated description of device, details are not described herein again.
In embodiments of the present invention, a kind of imaging sensor is additionally provided, referring to Fig.1 1, which can wrap
It includes：
Semiconductor substrate 200；
Isolated groove 210 (with reference to Fig. 5), is located in the semiconductor substrate 200；
Dielectric film 220 covers the inner wall of the isolated groove 210；
Metal barrier 230 covers the dielectric film 220；
Tensile stress layer 240 fills at least part of the groove space of the encirclement of the metal barrier 230.
Further, the tensile stress layer 240 can fill the complete of the groove space of the encirclement of the metal barrier 230
Portion.
Further, described image sensor can also include：First medium layer 252 fills the isolated groove 210 simultaneously
Cover the tensile stress layer 240 and metal barrier 230.
Further, the material of the tensile stress layer 240 can be conductive material, and described image sensor can also wrap
It includes：
Second dielectric layer 254 covers 252 surface of the semiconductor substrate 200 and first medium layer；
Contact hole 262 is located in the second dielectric layer 254 and first medium layer 252, and the bottom of the contact hole 262
Portion exposes the tensile stress layer 240；
Plug 264 is filled in the contact hole 262.
Further, the material of the tensile stress layer 240 can be boron doped SiGe.
The material of the metal barrier 230 can be titanium nitride or tantalum nitride.
It is please referred to above and shown in Fig. 2 to Figure 11 about the principle of the imaging sensor, specific implementation and advantageous effect
The associated description of forming method about imaging sensor, details are not described herein again.
In embodiments of the present invention, a kind of imaging sensor is additionally provided, referring to Fig.1 6, which can wrap
It includes：
Semiconductor substrate 300；
Isolated groove 310 (referring to Fig.1 2) is located in the semiconductor substrate 300；
Dielectric film 320 covers the inner wall of the isolated groove 310；
Metal barrier 330 covers the dielectric film 320；
Tensile stress layer 340 fills at least part of the groove space of the encirclement of the metal barrier 330.
Further, described image sensor can also include metal layer 332, be filled in the packet of the metal barrier 330
In the groove space enclosed, and 332 surface of the metal layer has 334 (referring to Fig.1 3) of recess, wherein the tensile stress layer 340
It fills the recess 334 and covers 332 surface of metal layer other than the recess 334.
Further, described image sensor can also include third dielectric layer 352, fill the isolated groove 310 simultaneously
Cover the tensile stress layer 340.
Further, the material of the tensile stress layer 340 can be conductive material, and described image sensor can also wrap
It includes：
4th dielectric layer 354 covers 352 surface of the semiconductor substrate 300 and third dielectric layer；
Contact hole 362 is located in the 4th dielectric layer 354 and third dielectric layer 352, and the bottom of the contact hole 362
Portion exposes the tensile stress layer 340；
Plug 364 is filled in the contact hole 362.
Further, the material of the tensile stress layer 340 can be boron doped SiGe.
The material of the metal barrier 330 can be titanium nitride or tantalum nitride.
It is please referred to above and shown in Fig. 2 to Figure 16 about the principle of the imaging sensor, specific implementation and advantageous effect
The associated description of forming method about imaging sensor, details are not described herein again.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (18)
1. a kind of forming method of imaging sensor, which is characterized in that include the following steps：
Semiconductor substrate is provided；
The semiconductor substrate is performed etching, to form isolated groove；
Dielectric film is formed, the dielectric film covers the inner wall of the isolated groove；
Metal barrier is formed, the metal barrier covers the dielectric film；
Tensile stress layer is formed, the tensile stress layer fills at least part for the groove space that the metal barrier surrounds.
2. the forming method of imaging sensor according to claim 1, which is characterized in that described in the tensile stress layer filling
The whole for the groove space that metal barrier surrounds.
3. the forming method of imaging sensor according to claim 2, which is characterized in that further include：
Etching removes a part for the tensile stress layer and metal barrier in the isolated groove；
First medium layer is formed, the first medium layer fills the isolated groove and covers the tensile stress layer and metal barrier
Layer.
4. the forming method of imaging sensor according to claim 3, which is characterized in that the material of the tensile stress layer is
Conductive material, the method further include：
Second dielectric layer is formed, the second dielectric layer covers the semiconductor substrate and first medium layer surface；
The second dielectric layer and first medium layer are performed etching, to form contact hole, the bottom-exposed of the contact hole goes out
The tensile stress layer；
Plug is filled in the contact hole.
5. the forming method of imaging sensor according to claim 1, which is characterized in that the formation tensile stress layer packet
It includes：
Metal layer is filled in the groove space that the metal barrier surrounds；
Etching removes a part for the metal layer and metal barrier, and the layer on surface of metal after etching has recess；
Tensile stress layer is formed, the tensile stress layer fills the recess and covers the layer on surface of metal other than the recess.
6. the forming method of imaging sensor according to claim 5, which is characterized in that further include：
Etching removes a part for the tensile stress layer in the isolated groove；
Third dielectric layer is formed, the third dielectric layer fills the isolated groove and covers the tensile stress layer.
7. the forming method of imaging sensor according to claim 6, which is characterized in that the material of the tensile stress layer is
Conductive material, the method further include：
The 4th dielectric layer is formed, the 4th dielectric layer covers the semiconductor substrate and third dielectric layer surface；
4th dielectric layer and third dielectric layer are performed etching, to form contact hole, the bottom-exposed of the contact hole goes out
The tensile stress layer；
Plug is filled in the contact hole.
8. the forming method of imaging sensor according to any one of claims 1 to 7, which is characterized in that the tensile stress
The material of layer is boron doped SiGe.
9. the forming method of imaging sensor according to any one of claims 1 to 7, which is characterized in that the metal resistance
The material of barrier is titanium nitride or tantalum nitride.
10. a kind of imaging sensor, which is characterized in that including：
Semiconductor substrate；
Isolated groove is located in the semiconductor substrate；
Dielectric film covers the inner wall of the isolated groove；
Metal barrier covers the dielectric film；
Tensile stress layer fills at least part for the groove space that the metal barrier surrounds.
11. imaging sensor according to claim 10, which is characterized in that the tensile stress layer fills the metal barrier
The whole for the groove space that layer surrounds.
12. imaging sensor according to claim 11, which is characterized in that further include：
First medium layer fills the isolated groove and covers the tensile stress layer and metal barrier.
13. imaging sensor according to claim 12, which is characterized in that the material of the tensile stress layer is conduction material
Expect, further includes：
Second dielectric layer covers the semiconductor substrate and first medium layer surface；
Contact hole is located in the second dielectric layer and first medium layer, and the bottom-exposed of the contact hole goes out the drawing and answers
Power layer；
Plug is filled in the contact hole.
14. imaging sensor according to claim 10, which is characterized in that further include：
Metal layer is filled in the groove space that the metal barrier surrounds, and the layer on surface of metal has recess；
Wherein, the tensile stress layer fills the recess and covers the layer on surface of metal other than the recess.
15. imaging sensor according to claim 14, which is characterized in that further include：
Third dielectric layer fills the isolated groove and covers the tensile stress layer.
16. imaging sensor according to claim 15, which is characterized in that the material of the tensile stress layer is conduction material
Expect, further includes：
4th dielectric layer covers the semiconductor substrate and third dielectric layer surface；
Contact hole is located in the 4th dielectric layer and third dielectric layer, and the bottom-exposed of the contact hole goes out the drawing and answers
Power layer；
Plug is filled in the contact hole.
17. according to claim 10 to 16 any one of them imaging sensor, which is characterized in that the material of the tensile stress layer
For boron doped SiGe.
18. according to claim 10 to 16 any one of them imaging sensor, which is characterized in that the material of the metal barrier
Material is titanium nitride or tantalum nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810083564.4A CN108281444A (en) | 2018-01-29 | 2018-01-29 | Imaging sensor and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810083564.4A CN108281444A (en) | 2018-01-29 | 2018-01-29 | Imaging sensor and forming method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108281444A true CN108281444A (en) | 2018-07-13 |
Family
ID=62805613
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810083564.4A Pending CN108281444A (en) | 2018-01-29 | 2018-01-29 | Imaging sensor and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108281444A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109216389A (en) * | 2018-08-24 | 2019-01-15 | 德淮半导体有限公司 | Back side illumination image sensor and its manufacturing method |
| CN109585479A (en) * | 2018-11-30 | 2019-04-05 | 长江存储科技有限责任公司 | A kind of semiconductor devices and forming method thereof |
| CN110246856A (en) * | 2019-06-14 | 2019-09-17 | 芯盟科技有限公司 | Forming method, imaging sensor and its working method of imaging sensor |
| CN110610954A (en) * | 2019-10-18 | 2019-12-24 | 德淮半导体有限公司 | Image sensor and forming method thereof |
| CN115831988A (en) * | 2021-09-17 | 2023-03-21 | 北京弘图半导体有限公司 | Deep trench isolation structure for image sensor |
| CN116169151A (en) * | 2023-04-25 | 2023-05-26 | 合肥晶合集成电路股份有限公司 | Semiconductor structure, manufacturing method of semiconductor structure and image sensor device |
| CN117153855A (en) * | 2023-10-30 | 2023-12-01 | 合肥晶合集成电路股份有限公司 | Semiconductor structure of back-illuminated image sensor and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347337A (en) * | 2010-07-26 | 2012-02-08 | 格科微电子（上海）有限公司 | CMOS (complementary metal-oxide semiconductor) image sensor with irradiation on back surface |
| CN104201184A (en) * | 2014-09-24 | 2014-12-10 | 格科微电子（上海）有限公司 | Image sensor and forming method thereof |
| CN105489621A (en) * | 2014-10-06 | 2016-04-13 | 意法半导体(克洛尔2)公司 | Back-illuminated integrated imaging device with simplified interconnect routing |
| US9659989B1 (en) * | 2016-04-19 | 2017-05-23 | Omnivision Technologies, Inc. | Image sensor with semiconductor trench isolation |
-
2018
- 2018-01-29 CN CN201810083564.4A patent/CN108281444A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347337A (en) * | 2010-07-26 | 2012-02-08 | 格科微电子（上海）有限公司 | CMOS (complementary metal-oxide semiconductor) image sensor with irradiation on back surface |
| CN104201184A (en) * | 2014-09-24 | 2014-12-10 | 格科微电子（上海）有限公司 | Image sensor and forming method thereof |
| CN105489621A (en) * | 2014-10-06 | 2016-04-13 | 意法半导体(克洛尔2)公司 | Back-illuminated integrated imaging device with simplified interconnect routing |
| US9659989B1 (en) * | 2016-04-19 | 2017-05-23 | Omnivision Technologies, Inc. | Image sensor with semiconductor trench isolation |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109216389A (en) * | 2018-08-24 | 2019-01-15 | 德淮半导体有限公司 | Back side illumination image sensor and its manufacturing method |
| CN109216389B (en) * | 2018-08-24 | 2020-12-04 | 德淮半导体有限公司 | Backside illuminated image sensor and method of manufacturing the same |
| CN109585479A (en) * | 2018-11-30 | 2019-04-05 | 长江存储科技有限责任公司 | A kind of semiconductor devices and forming method thereof |
| CN110246856A (en) * | 2019-06-14 | 2019-09-17 | 芯盟科技有限公司 | Forming method, imaging sensor and its working method of imaging sensor |
| CN110246856B (en) * | 2019-06-14 | 2022-03-15 | 芯盟科技有限公司 | Image sensor forming method, image sensor and working method thereof |
| CN110610954A (en) * | 2019-10-18 | 2019-12-24 | 德淮半导体有限公司 | Image sensor and forming method thereof |
| CN115831988A (en) * | 2021-09-17 | 2023-03-21 | 北京弘图半导体有限公司 | Deep trench isolation structure for image sensor |
| CN116169151A (en) * | 2023-04-25 | 2023-05-26 | 合肥晶合集成电路股份有限公司 | Semiconductor structure, manufacturing method of semiconductor structure and image sensor device |
| CN117153855A (en) * | 2023-10-30 | 2023-12-01 | 合肥晶合集成电路股份有限公司 | Semiconductor structure of back-illuminated image sensor and manufacturing method thereof |
| CN117153855B (en) * | 2023-10-30 | 2024-03-01 | 合肥晶合集成电路股份有限公司 | Semiconductor structure of back-illuminated image sensor and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108281444A (en) | Imaging sensor and forming method thereof | |
| KR100971803B1 (en) | Semiconductor device having a metal gate electrode formed on an annealed high-? gate dielectric layer | |
| US9373702B2 (en) | Carbon-doped cap for a raised active semiconductor region | |
| JP5318955B2 (en) | Shallow trench isolation structure having air gap, CMOS image sensor using the same, and method for manufacturing CMOS image sensor | |
| US8309448B2 (en) | Method for forming buried word line in semiconductor device | |
| JP5374980B2 (en) | Solid-state imaging device | |
| US7897514B2 (en) | Semiconductor contact barrier | |
| US10204822B2 (en) | Method for forming trench liner passivation | |
| CN107946330A (en) | Imaging sensor and forming method thereof | |
| CN109427834A (en) | Improve the image sensor apparatus and its manufacturing method of shutter efficiency | |
| KR20140028944A (en) | Semiconductor device and method for fabricating the same | |
| KR102641186B1 (en) | Back-side deep trench isolation structure for image sensor | |
| TW201218379A (en) | Strained structure of a p-type field effect transistor | |
| JP2013089889A (en) | Semiconductor device and method for manufacturing the same | |
| KR100603588B1 (en) | Semiconductor device with low contact resistance and method for fabricating the same | |
| CN108281439A (en) | Imaging sensor and forming method thereof | |
| CN108766953B (en) | Semiconductor device and method of forming the same | |
| US11121169B2 (en) | Metal vertical transfer gate with high-k dielectric passivation lining | |
| CN208655648U (en) | Semiconductor devices | |
| FR2647267A1 (en) | Dynamic random-access memory cell and method of manufacture | |
| US10446559B2 (en) | Method of fabricating DRAM | |
| KR20100076257A (en) | Semiconductor device and method for manufacturing the same | |
| CN209401624U (en) | Semiconducting gate structure | |
| CN114975490A (en) | Image sensor forming method and image sensor | |
| CN110610954A (en) | Image sensor and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20180713 |