CN109216389B - Backside illuminated image sensor and method of manufacturing the same - Google Patents

Backside illuminated image sensor and method of manufacturing the same Download PDF

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Publication number
CN109216389B
CN109216389B CN201810970047.9A CN201810970047A CN109216389B CN 109216389 B CN109216389 B CN 109216389B CN 201810970047 A CN201810970047 A CN 201810970047A CN 109216389 B CN109216389 B CN 109216389B
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substrate
trench
semiconductor material
image sensor
doping concentration
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CN109216389A (en
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黄心怡
鲸井裕
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Huaian Xide Industrial Design Co ltd
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Huaian Imaging Device Manufacturer Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14621—Colour filter arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof

Abstract

The present disclosure relates to a back-illuminated image sensor and a method of manufacturing the same. The back-illuminated image sensor includes a substrate having a first conductivity type and having a first doping concentration, the substrate having a first surface and a second surface opposite to the first surface; the substrate comprises pixel regions and an isolation region between the pixel regions, wherein the isolation region comprises a trench extending from the first surface to the second surface, the trench comprising: a trench liner layer on sidewalls of the trench, a semiconductor material of the first conductivity type at a bottom of the trench, and an insulating material in a portion of the trench proximate the first surface, wherein the semiconductor material has a second doping concentration higher than the first doping concentration.

Description

Backside illuminated image sensor and method of manufacturing the same
Technical Field
The present disclosure relates to a back-illuminated image sensor and a method of manufacturing the same.
Background
The image sensor may be used to sense radiation (e.g., optical radiation, including but not limited to visible light, infrared, ultraviolet, etc.). Image sensors may be classified into backside-illuminated (BSI) image sensors and front-illuminated (FSI) image sensors according to the manner in which they receive radiation.
BSI image sensors are capable of receiving radiation from their backside. Unlike FSI image sensors, in BSI image sensors, wiring and the like may affect radiation reception substantially on the front side of the substrate, while light is incident from the back side of the substrate.
For BSI image sensors, conventional techniques include, for example, the following steps: an epitaxial layer is grown on a substrate, a photo-sensing device (e.g., a photodiode) is fabricated on the epitaxial layer, and then the substrate is removed from the backside, wherein the epitaxial layer serves as a stop layer for removing the substrate. However, in the case of fabricating a BSI image sensor using a substrate and an epitaxial layer on the substrate, it is difficult to precisely control the thickness of the epitaxial layer for forming a photodiode when removing the substrate. In addition, since the substrate and the epitaxial layer on the substrate are used in manufacturing the BSI image sensor and then the substrate is removed, the manufacturing cost is high.
Accordingly, it is desirable to provide a technique that enables better control of the thickness of the semiconductor layers used to form the photo-sensing devices of BSI image sensors and that is less costly to manufacture.
Disclosure of Invention
It is an object of some embodiments of the present disclosure to provide a novel technique that better controls the thickness of the semiconductor layers forming the photo-sensing devices of BSI image sensors and is less costly to manufacture.
It is another object of embodiments of the present disclosure to provide a novel BSI image sensor and a method of manufacturing the same.
According to an aspect of the present disclosure, there is provided a BSI image sensor including: a substrate having a first conductivity type and having a first doping concentration, the substrate having a first surface and a second surface opposite the first surface; the substrate comprises pixel regions and an isolation region between the pixel regions, wherein the isolation region comprises a trench extending from the first surface to the second surface, the trench comprising: a trench liner layer on sidewalls of the trench, a semiconductor material of the first conductivity type at a bottom of the trench, and an insulating material in a portion of the trench proximate the first surface, wherein the semiconductor material has a second doping concentration higher than the first doping concentration.
According to another aspect of the present disclosure, there is provided a method of manufacturing a BSI image sensor, including: providing a substrate having a first surface and a second surface opposite the first surface, the substrate having a first conductivity type and having a first doping concentration; forming a first trench from a first surface of the substrate; forming a trench liner layer on a bottom surface and sidewalls of the first trench; removing the trench liner layer on the bottom surface of the first trench; forming a second trench communicating with the first trench from a bottom surface of the first trench; filling the first trench and the second trench with a semiconductor material having a first conductivity type, the semiconductor material having a second doping concentration that is greater than the first doping concentration of the substrate; performing annealing to cause impurities in the semiconductor material in the second trench to diffuse into the substrate to form a diffused portion of semiconductor material in the substrate having a doping concentration greater than a first doping concentration of the substrate; removing a portion of the semiconductor material located in the first trench and filling a portion of the first trench not filled with the semiconductor material with an insulating material; and thinning the substrate from the second surface of the substrate, wherein the diffused portion of semiconductor material serves as the stop layer for the thinning.
According to the embodiments of the present disclosure, by forming a trench from a first surface (e.g., a front surface) of a substrate, filling a bottom of the trench with a highly doped semiconductor material, wherein the highly doped semiconductor material is used as a stopper layer, when thinning the substrate from a back surface, a thickness of a semiconductor layer used to form a photo sensing device of a BSI image sensor can be precisely controlled. Meanwhile, since the substrate and the epitaxial layer on the substrate are not used and then the substrate is removed, the manufacturing cost of the BSI image sensor is reduced.
Other features of the present disclosure and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The drawings are for illustration purposes only and are not necessarily drawn to scale. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure, in which:
fig. 1A and 1B are schematic partial cross-sectional views of BSI image sensors in accordance with some embodiments of the present disclosure;
fig. 2 is a flow chart of a method of manufacturing a BSI image sensor in accordance with some embodiments of the present disclosure;
fig. 3A to 3I schematically show cross-sectional views of a semiconductor device corresponding to part of the steps of the method shown in fig. 2.
Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same portions or portions having the same functions, and a repetitive description thereof will be omitted. In this specification, like reference numerals and letters are used to designate like items, and therefore, once an item is defined in one drawing, further discussion thereof is not required in subsequent drawings.
For convenience of understanding, the positions, sizes, ranges, and the like of the respective structures shown in the drawings and the like do not sometimes indicate actual positions, sizes, ranges, and the like. Accordingly, the disclosure is not limited to the positions, dimensions, ranges, etc., disclosed in the drawings and the like.
Detailed Description
Hereinafter, embodiments disclosed in the present specification will be described in detail with reference to the drawings. It should be understood, however, that the description of various embodiments is illustrative only and is not intended to limit the claimed invention in any way. Unless specifically stated otherwise or the context or principles thereof indicate or imply, the relative arrangement of components and steps, expressions and values, etc. in the exemplary embodiments are not to be considered as limiting the invention as claimed in this application. In this specification, techniques, methods and apparatus that are known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. It will be understood that the terms "comprises/comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The terms "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
In the present disclosure, the term "providing" is used broadly to encompass all ways of obtaining an object, and thus "providing an object" includes, but is not limited to, "purchasing," "preparing/manufacturing," "arranging/setting," "installing/assembling," and/or "ordering" the object, and the like.
In the present disclosure, ordinal terms such as "first", "second", "third", etc., are labeled to avoid confusion of constituent elements and are not used for priority in any respect.
Fig. 1A and 1B are schematic partial cross-sectional views of a backside illuminated (BSI) image sensor according to some embodiments of the present disclosure.
As shown in fig. 1A, the BSI image sensor 100 includes a substrate 101. The substrate 101 may be composed of a unitary semiconductor material (such as silicon or germanium) or a compound semiconductor (such as silicon carbide, silicon germanium, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide), or a combination thereof. There is no particular limitation on the substrate 101 as long as it is suitable for forming therein a photodiode for sensing radiation.
In some embodiments, the substrate 101 may have a first conductivity type and have a first doping concentration. As shown in fig. 1A, the substrate 101 may have a first surface 1011 and a second surface 1013 opposite the first surface 1011.
As shown in fig. 1A, the substrate 101 includes pixel regions 103 and isolation regions 105 between the pixel regions 103. The isolation region 105 includes a trench extending from the first surface 1011 to the second surface 1013 of the substrate 101. In one example, the trench may be formed by etching from the first surface 1011 of the substrate 101. In some embodiments, the depth of the trench is, for example, 2.5 to 3 microns. In some embodiments, the width of the trench (e.g., the width of the trench opening) is, for example, 0.1 to 0.3 microns. Those skilled in the art will appreciate that the depth and width of the grooves may be set as desired. Embodiments of the present disclosure are not limited in this regard.
As shown in fig. 1A, the trench in the isolation region 105 includes: a trench liner layer 1055 on the sidewalls of the trench, a semiconductor material 1051 at the bottom of the trench, and an insulating material 1053 in the portion of the trench proximate the first surface 1011.
In some embodiments, the semiconductor material 1051 can have a first conductivity type and have a second doping concentration that is higher than the first doping concentration of the substrate 101.
In some embodiments, the insulating material 1053 comprises a material that can be formed from, for example, but not limited to, an oxide of silicon, a nitride of silicon, an oxynitride or oxynitride of silicon, or any combination thereof. The insulating material 1053 can be formed by CVD, PVD, spin-on-dielectric (SOD) process, or other suitable technique.
In some embodiments, as shown in fig. 1A, a trench liner layer 1055 is located on the sidewalls of the trench. The trench liner layer 1055 may be formed of, for example, but not limited to, an oxide of silicon, a nitride of silicon, an oxynitride or oxynitride of silicon, or any combination thereof. The trench liner layer 1055 may be formed by CVD, PVD, spin coating, Spin On Dielectric (SOD) process, or other suitable technique. The trench liner layer 1055 may, for example, serve to limit diffusion of the semiconductor material 1051 in the trench into the substrate 101.
In some embodiments, as shown in fig. 1B, BSI image sensor 100 also includes contact structure 107 that extends from first surface 1011 of substrate 101 through insulating material 1053 in the trench to contact semiconductor material 1051 in the trench. The contact structure 107 is formed of, for example, a metal material, and serves to ground the semiconductor material 1051 in the trench, thereby reducing dark current.
In some embodiments, as shown in fig. 1B, the isolation region 105 of the BSI image sensor 100 also includes a second semiconductor material 1057 surrounding sidewalls of the trench in the substrate 101. The second semiconductor material 1057 has the first conductivity type. The second semiconductor material 1057 is used, for example, to prevent dark current from increasing when a depletion region of a photodiode formed in a pixel region is close to a trench.
In some embodiments, BSI image sensor 100 also includes a photodiode and a transfer transistor (not shown in fig. 1A and 1B) located adjacent to first surface 1011 of substrate 101 in pixel region 103. The photodiode is operable to generate photo-generated carriers in response to illumination, and the transfer transistor collects the photo-generated carriers generated by the photodiode to generate an electrical signal in response to illumination.
In some embodiments, BSI image sensor 100 further includes a back end of line BEOL metallization stack (not shown in fig. 1A and 1B) coupled to the first surface 1011 of substrate 101. The back end of line BEOL metallization stack may be disposed over a first surface 1011 of the substrate 101 and coupled to route signals to or from the BSI image sensor 100.
The BEOL metallization stack may include a plurality of metallization layers stacked within an interlayer dielectric layer. One or more contacts of the BEOL metallization stack extend from the metallization layer to the pixel cell. Further, one or more vias of the BEOL metallization stack extend between the metallization layers to interconnect the metallization layers.
In some embodiments, as shown in fig. 1A and 1B, BSI image sensor 100 may further include an optical filter 1032 on second surface 1013 of substrate 101 and a microlens 1034 on optical filter 1032. Microlens 1034 is used to focus light received from the backside of BSI image sensor 100 to a pixel area for substrate 101. A filter 1032 between the microlens 1034 and the second surface 1013 of the substrate 101 is used to filter light received from the backside of the BSI image sensor 100.
The filters may include, for example, a red filter, a green filter, and a blue filter. Of course, the filters may have filters of other colors as desired. The filter may comprise a coloured or tinted material, such as acrylic. For example, polymethylmethacrylate ("PMMA") or propylene glycol monostearate ("PGMS") are suitable materials that can be used to add pigments or dyes to form the optical filter. However, other materials may also be used.
The microlens may be made of a transparent organic material, an inorganic compound material, and have a convex lower surface. The microlenses may be centered or slightly offset in the pixel cells of the BSI image sensor.
Fig. 2 is a flow chart of a method 200 of manufacturing BSI image sensor 100 in accordance with some embodiments of the present disclosure. Fig. 3A through 3I schematically illustrate partial cross-sectional views of BSI image sensor 100 at some of the steps of the method illustrated in fig. 2.
The following description will be made with reference to fig. 2 and fig. 3A to 3I. In the figure labeled (a), an example of one groove is shown, and on the way labeled (b), an example of a plurality of grooves (specifically, 3 grooves) is shown. However, one skilled in the art will appreciate that the number of grooves may be set as desired, and embodiments of the present disclosure are not limited in this regard.
In step S201, as shown in fig. 3A, a substrate 101 is provided. The substrate 101 has a first conductivity type and has a first doping concentration. As shown in fig. 3A, the substrate 101 has a first surface 1011 and a second surface 1015 opposite the first surface 1011. In fig. 3A, for convenience of illustration, the first surface 1011 and the second surface 1015 of the substrate 101 and portions of the substrate 101 near the first surface 1011 and the second surface 1015 are indicated by solid lines, and a middle portion of the substrate 101 is indicated by broken lines.
In step S202, as shown in fig. 3B, a first trench is formed from the first surface 1011 of the substrate 101. In some embodiments, this step may include wet etching from the first surface 1011 of the substrate 101 to form a first trench.
In some embodiments, this step may include, for example: forming a first insulating material (e.g., silicon oxide with a thickness of 5nm) on a first surface 1011 of the substrate 101; depositing a second insulating material (e.g., silicon nitride with a thickness of 40 nm) over the first insulating material; depositing a third insulating material (e.g., silicon oxide with a thickness of 100 nm) over the second insulating material; performing trench lithography (e.g., the opening width of the trench to be formed is about 0.1 to 0.3 μm); performing a first etching to remove the insulating material (including the first insulating material, the second insulating material, and the third insulating material) on the first surface of the substrate in a region corresponding to the trench to be formed; and performing a second etch (e.g., a wet etch) to form a first trench in the substrate 101.
In some embodiments, the depth of the first trench formed may be controlled by controlling a parameter (e.g., time) of the second etch. In some embodiments, the first trench is formed to a depth of about 3.5 microns.
It should be understood that the drawings are not drawn to scale in order to clearly illustrate the trenches and their associated structures. I.e., the trenches and related structures are exaggerated relative to the rest of the substrate 101 to show further details thereof. In fact, the bottom of the trench is a much greater distance from the second surface 1015 of the substrate 101 than is shown in fig. 3B.
In step S203, as shown in fig. 3C, a trench liner layer is formed on the bottom surface and the sidewalls of the formed first trench. The trench liner layer may be formed of, for example but not limited to, an oxide of silicon, a nitride of silicon, an oxynitride or oxynitride of silicon, or any combination thereof. The trench liner layer may be formed by CVD, PVD, spin coating, Spin On Dielectric (SOD) process, or other suitable technique. The trench liner layer may be used, for example, to limit diffusion of the semiconductor material 1051 in the trench into the substrate 101.
In some embodiments, the trench liner layer includes silicon oxide and silicon nitride. This step may for example comprise depositing silicon oxide (thickness for example 10nm), performing in situ water vapour generation (ISSG) to improve the quality of the generated silicon oxide (thickness of silicon oxide for example 15nm after ISSG); and depositing silicon nitride (thickness of, for example, 10 nm).
In step S204, as shown in fig. 3D, at least the trench liner layer on the bottom surface of the first trench is removed.
In some embodiments, the step may include performing an etch-back that removes a trench liner layer located over the first surface of the substrate and a trench liner layer on a bottom surface of the first trench.
In step S205, as shown in fig. 3E, a second trench communicating with the first trench is formed from the bottom surface of the first trench.
In some embodiments, the second trench communicating with the first trench may be formed by wet etching from a bottom surface of the first trench.
In some embodiments, the depth of the second trench formed may be controlled by controlling parameters (e.g., time) of the wet etch that forms the second trench. In some embodiments, the second trench is formed to a depth of about 2 microns.
In step S206, as shown in fig. 3F, the first trench and the second trench are filled with a semiconductor material. The semiconductor material has a first conductivity type and has a second doping concentration that is greater than the first doping concentration of the substrate.
In some embodiments, this step may further comprise: after filling the first trench and the second trench with a semiconductor material, performing an etch-back of the semiconductor material; and depositing a cap oxide after the etch back.
In step S207, as shown in fig. 3G, annealing is performed so that the impurity in the portion of the semiconductor material located in the second trench is diffused into the substrate 101 to form a semiconductor material diffusion portion having a higher doping concentration than the substrate in the substrate.
Further, as shown in (b) of fig. 3G, after the annealing is performed, for the adjacent second trenches, the semiconductor material diffusion portions thereof will be connected together, thereby forming one layer of the semiconductor material diffusion portion.
When annealing is performed, the trench liner layer on the side wall of the first trench prevents diffusion of impurities in the semiconductor material in the first trench into the substrate, and therefore only impurities in a portion of the semiconductor material located in the second trench diffuse into the substrate, thereby forming a semiconductor material diffusion portion. The extent of diffusion of the impurity of the semiconductor material in the second trench into the substrate (i.e. the width of the diffused portion of semiconductor material) may be controlled by controlling parameters of the anneal, such as temperature, time, etc.
In step S208, as shown in fig. 3H, a portion of the semiconductor material located in the first trench is removed, and a portion of the first trench not filled with the semiconductor material is filled with an insulating material.
In some embodiments, removing a portion of the semiconductor material located in the first trench may include: removing the capping oxide; an etch back is performed from the first surface 1011 of the substrate to remove insulating material on the first surface 1011 of the substrate and a portion of the semiconductor material located in the first trench. In this etch-back step, the semiconductor material located in the first trench is recessed with respect to the first surface 1011 of the substrate 101 due to the different etch rates of the insulating material and the semiconductor material, i.e. the first trench is not completely filled with the semiconductor material.
In step S209, the substrate 101 is thinned from the second surface of the substrate 101, as shown in fig. 3I, wherein the diffused portion of semiconductor material serves as a stop layer for the thinning.
In this step, the semiconductor material diffusion portion serves as a thinned stop layer, since the etch rate in the highly doped semiconductor material (in this example, the semiconductor material diffusion portion) is smaller than in the semiconductor substrate for wet etching.
In some embodiments, step S209 includes: removing a portion of the substrate 101 closer to the second surface 1015 than the semiconductor material diffusion portion such that the semiconductor material diffusion portion is exposed; and removing the semiconductor material diffusion portion.
In some embodiments, removing portions of the substrate 101 closer to the second surface 1015 than the diffused portions of semiconductor material comprises: grinding from the second surface 1015 of the substrate 101 so that the thickness of the substrate 101 is reduced as a whole; and performing a first wet etch to further remove portions of the substrate closer to the second surface 1015 than the diffused portions of the semiconductor material.
In some embodiments, removing the diffused portion of semiconductor material comprises: polishing the exposed surface of the diffused portion of semiconductor material; and performing a second wet etch to remove the semiconductor material diffusion.
In some embodiments, the thickness of the substrate 101 is 2.5 to 3 microns after thinning. Those skilled in the art will appreciate that the thickness of the obtained substrate 101 can be set as desired, and the thickness of the obtained substrate 101 can be precisely controlled by controlling the process parameters (e.g., etching time, etc.) during the thinning process. In addition, since the substrate and the epitaxial layer on the substrate are not used in manufacturing the BSI image sensor and then the substrate is removed, a reduction in manufacturing cost of the BSI image sensor is achieved.
In some embodiments, the method 200 further comprises: an optical filter and a microlens on the optical filter are formed on the second surface 1013 of the thinned substrate 101. The microlenses are used to focus light received from the backside of BSI image sensor 100 to the pixel areas of the substrate. A filter between the microlens and the second surface 1013 of the thinned substrate 101 is used to filter light received from the backside.
In some embodiments, prior to filling the portion of the first trench not filled with the semiconductor material with the insulating material, the method 200 further comprises: a second semiconductor material is formed in the substrate 101 surrounding the sidewalls of the first trench, the second semiconductor material having the same first conductivity type as the substrate. In some embodiments, the second semiconductor material may be formed in the substrate 101 by performing ion implantation. The second semiconductor material is used, for example, to prevent dark current from increasing when a depletion region of a photodiode formed in the pixel region is close to the trench.
In some embodiments, the method 200 further comprises: prior to thinning the substrate 101, contact structures are formed from the first surface of the substrate 101 that extend through the oxide to contact the semiconductor material. The contact structure is formed of, for example, a metal material, and serves to ground the semiconductor material in the trench, thereby reducing dark current.
In some embodiments, the method 200 further comprises: before thinning the substrate 101, a photodiode and a transfer transistor are formed adjacent to a first surface of the substrate 101. The photodiode is operable to generate photo-generated carriers in response to illumination, and the transfer transistor collects the photo-generated carriers generated by the photodiode to generate an electrical signal in response to illumination.
In some embodiments, the method 200 further comprises: before thinning the substrate 101, a back end of line BEOL metallization stack (not shown) is formed on the first surface 1011 of the substrate 101. The back end of line BEOL metallization stack is coupled to route signals to and from the BSI image sensor 100.
It should also be understood that the present disclosure also contemplates the following.
Item 8, a method for manufacturing a back-illuminated image sensor, comprising:
providing a substrate having a first surface and a second surface opposite the first surface, the substrate having a first conductivity type and having a first doping concentration;
forming a first trench from a first surface of the substrate;
forming a trench liner layer on a bottom surface and sidewalls of the first trench;
removing the trench liner layer on the bottom surface of the first trench;
forming a second trench communicating with the first trench from a bottom surface of the first trench;
filling the first trench and the second trench with a semiconductor material having a first conductivity type, the semiconductor material having a second doping concentration that is greater than the first doping concentration of the substrate;
performing annealing to cause impurities in the semiconductor material in the second trench to diffuse into the substrate to form a diffused portion of semiconductor material in the substrate having a doping concentration greater than a first doping concentration of the substrate;
removing a portion of the semiconductor material located in the first trench and filling a portion of the first trench not filled with the semiconductor material with an insulating material; and
thinning the substrate from the second surface of the substrate, wherein the diffused portion of semiconductor material serves as the stop layer for the thinning.
Item 9 the method of item 8, further comprising:
prior to thinning the substrate, forming contact structures from a first surface of the substrate extending through insulating material in the first trench to contact semiconductor material in the first trench.
Item 10, the method of item 8, further comprising:
forming a second semiconductor material in the substrate surrounding sidewalls of the first trench prior to filling portions of the first trench not filled with the semiconductor material with an insulating material, wherein the second semiconductor material is of a first conductivity type.
Item 11, the method of item 8, further comprising:
before thinning the substrate, a photodiode and a transfer transistor are formed adjacent to a first surface of the substrate.
Item 12 the method of item 11, further comprising:
a back end of line BEOL metallization stack is formed on a first surface of the substrate before thinning the substrate and after forming the photodiode and the transfer transistor.
Item 13, the method of item 8, wherein the thinning comprises:
removing a portion of the substrate closer to the second surface than the semiconductor material diffusion portion such that the semiconductor material diffusion portion is exposed; and
and removing the semiconductor material diffusion part.
Item 14, the method of item 13, wherein removing a portion of the substrate closer to the second surface than the diffused portion of semiconductor material comprises:
grinding from the second surface of the substrate so that the thickness of the substrate is reduced as a whole; and
a first wet etch is performed to further remove portions of the substrate closer to the second surface than the semiconductor material diffusion portions.
Item 15, the method of item 14, wherein removing the diffused portion of semiconductor material comprises:
polishing the exposed surface of the diffused portion of semiconductor material; and
a second wet etch is performed to remove the semiconductor material diffusion.
Item 16. the method of item 8, further comprising:
and forming an optical filter and a micro lens on the optical filter on the second surface of the thinned substrate.
Item 17, the method of item 8, wherein the substrate has a thickness of 2.5 to 3 micrometers after thinning.
Those skilled in the art will appreciate that the boundaries between the above described operations merely illustrative. Multiple operations may be combined into a single operation, single operations may be distributed in additional operations, and operations may be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. However, other modifications, variations, and alternatives are also possible. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Various embodiments of the present disclosure have been described above, but the above description is only exemplary and not exhaustive, and the present disclosure is not limited to the various embodiments disclosed. The various embodiments disclosed herein may be combined in any combination without departing from the spirit and scope of the present disclosure. Many modifications and variations will be apparent to those of ordinary skill in the relevant art in light of the teachings herein of this disclosure, and are intended to be included within the spirit and scope of this disclosure. The scope of the present disclosure is defined by the appended claims.

Claims (17)

1. A backside illuminated image sensor, comprising:
a substrate having a first conductivity type and having a first doping concentration, the substrate having a first surface and a second surface opposite the first surface;
the substrate comprises pixel regions and an isolation region between the pixel regions, wherein the isolation region comprises a trench extending from the first surface to the second surface, the trench comprising: a trench liner layer on sidewalls of the trench, a semiconductor material of the first conductivity type in a bottom of the trench proximate the second surface, and an insulating material in a portion of the trench proximate the first surface, wherein the semiconductor material has a second doping concentration higher than the first doping concentration.
2. The back-illuminated image sensor of claim 1, further comprising a contact structure extending from the first surface of the substrate through the insulating material in the trench to contact the semiconductor material in the trench.
3. The back-illuminated image sensor of claim 1, wherein the isolation region further comprises a second semiconductor material in the substrate surrounding sidewalls of the trench, wherein the second semiconductor material is of the first conductivity type.
4. The back-illuminated image sensor of claim 1, further comprising a photodiode and a transfer transistor located in the pixel region adjacent to the first surface of the substrate.
5. The back-illuminated image sensor of claim 4, further comprising a back-end-of-line BEOL metallization stack coupled to the first surface of the substrate.
6. The back-illuminated image sensor of claim 1, wherein the trench has a depth of 2.5 to 3 microns.
7. The back-illuminated image sensor of claim 1, further comprising an optical filter on the second surface of the substrate and a microlens on the optical filter.
8. A method for fabricating a back-illuminated image sensor, comprising:
providing a substrate having a first surface and a second surface opposite the first surface, the substrate having a first conductivity type and having a first doping concentration;
forming a first trench from a first surface of the substrate;
forming a trench liner layer on a bottom surface and sidewalls of the first trench;
removing the trench liner layer on the bottom surface of the first trench;
forming a second trench communicating with the first trench from a bottom surface of the first trench;
filling the first trench and the second trench with a semiconductor material having a first conductivity type, the semiconductor material having a second doping concentration that is greater than the first doping concentration of the substrate;
performing annealing to cause impurities in the semiconductor material in the second trench to diffuse into the substrate to form a diffused portion of semiconductor material in the substrate having a doping concentration greater than a first doping concentration of the substrate;
removing a portion of the semiconductor material located in the first trench and filling a portion of the first trench not filled with the semiconductor material with an insulating material; and
thinning the substrate from the second surface of the substrate, wherein the diffused portion of semiconductor material serves as the stop layer for the thinning.
9. The method of claim 8, further comprising:
prior to thinning the substrate, forming contact structures from a first surface of the substrate extending through insulating material in the first trench to contact semiconductor material in the first trench.
10. The method of claim 8, further comprising:
forming a second semiconductor material in the substrate surrounding sidewalls of the first trench prior to filling portions of the first trench not filled with the semiconductor material with an insulating material, wherein the second semiconductor material is of a first conductivity type.
11. The method of claim 8, further comprising:
before thinning the substrate, a photodiode and a transfer transistor are formed adjacent to a first surface of the substrate.
12. The method of claim 11, further comprising:
a back end of line BEOL metallization stack is formed on a first surface of the substrate before thinning the substrate and after forming the photodiode and the transfer transistor.
13. The method of claim 8, wherein the thinning comprises:
removing a portion of the substrate closer to the second surface than the semiconductor material diffusion portion such that the semiconductor material diffusion portion is exposed; and
and removing the semiconductor material diffusion part.
14. The method of claim 13, wherein removing a portion of the substrate closer to the second surface than the diffused portion of semiconductor material comprises:
grinding from the second surface of the substrate so that the thickness of the substrate is reduced as a whole; and
a first wet etch is performed to further remove portions of the substrate closer to the second surface than the semiconductor material diffusion portions.
15. The method of claim 14, wherein removing the semiconductor material diffusion comprises:
polishing the exposed surface of the diffused portion of semiconductor material; and
a second wet etch is performed to remove the semiconductor material diffusion.
16. The method of claim 8, further comprising:
and forming an optical filter and a micro lens on the optical filter on the second surface of the thinned substrate.
17. The method of claim 8, wherein the substrate has a thickness of 2.5 to 3 microns after thinning.
CN201810970047.9A 2018-08-24 2018-08-24 Backside illuminated image sensor and method of manufacturing the same Active CN109216389B (en)

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EP2416361A2 (en) * 2010-08-02 2012-02-08 Imec Arrays for CMOS imagers and their method of manufacturing
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CN108281444A (en) * 2018-01-29 2018-07-13 德淮半导体有限公司 Imaging sensor and forming method thereof

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EP2416361A2 (en) * 2010-08-02 2012-02-08 Imec Arrays for CMOS imagers and their method of manufacturing
CN108281439A (en) * 2018-01-23 2018-07-13 德淮半导体有限公司 Imaging sensor and forming method thereof
CN108281444A (en) * 2018-01-29 2018-07-13 德淮半导体有限公司 Imaging sensor and forming method thereof

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