CN114975490A - Image sensor forming method and image sensor - Google Patents
Image sensor forming method and image sensor Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 75
- 239000004065 semiconductor Substances 0.000 claims abstract description 110
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 238000002955 isolation Methods 0.000 claims description 61
- 238000000407 epitaxy Methods 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 13
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 claims description 3
- MIQVEZFSDIJTMW-UHFFFAOYSA-N aluminum hafnium(4+) oxygen(2-) Chemical compound [O-2].[Al+3].[Hf+4] MIQVEZFSDIJTMW-UHFFFAOYSA-N 0.000 claims description 3
- ZQXQADNTSSMHJI-UHFFFAOYSA-N hafnium(4+) oxygen(2-) tantalum(5+) Chemical compound [O-2].[Ta+5].[Hf+4] ZQXQADNTSSMHJI-UHFFFAOYSA-N 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 230000003287 optical effect Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14632—Wafer-level processed structures
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
Abstract
The invention provides an image sensor forming method and an image sensor, wherein the forming process of the image sensor at least comprises two bonding processes to a semiconductor substrate wafer; and forming a lateral PN junction and a pinning layer in the semiconductor substrate wafer before the first bonding, and forming a logic circuit region after the first bonding and before the second bonding. The technology of the invention has the advantages of simple process, high capacity of the full trap, completion by the self-alignment process, no temperature limitation and extremely high feasibility.
Description
Technical Field
The present invention relates to the field of storage processing, and in particular, to an image sensor and a method for forming the same.
Background
In back side illuminated image sensor designs, backside deep trenches are typically used to isolate individual pixels to reduce cross talk (Crosstalk) due to incoming light. The crosstalk is divided into electric crosstalk and optical crosstalk, wherein the electric crosstalk is mainly formed by forming a doped isolation layer on the side wall of the deep groove by an ion implantation method to isolate a photosensitive pixel region; optical crosstalk is mainly reduced by growing oxide or other low-refractive-index films on the side walls of the deep trenches through total reflection.
In a conventional process, a deep trench etching is usually performed on the back surface of the device layer, and then ion implantation is performed. However, since the ion implantation process generates lattice damage and malformed clusters, and some of the ions are not in place during implantation, thermal annealing is typically required to repair lattice defects and to move most of the implanted ions to the place. The temperature of the thermal annealing process is usually above 800 ℃, and the temperature is too high, which causes great damage to the front device and needs to be controlled, but this causes the problem of uneven doping, and causes adverse factors such as dark current locally generated in the deep trench.
In addition, the alignment deviation problem exists when deep trench etching is carried out on the back surface, so that the back surface isolation region and the front surface isolation region cannot be connected, and crosstalk is generated. Moreover, in the high-pixel backside illuminated sensor product, especially at 64Mbits or more, the full-well capacity of the photosensitive region is limited to a certain extent due to the small size of the pixel region and the influence of the ion implantation depth, and usually only thousands of electron capacities are available, which is not favorable for improving the maximum signal-to-noise ratio of the image sensor.
Disclosure of Invention
The invention aims to provide a method for forming an image sensor, which has simple process, high full-diameter capacity and no temperature limit. The specific scheme comprises the following steps:
the forming process of the image sensor at least comprises two bonding processes to a semiconductor substrate wafer; wherein the content of the first and second substances,
and forming a lateral PN junction and a pinning layer in the semiconductor substrate wafer before the first bonding, and forming a logic circuit region after the first bonding and before the second bonding.
Further, the method specifically comprises:
forming a first photosensitive area, a first isolation area and a pinning layer on the front surface of the semiconductor substrate wafer, wherein the lateral PN junction is formed by the first photosensitive area and the first isolation area;
carrying out first bonding on the front surface of the semiconductor substrate wafer;
forming a second photosensitive area, a second isolation area and the logic circuit area on the back of the semiconductor substrate wafer;
carrying out second bonding on the back of the semiconductor substrate wafer;
and thinning the front surface of the semiconductor substrate wafer, and finishing the subsequent process of the image sensor.
Further, the front surface of the semiconductor substrate wafer is provided with a first hard mask layer, and the method for forming the first photosensitive region and the first isolation region comprises the following steps:
etching the semiconductor substrate to form a first groove according to the first hard mask layer;
performing first epitaxy on the surface of the first groove to form a first epitaxial layer;
performing self-aligned etching on the first epitaxial layer and the semiconductor substrate to form a second groove;
performing at least one second epitaxy on the surfaces of the first epitaxial layer and the second trench to form a second epitaxial layer, wherein the first photosensitive region is formed by the second epitaxial layer, the first epitaxial layer and the semiconductor substrate;
depositing and forming an oxide layer on the surface of the second epitaxial layer;
and filling polycrystalline semiconductors on the surface of the oxide layer to form the first isolation region, wherein the polycrystalline semiconductors are suitable for being connected with different electric potentials to improve the depletion of the doped ions of the first photosensitive region.
Further, the method for forming the pinning layer comprises the following steps:
forming a second hard mask layer on the surfaces of the first photosensitive region and the first isolation region;
etching the first photosensitive area to form a third groove according to the second light resistance pattern;
and performing third epitaxy on the second hard mask layer and the surface of the third groove, and forming a pinning layer in the third groove, wherein the pinning layer is opposite to the conductivity type of the first photosensitive region.
Further, the performing a third epitaxy on the second hard mask layer and the third trench surface, the forming the pinning layer in the third trench comprising:
the third epitaxy adopts polycrystalline semiconductor materials, and polycrystalline semiconductors are grown in the third grooves to form the pinning layers;
and continuing the third epitaxy to form a third epitaxial layer, wherein the third epitaxial layer comprises a polycrystalline semiconductor layer formed on the surface of the second hard mask layer in a growing mode, and a semiconductor layer with gradually-increased doping concentration is formed on the surface of the pinning layer.
Further, the forming a second hard mask layer on the surfaces of the first photosensitive region and the first isolation region includes:
flattening the surfaces of the first photosensitive region and the first isolation region;
and depositing a medium layer on the surfaces of the first photosensitive area and the first isolation area to form the second hard mask layer.
Further, the first bonding process includes:
carrying out flattening treatment on the surface of the third epitaxial layer;
and bonding the third epitaxial layer and the first bearing wafer.
Further, the second epitaxial layer includes an intrinsic semiconductor layer and/or a fourth epitaxial layer of opposite conductivity type to the first epitaxial layer.
Further, the second epitaxy comprises:
and epitaxially growing an undoped and/or doped semiconductor on the surfaces of the first epitaxial layer and the second groove to form an intrinsic semiconductor layer and/or the fourth epitaxial layer. .
Further, after the polycrystalline semiconductor is filled, the polycrystalline semiconductor and the oxide layer on the front surface of the semiconductor substrate are removed.
Further, the doping concentration of the first epitaxy is not less than 2 x 10 16 cm -3 。
Further, the forming of the second photosensitive area, the second isolation area and the logic circuit area on the back surface of the semiconductor substrate wafer of the semiconductor substrate includes:
forming the second photosensitive area and the second isolation area on the back surface of the semiconductor substrate wafer, wherein the second photosensitive area and the second isolation area are respectively electrically communicated with the first photosensitive area and the first isolation area;
forming the logic circuit region on the second photosensitive region and the second isolation region.
Further, the second photosensitive region and/or the second isolation region are formed by ion implantation.
Further, the second bonding comprises:
forming a metal interconnection structure on the back surface of the semiconductor substrate wafer, and carrying out surface passivation;
and bonding the back surface of the semiconductor substrate wafer with a second bearing wafer.
Further, the thinning the front side of the semiconductor substrate wafer comprises:
thinning to the second hard mask layer;
carrying out chemical mechanical polishing to remove the second hard mask layer;
the subsequent process comprises the following steps:
forming a high dielectric constant material layer on the front surface of the semiconductor substrate wafer;
and sequentially arranging an isolation grid, a color filter and a micro lens on the surface of the high-dielectric-constant material layer to form the image sensor.
Further, the high dielectric constant material layer includes one or more combinations of aluminum oxide, tantalum oxide, hafnium silicon oxide, hafnium aluminum oxide, or hafnium tantalum oxide.
In addition, the invention also provides an image sensor which is formed by the image sensor forming method.
According to the scheme, through two bonding processes, the deep trench isolation region is formed on the front surface in the image sensor forming process, then the partial region of the photosensitive region is epitaxially grown in the deep trench, and the full-well capacity of the photosensitive region is improved by improving the doping concentration. In the subsequent process, the polysilicon can be controlled by the contact circuit by growing the polysilicon in the deep trench. The technology of the invention has the advantages of simple process, high capacity of the full trap, completion by the self-alignment process, no temperature limitation and extremely high feasibility.
Drawings
Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments thereof, which proceeds with reference to the accompanying drawings.
FIG. 1 is a flow chart of an image sensor formation process according to the present invention;
fig. 2 to 13 are schematic structural views of an image sensor in the forming process of the present invention.
In the drawings, like or similar reference numbers indicate like or similar devices (modules) or steps throughout the different views.
Detailed Description
The invention provides a method for forming an image sensor, which is mainly applied to a manufacturing process of a back-illuminated image sensor. Through the mode of two times of bonding, a deep groove isolation region is firstly formed on the front surface in the image sensor forming process, then a partial region of a photosensitive region is epitaxially grown in the deep groove, and the full-well capacity of the photosensitive region is improved by improving the doping concentration.
Specifically, in one embodiment of the present invention, an image sensor forming method includes: the forming process of the image sensor at least comprises two bonding processes of a semiconductor substrate wafer; and forming a lateral PN junction and a pinning layer in the semiconductor substrate wafer before the first bonding, and forming a logic circuit region after the first bonding and before the second bonding.
In the conventional image sensor forming process, only one bonding operation is often performed, and in the application, a two-time bonding mode is adopted. In a specific embodiment, as shown in fig. 1, the method comprises the steps of:
step S100: forming a first photosensitive region 110, a first isolation region 120 and a pinning layer 130 on the front surface of the semiconductor substrate 100 wafer, wherein the first photosensitive region 110 and the first isolation region 120 form the lateral PN junction;
step S200: carrying out first bonding on the front surface of the semiconductor substrate 100 wafer;
step S300: forming a second photosensitive area 210, a second isolation area 220 and the logic circuit area 230 on the wafer back side of the semiconductor substrate 100;
step S400: carrying out second bonding on the back of the semiconductor substrate 100 wafer;
step S500: and thinning the front surface of the semiconductor substrate 100 wafer, and finishing the subsequent process of the image sensor.
In step S100, a semiconductor substrate 100 is provided, and a first photosensitive region 110, a first isolation region 120, and a pinning layer 130 are formed on the front surface. Specifically, in a preferred embodiment, the front surface of the semiconductor substrate 100 wafer has a first hard mask layer 140, and the method for forming the first photosensitive region 110 and the first isolation region 120 includes:
step S111: etching the semiconductor substrate 100 to form a first trench 111 according to the first hard mask layer 140, as shown in fig. 2;
step S112: performing a first epitaxy on the surface of the first trench 111 to form a first epitaxial layer 112, as shown in fig. 3;
preferably, in a general scheme, the semiconductor substrate 100 may select a P-type semiconductor, and the first external delay grows an N-type semiconductor to form a photosensitive region later. In practical implementation, the doping concentration of the first epitaxy is preferably not less than 2 × 10 16 cm -3 I.e. using high concentration epitaxy.
Step S113: performing self-aligned etching on the first epitaxial layer 112 and the semiconductor substrate 100 to form a second trench 113, as shown in fig. 4;
the second trench 113 continues to extend downward on the basis of the first trench 111, and as shown in the figure, since the first hard mask layer 140 still remains, this etching can be formed in a self-aligned manner without using a photolithography pattern. The second trench 113 forms a stepped bottom trench on the basis of the first trench 111.
Step S114: performing at least one second epitaxy on the surfaces of the first epitaxial layer 112 and the second trench 113 to form a second epitaxial layer 114, where the first photosensitive region 110 is formed by the second epitaxial layer 114, the first epitaxial layer 112, and the semiconductor substrate 100;
in a preferred embodiment, the second epitaxial layer 114 includes an intrinsic semiconductor layer 115 and/or a fourth epitaxial layer 116 of opposite conductivity type to the first epitaxial layer. Optionally, when forming the second epitaxial layer 114, an undoped and/or doped semiconductor may be epitaxially grown on the surfaces of the first epitaxial layer 112 and the second trench 113 to form an intrinsic semiconductor layer 115 and/or the fourth epitaxial layer 116, as shown in fig. 5.
Step S115: depositing an oxide layer 121 on the surface of the second epitaxial layer; the oxide layer 121 serves to electrically isolate the polycrystalline semiconductor 122 to be filled later, and serves as a total reflection layer to form an optical isolation of the first photosensitive region 110.
Step S116: the first isolation region 120 is formed by filling a polycrystalline semiconductor 122, such as polysilicon, on the surface of the oxide layer 121, as shown in fig. 6, the polycrystalline semiconductor is adapted to access different potentials to induce charges at the interface between the deep trench and the semiconductor, thereby reducing dark current and thermal noise, and improving the depletion of the dopant ions in the first photosensitive region.
Preferably, after the filling of the polycrystalline semiconductor 122, the polycrystalline semiconductor and the oxide layer on the front surface of the semiconductor substrate 100 may be removed for the subsequent steps.
Further, in an alternative embodiment, the pinning layer 130 may be formed in step S100 by adopting the following scheme:
step S121: forming a second hard mask layer 131 on the surfaces of the first photosensitive region 110 and the first isolation region 120;
specifically, after the first isolation region 120 is formed in step S116, the surfaces of the first photosensitive region 110 and the first isolation region 120 may be planarized, and the excess polycrystalline semiconductor and the first hard mask layer 140 may be removed to form a plane. Then, a dielectric layer is deposited on the surfaces of the first photosensitive region 110 and the first isolation region 120 to form the second hard mask layer 131. Then, etching the first photosensitive region 110 to form a third trench 132 according to the second photoresist pattern defined by the second hard mask layer 131, as shown in fig. 7;
step S122: a third epitaxy is performed on the second hard mask layer 131 and the third trench surface 132, and the pinning layer 130 is formed in the third trench 132, the pinning layer 130 being opposite in conductivity type to the first photosensitive region 110. That is, if the first photosensitive region 110 is predominantly N-type doped, the pinning layer 130 selects P-type doping, and vice versa.
Specifically, in an alternative embodiment, the third epitaxy in step S122 uses a polycrystalline semiconductor material, and a polycrystalline semiconductor is grown in the third trench 132 to form the pinning layer 130; and continuing the third epitaxy to form a third epitaxial layer 133, wherein the third epitaxial layer 133 comprises a polycrystalline semiconductor layer grown on the surface of the second hard mask layer 131, and a semiconductor layer with gradually increased doping concentration is formed on the surface of the pinning layer. In the process of epitaxially growing a polycrystalline semiconductor, a polycrystalline semiconductor material grows on the oxide interface, and a single crystal semiconductor material grows on the single crystal semiconductor interface. After a certain thickness, the epitaxial growth parameters are adjusted so that the grown materials are all polycrystalline semiconductor layers and the doping concentration is gradually increased to enhance the impurity adsorption capability, and in general, the doping concentration of the regions farther away from the photosensitive region can be made higher, as shown in fig. 8.
In step S200, a first bonding is performed on the front surface of the semiconductor substrate 100 wafer. Specifically, in an alternative embodiment, after forming the third epitaxial layer 133, the first bonding process may refer to the following steps:
step S210: carrying out planarization treatment on the surface of the third epitaxial layer 133;
step S220: the third epitaxial layer 133 is bonded to the first carrier wafer 300. In bonding, a bonding oxide may be used during bonding to bond the semiconductor substrate 100 to the first carrier wafer 300, as shown in fig. 9, and held together for flipping to perform the other side operation.
After the first bonding process is completed, a subsequent process is performed on the wafer back surface of the semiconductor substrate 100. In step S300, a second photosensitive region 210, a second isolation region 220 and the logic circuit region 230 are formed on the back surface of the semiconductor substrate 100.
Specifically, forming the second photosensitive region 210, the second isolation region 220 and the logic circuit region 230 may be performed according to the following steps:
step S310: forming the second photosensitive region 210 and the second isolation region 220 on the back side of the semiconductor substrate wafer 100, which are respectively in electrical communication with the first photosensitive region 110 and the first isolation region 120; in a preferred embodiment, the second photosensitive region 210 and/or the second isolation region 220 may be formed by ion implantation.
The second photosensitive region 210 and the second isolation region 220 may be designed in a stereoscopic pixel form according to actual needs, as shown in fig. 10.
Step S320: the logic circuit region 230 is formed on the second photosensitive region 210 and the second isolation region 220. The logic circuit area 230 is used for arranging the electronic devices.
Thereafter, a second bonding process is performed in step S400, as shown in fig. 11. Preferably, the second bonding comprises the steps of:
step S410: forming a metal interconnection structure on the back surface of the semiconductor substrate 100 wafer, and performing surface passivation;
step S420: the back side of the semiconductor substrate wafer 100 is bonded to a second carrier wafer 400.
Between the first bonding and the second bonding, a device layer is mainly formed on the back surface of the semiconductor substrate 100, and after the second photosensitive region 210, the second isolation region 220 and the logic circuit layer 230 are formed, the back surface of the semiconductor substrate 100 may be bonded to the second carrier wafer 400 through a bonding oxide so as to thin the front surface of the semiconductor substrate 100.
On the basis of this, in step S500, the front surface of the semiconductor substrate 100 is thinned, and the first carrier wafer 300, and in a preferred embodiment, a material such as a bonding oxide, are removed. Specifically, in a preferred embodiment, after step S420, the thinning the front side of the semiconductor substrate 100 wafer includes the following steps:
step S511: thinning to the second hard mask layer 131; selective etching or the like may be used in this step until the second hard mask layer 131 is exposed.
Step S512: performing chemical mechanical polishing to remove the second hard mask layer 131; the pinning layer 130 and the first isolation region 120 are exposed, and at least the polysilicon material in the first isolation region 120 is exposed, as shown in FIG. 12. Compared with step S511, the polishing method without selectivity in step S512 may be selected.
Further, in step S500, in a preferred embodiment, the subsequent process further includes:
step S521: forming a high dielectric constant material layer 150 on the front surface of the semiconductor substrate 100 wafer; preferably, the high dielectric constant material layer comprises one or more combinations of aluminum oxide, tantalum oxide, hafnium silicon oxide, hafnium aluminum oxide, or hafnium tantalum oxide.
Step S522: an isolation grid 160, a color filter 170 and a micro lens 180 are sequentially arranged on the surface of the high-k material 150, as shown in fig. 13, and finally an image sensor is formed. Preferably, the isolation grid 160 may correspond to the polysilicon position in the first isolation region 120, and is divided to form the pixel array. The color filter 170 and the micro lens 180 can be designed according to the actual image sensor function and application requirements.
Based on the foregoing embodiments, in the present invention, through two bonding processes, a deep trench isolation region is formed on the front surface of the image sensor, and then a partial region of a photosensitive region is epitaxially grown in the deep trench, so as to increase the full well capacity of the photosensitive region by increasing the doping concentration. In the subsequent process, the polysilicon can be controlled by the contact circuit by growing the polysilicon in the deep trench. The technology of the invention has the advantages of simple process, high capacity of the filled well, completion by the self-alignment process and no temperature limitation, so the feasibility is extremely high.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. Furthermore, it will be obvious that the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. Several elements recited in the apparatus claims may also be implemented by one element. The terms first, second, etc. are used to denote names, but not any particular order.
Claims (17)
1. An image sensor forming method is characterized in that,
the forming process of the image sensor at least comprises two bonding processes to a semiconductor substrate wafer; wherein, the first and the second end of the pipe are connected with each other,
and forming a lateral PN junction and a pinning layer in the semiconductor substrate wafer before the first bonding, and forming a logic circuit region after the first bonding and before the second bonding.
2. The method of forming an image sensor of claim 1, the method comprising in particular:
forming a first photosensitive area, a first isolation area and a pinning layer on the front surface of the semiconductor substrate wafer, wherein the lateral PN junction is formed by the first photosensitive area and the first isolation area;
carrying out first bonding on the front surface of the semiconductor substrate wafer;
forming a second photosensitive area, a second isolation area and the logic circuit area on the back surface of the semiconductor substrate wafer;
carrying out second bonding on the back of the semiconductor substrate wafer;
and thinning the front surface of the semiconductor substrate wafer, and finishing the subsequent process of the image sensor.
3. The method for forming an image sensor as claimed in claim 2, wherein the front surface of the semiconductor substrate wafer is provided with a first hard mask layer, and the method for forming the first photosensitive region and the first isolation region comprises:
etching the semiconductor substrate to form a first groove according to the first hard mask layer;
performing first epitaxy on the surface of the first groove to form a first epitaxial layer;
performing self-aligned etching on the first epitaxial layer and the semiconductor substrate to form a second groove;
performing at least one second epitaxy on the surfaces of the first epitaxial layer and the second trench to form a second epitaxial layer, wherein the first photosensitive region is formed by the second epitaxial layer, the first epitaxial layer and the semiconductor substrate;
depositing and forming an oxide layer on the surface of the second epitaxial layer;
and filling polycrystalline semiconductors on the surface of the oxide layer to form the first isolation region, wherein the polycrystalline semiconductors are suitable for being connected with different electric potentials to improve the depletion of the doped ions of the first photosensitive region.
4. The image sensor forming method of claim 2, wherein the pinning layer forming method comprises:
forming a second hard mask layer on the surfaces of the first photosensitive region and the first isolation region;
etching the first photosensitive area to form a third groove according to the second light resistance pattern;
and performing third epitaxy on the second hard mask layer and the surface of the third groove, and forming a pinning layer in the third groove, wherein the pinning layer is opposite to the conductivity type of the first photosensitive region.
5. The image sensor forming method of claim 4, wherein the performing a third epitaxy on the second hard mask layer and the third trench surface, the forming the pinning layer in the third trench comprises:
the third epitaxy adopts polycrystalline semiconductor materials, and polycrystalline semiconductors are grown in the third grooves to form the pinning layers;
and continuing the third epitaxy to form a third epitaxial layer, wherein the third epitaxial layer comprises a polycrystalline semiconductor layer formed on the surface of the second hard mask layer in a growing mode, and a semiconductor layer with gradually-increased doping concentration is formed on the surface of the pinning layer.
6. The method of claim 4, wherein the forming a second hard mask layer on the surfaces of the first photosensitive region and the first isolation region comprises:
flattening the surfaces of the first photosensitive region and the first isolation region;
and depositing a medium layer on the surfaces of the first photosensitive area and the first isolation area to form the second hard mask layer.
7. The image sensor forming method of claim 5, wherein the first bonding process comprises:
carrying out flattening treatment on the surface of the third epitaxial layer;
and bonding the third epitaxial layer and the first bearing wafer.
8. The image sensor forming method of claim 3, wherein the second epitaxial layer comprises an intrinsic semiconductor layer and/or a fourth epitaxial layer of opposite conductivity type to the first epitaxial layer.
9. The image sensor forming method of claim 8, wherein the second epitaxy includes:
and epitaxially growing an undoped and/or doped semiconductor on the surfaces of the first epitaxial layer and the second groove to form an intrinsic semiconductor layer and/or the fourth epitaxial layer.
10. The image sensor forming method according to claim 3, wherein after the filling of the polycrystalline semiconductor, the polycrystalline semiconductor and the oxide layer on the front surface of the semiconductor substrate are removed.
11. The image sensor forming method of claim 3, wherein the doping concentration of the first epitaxy is not less than 2 x 10 16 cm -3 。
12. The method of claim 2, wherein forming a second photosensitive region, a second isolation region, and a logic circuit region on a back side of a semiconductor substrate wafer of the semiconductor substrate comprises:
forming the second photosensitive area and the second isolation area on the back surface of the semiconductor substrate wafer, and respectively electrically communicating with the first photosensitive area and the first isolation area;
forming the logic circuit region on the second photosensitive region and the second isolation region.
13. The image sensor forming method of claim 12, wherein the second photosensitive region and/or the second isolation region is formed by ion implantation.
14. The image sensor forming method of claim 2, wherein the second bonding comprises:
forming a metal interconnection structure on the back surface of the semiconductor substrate wafer, and carrying out surface passivation;
and bonding the back surface of the semiconductor substrate wafer with a second bearing wafer.
15. The image sensor forming method of claim 4, wherein the thinning of the front side of the semiconductor substrate wafer comprises:
thinning to the second hard mask layer;
carrying out chemical mechanical polishing to remove the second hard mask layer;
the subsequent process comprises the following steps:
forming a high dielectric constant material layer on the front surface of the semiconductor substrate wafer;
and sequentially arranging an isolation grid, a color filter and a micro lens on the surface of the high-dielectric-constant material layer to form the image sensor.
16. The method of claim 15, wherein the high-k material layer comprises one or more combinations of aluminum oxide, tantalum oxide, hafnium silicon oxide, hafnium aluminum oxide, or hafnium tantalum oxide.
17. An image sensor formed by the image sensor forming method according to claims 1 to 16.
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