CN101312146A - Shallow groove isolation region forming method, shallow groove isolation region structure and film forming method - Google Patents
Shallow groove isolation region forming method, shallow groove isolation region structure and film forming method Download PDFInfo
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- CN101312146A CN101312146A CNA2007100409827A CN200710040982A CN101312146A CN 101312146 A CN101312146 A CN 101312146A CN A2007100409827 A CNA2007100409827 A CN A2007100409827A CN 200710040982 A CN200710040982 A CN 200710040982A CN 101312146 A CN101312146 A CN 101312146A
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Abstract
A shallow groove isolation area forming method includes forming a shallow groove on a semiconductor substrate, defining a parameter of an isolation layer and isolation layer distribution corresponding to the parameter, wherein the isolation layer comprises at least one compressive stress membrane layer and at least one pulling stress membrane layer, and the compressive stress membrane layer and the pulling stress membrane layer are connected at intervals, depositing the compressive stress membrane layer and the pulling stress membrane layer in the isolation layer by the distribution of the isolation layer, and covering the isolation layer on the shallow groove, thereby a shallow groove isolation area for an isolation layer which meets the product stress improving requirement. The invention additionally provides a shallow groove isolation area structure, and the shallow groove isolation area has an isolation layer which meets the product stress improving requirement. The invention further provides a membrane forming method, which can form membrane layers which meet the product stress improving requirement.
Description
Technical field
The present invention relates to the ic manufacturing technology field, particularly a kind of shallow channel isolation area formation method, shallow groove isolation region structure and rete formation method.
Background technology
In the ic manufacturing technology field, the step that forms shallow channel isolation area comprises: form shallow trench on the semiconductor-based end; Fill spacer to described shallow trench.Wherein, the step to described shallow trench filling spacer comprises: clean the semiconductor-based end that has formed described shallow trench; In described shallow trench, form pad oxide; Layer deposited isolating, described separator cover described pad oxide and fill described shallow trench.The described semiconductor-based end, obtain after forming separator and passivation layer in turn at semiconductor substrate surface.As shown in Figure 1, the structure of the shallow channel isolation area of application said method formation comprises: the semiconductor-based end 10, the separator 20 that is positioned at the intrabasement shallow trench 12 of described semiconductor and fills described shallow trench.
Along with dwindling gradually of critical dimension, stress problem is subjected to the attention of industry day by day, in the existing technology, how to reduce the stress that has in the described separator, and industry has been done certain trial.
As a kind of method that reduces shallow trench isolating side wall oxide layer stress and erosion that in the Chinese patent of disclosed notification number on March 19 in 2003, provides for CN1242466C, this method comprises the following steps: to provide substrate at least, and described substrate has first dielectric layer and covers second dielectric layer of described first dielectric layer; In described substrate, form groove; Form sidewall oxide, described sidewall oxide covers the sidewall and the bottom of described groove; Fill up described groove with dielectric material; And carry out on-site steam generation processing procedure to reoxidize described sidewall oxide, described on-site steam generation processing procedure comprises at least introduces oxygen and hydroxyl.
But this method is only in order to reducing shallow trench isolating side wall oxide layer stress, and and then reduces the erosion that successive process causes device.Yet, recently, there are some researches show that the stress that has suitable type in the device conducting channel will produce useful influence to the performance of semiconductor device.Industry is generally acknowledged, has the electron mobility that tension stress helps to strengthen nmos device in the described conducting channel; Has the hole mobility that compression helps to strengthen the PMOS device in the described conducting channel; Correspondingly, shallow trench isolation has the electron mobility that compression helps to strengthen nmos device from the side-walls oxide layer; Shallow trench isolation has the hole mobility that tension stress helps to strengthen the PMOS device from the side-walls oxide layer; Promptly along with the development of technology, merely reduce shallow trench isolating side wall oxide layer stress and can not satisfy demand of practical production, the stress of controlling in the described shallow trench isolating side wall oxide layer becomes the direction of improving device performance.
Summary of the invention
The invention provides a kind of shallow channel isolation area formation method, can form to have and satisfy the shallow channel isolation area that product stress improves the separator that requires; The invention provides a kind of shallow groove isolation region structure, described shallow channel isolation area has the separator that satisfies product stress improvement requirement; The invention provides a kind of rete formation method, can form and satisfy the rete that product stress improves requirement.
A kind of shallow channel isolation area formation method provided by the invention comprises:
On the semiconductor-based end, form shallow trench;
Determine the separator parameter;
Determine the separator distribution corresponding with described parameter, described separator comprises at least one lamination stress rete and one deck tension stress rete at least, and described compression rete and tension stress rete join at interval;
According to described separator distribution layer deposited isolating internal pressure stress rete and tension stress rete, described separator covers described shallow trench.
Alternatively, the step of determining the separator parameter comprises the target stress value of determining described separator and the operation of thickness; Alternatively, determine that the step that separator distributes comprises the operation of determining described separator branch fiducial value, the sum of products of the stress value that the thickness of each tension stress rete of sum of products of the stress value that the thickness that described separator branch fiducial value is each described compression rete has with it has with it; Alternatively, the difference of the ratio of the thickness of the absolute value of described separator branch fiducial value and described separator and described separator target stress value is less than or equal to 20MPa; Alternatively, the method for layer deposited isolating internal pressure stress rete and tension stress rete is a kind of among PECVD, HDPCVD, APCVD, LPCVD, SACVD or the HARP SACVD; Alternatively, the number of compression rete that comprises in the described separator and tension stress rete is identical or inequality.
A kind of shallow groove isolation region structure provided by the invention comprises: the semiconductor-based end, the separator that is positioned at the intrabasement shallow trench of described semiconductor and fills described shallow trench; Described separator comprises at least one lamination stress rete and one deck tension stress rete at least, and described compression rete and tension stress rete join at interval.
Alternatively, the number of compression rete that comprises in the described separator and tension stress rete is identical or inequality.
A kind of rete formation method provided by the invention comprises:
Form semiconductor substrate;
Determine the rete parameter;
Determine the rete distribution corresponding with described parameter, described rete comprises at least one lamination stressor layers and one deck tension stress layer at least, and described compressive stress layer and tension stress interlayer are every joining;
According to described distribution depositional coating internal pressure stress layer and tension stress layer, described rete covers described semiconductor substrate.
Alternatively, the step of determining the rete parameter comprises the target stress value of determining described rete and the operation of thickness; Alternatively, determine that the step that rete distributes comprises the operation of determining described rete branch fiducial value, the sum of products of the stress value that the thickness of each tension stress layer of sum of products of the stress value that the thickness that described rete branch fiducial value is each described compressive stress layer has with it has with it; Alternatively, the difference of the ratio of the thickness of the absolute value of described rete branch fiducial value and described rete and described rete target stress value is less than or equal to 20MPa; Alternatively, the method for depositional coating internal pressure stress layer and tension stress layer is a kind of among PECVD, HDPCVD, APCVD, LPCVD, SACVD or the HARP SACVD; Alternatively, the number of compressive stress layer that comprises in the described rete and tension stress layer is identical or inequality.
Compared with prior art, the present invention has the following advantages:
Shallow channel isolation area formation method provided by the invention comprises the separator of different stress types rete by deposition, can form to have to satisfy the shallow channel isolation area that product stress improves the separator that requires, and then make the improvement of device performance become possibility;
Shallow groove isolation region structure provided by the invention by having the separator that comprises the different stress types rete, improves requirement and make the stress that has in the described separator satisfy product stress, and then the device that makes acquisition have the optimization performance becomes possibility;
Rete formation method provided by the invention comprises the rete of different stress types by deposition, can form to have to satisfy product stress and improve the rete that requires, and then make the improvement of device performance become possibility.
Description of drawings
Fig. 1 is the structural representation of shallow channel isolation area in the explanation prior art;
Fig. 2 is the schematic flow sheet of the formation shallow channel isolation area of the explanation embodiment of the invention;
Fig. 3 is the structural representation of the shallow channel isolation area of explanation first embodiment of the invention;
Fig. 4 is the structural representation of the shallow channel isolation area of explanation second embodiment of the invention;
Fig. 5 is the structural representation of the shallow channel isolation area of explanation third embodiment of the invention;
Fig. 6 is the structural representation of the semiconductor substrate of the explanation embodiment of the invention;
The structural representation of semiconductor substrate of Fig. 7 after for the formation rete of explanation fourth embodiment of the invention;
The structural representation of semiconductor substrate of Fig. 8 after for the formation rete of explanation fifth embodiment of the invention;
The structural representation of semiconductor substrate of Fig. 9 after for the formation rete of explanation sixth embodiment of the invention.
Embodiment
Although below with reference to accompanying drawings the present invention is described in more detail, wherein represented the preferred embodiments of the present invention, be to be understood that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensive instruction for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work for those skilled in the art with advantage of the present invention.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.Will be clearer according to following explanation and claims advantages and features of the invention.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
The step of using method formation shallow channel isolation area provided by the invention comprises: form shallow trench on the semiconductor-based end; Determine the separator parameter; Utilize described parameter to determine that separator distributes, described separator comprises at least one lamination stress rete and one deck tension stress rete at least, and described compression rete and tension stress rete join at interval; According to described separator distribution layer deposited isolating, described separator covers described shallow trench.
As shown in Figure 2, using the concrete steps that method provided by the invention forms shallow channel isolation area comprises:
Step 201: on the semiconductor-based end, form shallow trench.
The described semiconductor-based end for defined device active region and need finish shallow trench isolation from Semiconductor substrate.
The step that forms shallow trench comprises: the semiconductor-based end is provided; On the described semiconductor-based end, form passivation layer and patterned resist layer; With described patterned resist layer is mask, the described passivation layer of etching; With the described passivation layer after the etching is hard mask, the described semiconductor-based end of etched portions, forms described shallow trench.The described semiconductor-based end, have the described Semiconductor substrate of separator for the surface.
Step 202: determine the separator parameter.
There are some researches show that the stress that has suitable type in the device conducting channel will produce useful influence to the performance of semiconductor device.Industry is generally acknowledged, has the electron mobility that tension stress helps to strengthen nmos device in the described conducting channel; Has the hole mobility that compression helps to strengthen the PMOS device in the described conducting channel; Correspondingly, shallow trench isolation has the electron mobility that compression helps to strengthen nmos device from the side-walls separator; Shallow trench isolation has the hole mobility that tension stress helps to strengthen the PMOS device from the side-walls separator; The present inventor thinks that controlling described shallow trench isolation becomes the direction of improving device performance from the stress of sidewall spacers after analyzing.
Described parameter comprises the target stress value, and described target stress value is the permissible value of the device shallow channel isolation area internal stress determined according to product requirement and process conditions; Described parameter also comprises separation layer thickness, and described thickness is the permissible value of separation layer thickness in the device shallow channel isolation area of determining according to product requirement and process conditions.
Step 203: determine the separator distribution corresponding with described parameter, described separator comprises at least one lamination stress rete and one deck tension stress rete at least, and described compression rete and tension stress rete join at interval.
Described separator distributes and means each the compression rete that comprises in the described separator and the structural relation between each tension stress rete.Determine that the step that separator distributes comprises the operation of determining described separator branch fiducial value, the sum of products of the stress value that the thickness of each tension stress rete of sum of products of the stress value that the thickness that described separator branch fiducial value is each described compression rete has with it has with it.
To single compression rete, the product that defines the stress value that the thickness of described compression rete has with it is the compression fiducial value; When described separator comprised one deck compression rete, the compression fiducial value of described separator was the compression fiducial value of described compression rete; When described separator comprised two-layer at least compression rete, the compression fiducial value in the described separator was the compression fiducial value sum of each compression rete.
To single tension stress rete, the product that defines the stress value that the thickness of described tension stress rete has with it is the tension stress fiducial value; When described separator comprised one deck tension stress rete, the tension stress fiducial value of described separator was the tension stress fiducial value of described tension stress rete; When described separator comprised two-layer at least tension stress rete, the tension stress fiducial value in the described separator was the tension stress fiducial value sum of each tension stress rete.
The compression fiducial value and the tension stress fiducial value sum that define described separator are separator branch fiducial value.The difference of the ratio of the absolute value of described separator branch fiducial value and the thickness of described separator and described separator target stress value satisfies product requirement, and described product requirement detects deviation according to stress and determines that difference is less than or equal to 20MPa as described.
Thickness that described compression rete and tension stress rete have respectively and stress value can utilize the creation data storehouse to obtain.
Step 204: according to described separator distribution layer deposited isolating internal pressure stress rete and tension stress rete, described separator covers described shallow trench.
As example, when described separator comprised one deck compression rete and one deck tension stress rete, the step of using method formation shallow channel isolation area provided by the invention comprised: form shallow trench on the semiconductor-based end; The separator that deposition has first stress types, described separator covers the sidewall and the bottom of described shallow trench; The separator that deposition has second stress types, described separator covers described separator with first stress types, and fills described shallow trench.
Described stress types comprises compression and tension stress.Particularly, when described first stress types was compression, described second stress types was a tension stress; When described first stress types was tension stress, described second stress types was a compression.
Table 1 is the tables of data that corresponding above-mentioned separator distributes.
Table 1
| Coding | 1 | 2 | 3 | 4 |
| Stress in thin film value (MPa) | -140 | -80 | -45 | 25 |
| Thicknesses of layers (dust) | 5080 | 5120 | 5200 | 5250 |
| Compressive stress film ply stress value (MPa) | -200 | -200 | -200 | -200 |
| Compressive stress film layer thickness (dust) | 4060 | 3070 | 2100 | 1100 |
| Tension stress stress in thin film value (MPa) | 80 | 80 | 80 | 80 |
| Tension stress thicknesses of layers (dust) | 1020 | 2050 | 3100 | 4150 |
As shown in table 1, to be encoded to 1 data set is example, for obtain thickness be 5080 dusts, stress value be 140MPa and stress types be compression separator (be designated as-140MPa), the thickness of compression rete and stress value be respectively 4060 dusts and-200MPa, the thickness of tension stress rete and stress value are respectively 1020 dusts and 80MPa.Corresponding certain thickness rete has the distribution of the rete of different stress types by change, can obtain different stress in thin film values.
The present inventor thinks that the relative position relation of described compression rete and tension stress rete should be not restricted.Promptly as shown in Figure 3, in the shallow trench 120 in the semiconductor-based end 100, at first deposit compression rete 140, described compression rete 140 covers the sidewall and the bottom of described shallow trench 120; Then deposit tension stress rete 160, described tension stress rete 160 covers described compression rete 140, and fills described shallow trench 120; Perhaps, as shown in Figure 4, in the shallow trench 220 in the semiconductor-based end 200, at first deposit tension stress rete 260, described tension stress rete 260 covers the sidewall and the bottom of described shallow trench 220; Then deposit compression rete 240, described compression rete 240 covers described tension stress rete 260, and fills described shallow trench 220; The method of the formation shallow channel isolation area that relates to all is included among the protection range that the present invention requires.
In addition, the number of compression rete that comprises in the described separator and tension stress rete can be identical or inequality.As example, in the shallow trench 320 in the semiconductor-based end 300, the number of the described compression rete 340 that comprises in it is 2, the number of described tension stress rete 360 be 1 described separator structure as shown in Figure 5.By adopting at least three layers overlapped way, the STRESS VARIATION of described shallow channel isolation area is tending towards evenly, the device performance after the improvement is stablized.
The present inventor also thinks, the generation type of described compression rete and tension stress rete should be not restricted, utilize common process, as the rete with compression or tension stress that utilizes technologies such as PECVD, HDPCVD, APCVD, LPCVD, SACVD or HARP SACVD to form all can be used for the enforcement of the inventive method.
As embodiments of the invention, the process conditions of using HDPCVD formation compression rete can comprise: described deposit reacting gas is silane (SiH
4) and oxygen (O
2), the top flux scope of described silane is 20～40 cc/min (sccm), as 25,30 or 35sccm; The lateral flow weight range of described silane is 50～150sccm, as 70,90,110 or 130sccm; The range of flow of described oxygen is 150～200sccm, as 175sccm; Deposited gas also comprises helium (He) and hydrogen (H
2), the range of flow of described helium is 200～400sccm, as 250,300 or 350sccm; The range of flow of described hydrogen is 100～150sccm, as 125sccm; In the deposit course of reaction, required top plasma dissociation power (TOP SRF) scope is 6000～8000 watts (W), as 6500,7000 or 7500W; Required lateral plasma body power (SIDE SRF) scope of dissociating is 6000～8000 watts (W), as 6500,7000 or 7500W; Required plasma-deposited power (BRF) scope is 2500～4000W, as 3000 or 3500W;
Described sputter reacting gas is Nitrogen trifluoride (NF
3), the range of flow of described Nitrogen trifluoride is 100～300sccm, as 150,200 or 250sccm; Sputter gas also comprises helium (He) and hydrogen (H
2), the range of flow of described helium is 80～150sccm, as 90,110 or 130sccm; The range of flow of described hydrogen is 100～300sccm, as 150,200 or 250sccm; In the sputter course of reaction, required top plasma dissociation power (TOP SRF) scope is 1000～3000 watts (W), as 1500,2000 or 2500W; Required lateral plasma body power (SIDE SRF) scope of dissociating is 5000～7000 watts (W), as 5500,6000 or 6500W; Required plasma sputter power (BRF) scope is 1000～1500W, as 1200 or 1300W.
The process conditions of using HDPCVD formation tension stress rete can comprise: described deposit reacting gas is silane (SiH
4) and oxygen (O
2), the top flux scope of described silane is 5～10 cc/min (sccm), as 7 or 9sccm; The lateral flow weight range of described silane is 25～40sccm, as 30 or 35sccm; The range of flow of described oxygen is 40～60sccm, as 50sccm; Deposited gas also comprises helium (He) and hydrogen (H
2), the range of flow of described helium is 200～400sccm, as 250,300 or 350sccm; The range of flow of described hydrogen is 100～150sccm, as 125sccm; The top flux scope of described hydrogen is 40～60sccm, as 50sccm; In the deposit course of reaction, required top plasma dissociation power (TOP SRF) scope is 3000～4000 watts (W), as 3500W; Required lateral plasma body power (SIDE SRF) scope of dissociating is 3000～4000 watts (W), as 3500W; Required plasma-deposited power (BRF) scope is 1000～2500W, as 2000W; Helium pressure is 6～10 millimetress of mercury (torr) in the described interior air ring, as 8torr; Helium pressure is 8～12 millimetress of mercury (torr) in the described outer air ring, as 10torr;
Described sputter reacting gas is Nitrogen trifluoride (NF
3), the range of flow of described Nitrogen trifluoride is 150～250sccm, as 200sccm; Sputter gas also comprises helium (He) and oxygen (O
2), the range of flow of described helium is 100～200sccm, as 150sccm; The range of flow of described oxygen is 200～300sccm, as 250sccm; In the sputter course of reaction, required top plasma dissociation power (TOP SRF) scope is 4000～5000 watts (W), as 4500W; Required lateral plasma body power (SIDE SRF) scope of dissociating is 800～1500 watts (W), as 1000 or 1200W; Required plasma sputter power (BRF) scope is 1000～2500W, as 1500 or 2000W.
Separator by only utilizing HDP board deposition to have different stress types can shorten the turnaround time between board, enhances productivity.
The present invention also provides a kind of shallow groove isolation region structure, comprising: the semiconductor-based end, the separator that is positioned at the intrabasement shallow trench of described semiconductor and fills described shallow trench; Especially, described separator comprises at least one lamination stress rete and one deck tension stress rete at least, and described compression rete and tension stress rete join at interval.
Described separator has parameter, and described parameter comprises the target stress value, and described target stress value is the permissible value of the device shallow channel isolation area internal stress determined according to product requirement and process conditions; Described parameter also comprises separation layer thickness, and described thickness is the permissible value of separation layer thickness in the device shallow channel isolation area of determining according to product requirement and process conditions.
To single compression rete, the product that defines the stress value that the thickness of described compression rete has with it is the compression fiducial value; When described separator comprised one deck compression rete, the compression fiducial value of described separator was the compression fiducial value of described compression rete; When described separator comprised two-layer at least compression rete, the compression fiducial value in the described separator was the compression fiducial value sum of each compression rete.
To single tension stress rete, the product that defines the stress value that the thickness of described tension stress rete has with it is the tension stress fiducial value; When described separator comprised one deck tension stress rete, the tension stress fiducial value of described separator was the tension stress fiducial value of described tension stress rete; When described separator comprised two-layer at least tension stress rete, the tension stress fiducial value in the described separator was the tension stress fiducial value sum of each tension stress rete.The compression fiducial value and the tension stress fiducial value sum that define described separator are separator branch fiducial value.The difference of the ratio of the absolute value of described separator branch fiducial value and the thickness of described separator and described separator target stress value satisfies product requirement, and described product requirement detects deviation according to stress and determines that difference is less than or equal to 20MPa as described.
Thickness that described compression rete and tension stress rete have respectively and stress value can utilize the creation data storehouse to obtain.
The present inventor thinks that the relative position relation of described compression rete and tension stress rete should be not restricted.That is, at first form the compression rete, described compression rete covers the sidewall and the bottom of described shallow trench; Then form the tension stress rete, described tension stress rete covers described compression rete; Perhaps, at first form the tension stress rete, described tension stress rete covers the sidewall and the bottom of described shallow trench; Then form the compression rete, described compression rete covers described tension stress rete; The shallow channel isolation area that relates to all is included among the protection range that the present invention requires.
In addition, the number of compression rete that comprises in the described separator and tension stress rete can be identical or inequality.As example, the number of the described compression rete that comprises in it is 2, and the number of described tension stress rete can be 1.By adopting at least three layers overlapped way, the STRESS VARIATION of described shallow channel isolation area is tending towards evenly, the device performance after the improvement is stablized.
In addition; control to device conducting channel internal stress also can realize by the stress that control stops in the layer; the rete that describedly stop that layer means after device forms, extraneous interconnection line covers described device before forming; described stop layer both protection device do not stain, can be used as the subsequent interconnect line again and form etching stop layer in the processing procedure.
Control to device conducting channel internal stress also can realize that described before-metal medium layer means first interlayer dielectric layer that covered described device before extraneous interconnection line forms by the stress in the control before-metal medium layer.
The present invention also provides a kind of rete formation method, and the step that using said method forms rete comprises: form semiconductor substrate; Determine the rete parameter; Determine the rete distribution corresponding with described parameter, described rete comprises at least one lamination stressor layers and one deck tension stress layer at least, and described compressive stress layer and tension stress interlayer are every joining; With described distribution depositional coating internal pressure stress layer and tension stress layer, described rete covers described semiconductor substrate.
Described rete comprises separator in the shallow trench, stops layer and before-metal medium layer etc.When stopping the control of the stress realization device conducting channel internal stress in the layer by control, as shown in Figure 6, described semiconductor substrate 400 can by go up the definition device active region in Semiconductor substrate 410 (substrate) and finish shallow trench isolation from, form after forming grid structure and source region and drain region then; When realizing the control of device conducting channel internal stress by the stress in the control before-metal medium layer, described semiconductor substrate can by go up the definition device active region in Semiconductor substrate (substrate) and finish shallow trench isolation from, then form grid structure and source region and drain region after, and then form and stop layer back and form.Described grid structure comprises the side wall 430 and the gate oxide 420 of grid 440, all around gate.
Described parameter comprises the target stress value, and described target stress value is the permissible value of the stress in thin film determined according to product requirement and process conditions; Described parameter also comprises thickness, and described thickness is the permissible value of the thicknesses of layers determined according to product requirement and process conditions.
Described rete distributes and means each compressive stress layer that comprises in the described rete and the structural relation between each tension stress layer.Determine that the step that rete distributes comprises the operation of determining described rete branch fiducial value, the sum of products of the stress value that the thickness of each tension stress layer of sum of products of the stress value that the thickness that described rete branch fiducial value is each described compressive stress layer has with it has with it.
Defining the thickness of described rete and the product of target stress value is the rete fiducial value; To single compressive stress layer, the product that defines the stress value that the thickness of described compressive stress layer has with it is the compression fiducial value; When described rete comprised one deck compressive stress layer, the compression fiducial value of described rete was the compression fiducial value of described compressive stress layer; When described rete comprised two-layer at least compressive stress layer, the compression fiducial value in the described rete was the compression fiducial value sum of each compressive stress layer.
To single tension stress layer, the product that defines the stress value that the thickness of described tension stress layer has with it is the tension stress fiducial value; When described rete comprised one deck tension stress layer, the tension stress fiducial value of described rete was the tension stress fiducial value of described tension stress layer; When described rete comprised two-layer at least tension stress layer, the tension stress fiducial value in the described rete was the tension stress fiducial value sum of each tension stress layer.
The compression fiducial value and the tension stress fiducial value sum that define in the described rete are rete branch fiducial value.The difference of the ratio of the absolute value of described rete branch fiducial value and the thickness of described rete and described rete target stress value satisfies product requirement, and described product requirement detects deviation according to stress and determines that difference is less than or equal to 20MPa as described.
Thickness that described compressive stress layer and tension stress layer have respectively and stress value can utilize the creation data storehouse to obtain.
As example, when described rete comprised one deck compressive stress layer and one deck tension stress layer, the step of using method formation shallow channel isolation area provided by the invention comprised: form semiconductor substrate; The rete that deposition has first stress types, described rete covers described semiconductor substrate; The rete that deposition has second stress types, described rete covers described rete with first stress types.
Described stress types comprises compression and tension stress.When described first stress types was compression, described second stress types was a tension stress; When described first stress types was tension stress, described second stress types was a compression.
Corresponding certain thickness rete has the distribution of the rete of different stress types by change, can obtain different stress in thin film values.
The present inventor thinks that the relative position relation of described compressive stress layer and tension stress layer should be not restricted.Realize that with the stress that stops by control in the layer embodiment of device conducting channel internal stress is an example, that is, as shown in Figure 7, on semiconductor substrate 400, at first deposit compressive stress layer 460, described compressive stress layer 460 covers described semiconductor substrate; Then deposit tension stress layer 480, described tension stress layer 480 covers described compressive stress layer 460; Perhaps, as shown in Figure 8, at first deposit tension stress layer 480, described tension stress layer 480 covers described semiconductor substrate; Then deposit compressive stress layer 460, described compressive stress layer 460 covers described tension stress layer 480; The method of the formation shallow channel isolation area that relates to all is included among the protection range that the present invention requires.
In addition, the number of described compressive stress layer that comprises in the described rete and described tension stress layer can be identical or inequality.As example, as shown in Figure 9, on semiconductor substrate, the number of the described compressive stress layer 660 that comprises in the described rete is 2 o'clock, and the number of described tension stress layer 680 can be 1.By adopting at least three layers overlapped way, the STRESS VARIATION of described rete is tending towards evenly, the device performance after the improvement is stablized.
The present inventor also thinks, the generation type of described compressive stress layer and tension stress layer should be not restricted, utilize common process, as the rete with compression or tension stress that utilizes technologies such as PECVD, HDPCVD, APCVD, LPCVD, SACVD or HARP SACVD to form all can be used for the enforcement of the inventive method.
As embodiments of the invention, the process conditions of using HDPCVD formation compressive stress layer can comprise: described deposit reacting gas is silane (SiH
4) and oxygen (O
2), the top flux scope of described silane is 20～40 cc/min (sccm), as 25,30 or 35sccm; The lateral flow weight range of described silane is 50～150sccm, as 70,90,110 or 130sccm; The range of flow of described oxygen is 150～200sccm, as 175sccm; Deposited gas also comprises helium (He) and hydrogen (H
2), the range of flow of described helium is 200～400sccm, as 250,300 or 350sccm; The range of flow of described hydrogen is 100～150sccm, as 125sccm; In the deposit course of reaction, required top plasma dissociation power (TOP SRF) scope is 6000～8000 watts (W), as 6500,7000 or 7500W; Required lateral plasma body power (SIDE SRF) scope of dissociating is 6000～8000 watts (W), as 6500,7000 or 7500W; Required plasma-deposited power (BRF) scope is 2500～4000W, as 3000 or 3500W;
Described sputter reacting gas is Nitrogen trifluoride (NF
3), the range of flow of described Nitrogen trifluoride is 100～300sccm, as 150,200 or 250sccm; Sputter gas also comprises helium (He) and hydrogen (H
2), the range of flow of described helium is 80～150sccm, as 90,110 or 130sccm; The range of flow of described hydrogen is 100～300sccm, as 150,200 or 250sccm; In the sputter course of reaction, required top plasma dissociation power (TOP SRF) scope is 1000～3000 watts (W), as 1500,2000 or 2500W; Required lateral plasma body power (SIDESRF) scope of dissociating is 5000～7000 watts (W), as 5500,6000 or 6500W; Required plasma sputter power (BRF) scope is 1000～1500W, as 1200 or 1300W.
The process conditions of using HDPCVD formation tension stress layer can comprise: described deposit reacting gas is silane (SiH
4) and oxygen (O
2), the top flux scope of described silane is 5～10 cc/min (sccm), as 7 or 9sccm; The lateral flow weight range of described silane is 25～40sccm, as 30 or 35sccm; The range of flow of described oxygen is 40～60sccm, as 50sccm; Deposited gas also comprises helium (He) and hydrogen (H
2), the range of flow of described helium is 200～400sccm, as 250,300 or 350sccm; The range of flow of described hydrogen is 100～150sccm, as 125sccm; The top flux scope of described hydrogen is 40～60sccm, as 50sccm; In the deposit course of reaction, required top plasma dissociation power (TOP SRF) scope is 3000～4000 watts (W), as 3500W; Required lateral plasma body power (SIDE SRF) scope of dissociating is 3000～4000 watts (W), as 3500W; Required plasma-deposited power (BRF) scope is 1000～2500W, as 2000W; Helium pressure is 6～10 millimetress of mercury (torr) in the described interior air ring, as 8torr; Helium pressure is 8～12 millimetress of mercury (torr) in the described outer air ring, as 10torr;
Described sputter reacting gas is Nitrogen trifluoride (NF
3), the range of flow of described Nitrogen trifluoride is 150～250sccm, as 200sccm; Sputter gas also comprises helium (He) and oxygen (O
2), the range of flow of described helium is 100～200sccm, as 150sccm; The range of flow of described oxygen is 200～300sccm, as 250sccm; In the sputter course of reaction, required top plasma dissociation power (TOP SRF) scope is 4000～5000 watts (W), as 4500W; Required lateral plasma body power (SIDE SRF) scope of dissociating is 800～1500 watts (W), as 1000 or 1200W; Required plasma sputter power (BRF) scope is 1000～2500W, as 1500 or 2000W.
Rete by only utilizing HDP board deposition to have different stress types can shorten the turnaround time between board, enhances productivity.
Although the present invention has been described and has enough described embodiment in detail although describe by the embodiment at this, the applicant does not wish by any way the scope of claims is limited on this details.Other to those skilled in the art advantage and improvement are conspicuous.Therefore, relative broad range the invention is not restricted to represent and the specific detail of describing, equipment and the method and the illustrative example of expression.Therefore, can depart from these details and do not break away from the spirit and scope of the total inventive concept of applicant.
Claims (14)
1. a shallow channel isolation area formation method is characterized in that, comprising:
On the semiconductor-based end, form shallow trench;
Determine the separator parameter;
Determine the separator distribution corresponding with described parameter, described separator comprises at least one lamination stress rete and one deck tension stress rete at least, and described compression rete and tension stress rete join at interval;
According to described separator distribution layer deposited isolating internal pressure stress rete and tension stress rete, described separator covers described shallow trench.
2. shallow channel isolation area formation method according to claim 1 is characterized in that: the step of determining the separator parameter comprises the target stress value of definite described separator and the operation of thickness.
3. shallow channel isolation area formation method according to claim 1 and 2, it is characterized in that: determine that the step that separator distributes comprises the operation of determining described separator branch fiducial value, the sum of products of the stress value that the thickness of each tension stress rete of sum of products of the stress value that the thickness that described separator branch fiducial value is each described compression rete has with it has with it.
4. shallow channel isolation area formation method according to claim 3 is characterized in that: the ratio of the absolute value of described separator branch fiducial value and the thickness of described separator and the difference of described separator target stress value are less than or equal to 20MPa.
5. shallow channel isolation area formation method according to claim 1 is characterized in that: the method for layer deposited isolating internal pressure stress rete and tension stress rete is a kind of among PECVD, HDPCVD, APCVD, LPCVD, SACVD or the HARP SACVD.
6. shallow channel isolation area formation method according to claim 1 is characterized in that: the compression rete that comprises in the described separator is identical or inequality with the number of tension stress rete.
7. a shallow groove isolation region structure comprises: the semiconductor-based end, the separator that is positioned at the intrabasement shallow trench of described semiconductor and fills described shallow trench; It is characterized in that: described separator comprises at least one lamination stress rete and one deck tension stress rete at least, and described compression rete and tension stress rete join at interval.
8. shallow groove isolation region structure according to claim 7 is characterized in that: the compression rete that comprises in the described separator is identical or inequality with the number of tension stress rete.
9. a rete formation method is characterized in that, comprising:
Form semiconductor substrate;
Determine the rete parameter;
Determine the rete distribution corresponding with described parameter, described rete comprises at least one lamination stressor layers and one deck tension stress layer at least, and described compressive stress layer and tension stress interlayer are every joining;
According to described distribution depositional coating internal pressure stress layer and tension stress layer, described rete covers described semiconductor substrate.
10. rete formation method according to claim 9 is characterized in that: the step of determining the rete parameter comprises the target stress value of definite described rete and the operation of thickness.
11. according to claim 9 or 10 described rete formation methods, it is characterized in that: determine that the step that rete distributes comprises the operation of determining described rete branch fiducial value, the sum of products of the stress value that the thickness of each tension stress layer of sum of products of the stress value that the thickness that described rete branch fiducial value is each described compressive stress layer has with it has with it.
12. rete formation method according to claim 11 is characterized in that: the ratio of the absolute value of described rete branch fiducial value and the thickness of described rete and the difference of described rete target stress value are less than or equal to 20MPa.
13. rete formation method according to claim 9 is characterized in that: the method for depositional coating internal pressure stress layer and tension stress layer is a kind of among PECVD, HDPCVD, APCVD, LPCVD, SACVD or the HARP SACVD.
14. rete formation method according to claim 9 is characterized in that: the number of compressive stress layer that comprises in the described rete and tension stress layer is identical or inequality.
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| CN2007100409827A CN101312146B (en) | 2007-05-21 | 2007-05-21 | Shallow groove isolation region forming method, shallow groove isolation region structure and film forming method |
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| CN2007100409827A CN101312146B (en) | 2007-05-21 | 2007-05-21 | Shallow groove isolation region forming method, shallow groove isolation region structure and film forming method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104716083A (en) * | 2015-03-20 | 2015-06-17 | 上海华力微电子有限公司 | Method for forming shallow-trench isolation |
| CN117153855A (en) * | 2023-10-30 | 2023-12-01 | 合肥晶合集成电路股份有限公司 | Semiconductor structure of back-illuminated image sensor and manufacturing method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5528081A (en) * | 1993-06-25 | 1996-06-18 | Hall; John H. | High temperature refractory metal contact in silicon integrated circuits |
| US6297128B1 (en) * | 1999-01-29 | 2001-10-02 | Vantis Corporation | Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress |
| US6368931B1 (en) * | 2000-03-27 | 2002-04-09 | Intel Corporation | Thin tensile layers in shallow trench isolation and method of making same |
-
2007
- 2007-05-21 CN CN2007100409827A patent/CN101312146B/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104716083A (en) * | 2015-03-20 | 2015-06-17 | 上海华力微电子有限公司 | Method for forming shallow-trench isolation |
| CN104716083B (en) * | 2015-03-20 | 2018-06-26 | 上海华力集成电路制造有限公司 | The method for forming shallow-trench isolation |
| CN117153855A (en) * | 2023-10-30 | 2023-12-01 | 合肥晶合集成电路股份有限公司 | Semiconductor structure of back-illuminated image sensor and manufacturing method thereof |
| CN117153855B (en) * | 2023-10-30 | 2024-03-01 | 合肥晶合集成电路股份有限公司 | Semiconductor structure of back-illuminated image sensor and manufacturing method thereof |
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| CN101312146B (en) | 2011-07-13 |
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