CN115764545A - VCSEL chip manufacturing method and VCSEL array - Google Patents

VCSEL chip manufacturing method and VCSEL array Download PDF

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Publication number
CN115764545A
CN115764545A CN202210992271.4A CN202210992271A CN115764545A CN 115764545 A CN115764545 A CN 115764545A CN 202210992271 A CN202210992271 A CN 202210992271A CN 115764545 A CN115764545 A CN 115764545A
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vcsel
vcsel chip
stress
manufacturing
layer
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李加伟
严磊
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Suzhou Changrui Photoelectric Co ltd
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Suzhou Changrui Photoelectric Co ltd
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Abstract

The invention discloses a VCSEL chip manufacturing method, and belongs to the technical field of semiconductor laser manufacturing. The manufacturing method of the VCSEL chip comprises the following steps: a step of forming a plurality of active region mesas having an oxide-confined structure on the epitaxial wafer, the method further comprising: and depositing a stress compensation layer with tensile stress at the bottom of the trench between the formed active region platforms. The invention also discloses a VCSEL array. Aiming at the problem of warping caused by the compressive stress of the laminated DBR in the process of manufacturing the VCSEL chip, the manufacturing process improves the existing manufacturing process, and after the oxidation-limited active region platform is manufactured, a stress compensation layer with tensile stress is deposited at the bottom of the groove between the active region platforms to offset the compressive stress generated by the laminated DBR, so that the warping generated in the subsequent process of the VCSEL chip can be effectively reduced, and the product breakage rate is greatly reduced.

Description

VCSEL chip manufacturing method and VCSEL array
Technical Field
The invention relates to the technical field of semiconductor Laser manufacturing, in particular to a method for manufacturing a Vertical-Cavity Surface-Emitting Laser (VCSEL) chip.
Background
The Vertical Cavity Surface Emitting Laser (VCSEL) is an ideal light source for short-distance optical communication, and has the advantages of low power consumption, small threshold current, high modulation speed, high light beam quality, compact chip structure and low manufacturing cost. In addition, VCSEL lasersThe method is widely applied to the technical fields of posture perception, medical technology, 3D sensors, optical storage and the like. The VCSEL laser has the advantages of thin active region, short cavity length and small single-layer gain, and the effective photon life can be greatly prolonged by adopting a stacked multi-layer DBR structure. In order to improve the convergence of current injected into the active layer of the quantum well, the conventional VCSEL laser mostly adopts a wet oxidation process to mix one or more layers of Al with high aluminum content in the DBR thereof x Ga 1-x Oxidizing As (x is more than or equal to 0.95) layer into AlO x The DBR high aluminum layer directly above the quantum well active layer is not oxidized to form an oxidized hole, so that an annular circular current channel is obtained, which is called an oxidation-limited DBR structure (or simply referred to as an oxidation-limited structure), and the folded current channel can effectively reduce the threshold current of the VCSEL laser. Meanwhile, because the DBR high aluminum layer material at the oxide hole is not oxidized, gaAs/Al is kept x Ga 1-x The As is unchanged, the refractive index is kept between 3 and 3.11, and the oxidized DBR high aluminum layer material around the oxidation hole is made of Al x Ga 1-x As becomes AlO x The refractive index is reduced from 3.11 to 1.6, so that the difference of the refractive indexes of the DBR materials can greatly limit the light emitted by the active layer to the vertical direction, the photon life of the laser is prolonged, and the threshold current of the VCSEL laser is further reduced.
The VCSEL laser mostly adopts a laminated DBR which is composed of a high-refractive-index GaAs layer with the thickness of 1/4 lambda (lambda is the light-emitting wavelength of the laser) and a low-refractive-index Al layer with the thickness of 1/4 lambda x Ga 1-x As (x is more than or equal to 0.8 and less than or equal to 0.95) layers are alternately laminated, and the laminated DBR is formed by growing on the surface of the GaAs substrate. Al (Al) x Ga 1-x The use of the As layer increases the compressive stress of the epitaxial wafer, and the more the aluminum content in the stacked DBR, the greater the compressive stress of the epitaxial wafer. The epitaxial wafer becomes warped under excessive compressive stress, and the whole wafer is in a dome-like bent state, so that the wafer is difficult to handle in chip manufacturing process engineering (GaAs is brittle and fragile). Meanwhile, in order to facilitate the cutting of the VCSEL laser and the heat dissipation of the chip, the GaAs substrate needs to be thinned after the wafer-level chip is manufactured, and the thickness of the thinned wafer is 60-350 um. The warping of the chip is further intensified after the GaAs substrate is thinned, and the GaAs substrateThe higher the degree of bottom thinning, the more severe the chip warpage. After the GaAs substrate is thinned to 80-150um, the warp curvature radius of the 6-inch wafer chip can reach several hundred cm. Such large warpage is very easy to cause fragment damage, and severely restricts the dicing treatment of wafer level chips. In addition, when wafer-level chips are diced into larger scale VCSEL arrays for use, the presence of compressive stress and warpage can also severely impact the performance and reliability of the VCSEL array.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a VCSEL chip manufacturing method which can effectively solve the problems of large warping amount and easiness in damage of an epitaxial wafer caused by actions such as thinning in the chip manufacturing process.
The invention specifically adopts the following technical scheme to solve the technical problems:
a VCSEL chip fabrication method, comprising: a step of forming a plurality of active region mesas having an oxide-confined structure on the epitaxial wafer, the method further comprising: and depositing a stress compensation layer with tensile stress at the bottom of the trench between the formed active region platforms.
Preferably, the tensile stress has a stress value of 300 MPa to 800 MPa.
Preferably, the stress compensation layer is one or a composite of at least two of the following materials: siN x 、SiO x 、SiON、Si。
Preferably, the thickness of the stress compensation layer is 500nm to 3000 nm.
Further, the manufacturing method further includes: depositing a metal heat conducting layer over the stress compensation layer.
Preferably, the metal heat conduction layer is one or a composite of at least two of the following metal materials: mo, al, ti.
Preferably, the thickness of the metal heat conduction layer is 100 nm-1000 nm.
Still further, the manufacturing method further includes: and coating a water and oxygen barrier film on the surface of the epitaxial wafer.
Preferably, the water oxygen barrier filmIs one or at least two of the following materials: siN x 、SiO x 、SiON、AlO x 、TiO x 。
A VCSEL array is manufactured by using the manufacturing method of the VCSEL chip of any one of the technical schemes.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
aiming at the problem of warping caused by the compressive stress of the laminated DBR in the process of manufacturing the VCSEL chip, the manufacturing process improves the existing manufacturing process, and after the oxidation limiting type active region platform is manufactured, a stress compensation layer with tensile stress is deposited at the bottom of a groove between the active region platforms so as to offset the compressive stress generated by the laminated DBR, thereby effectively reducing the warping generated in the subsequent process of the VCSEL chip and greatly reducing the product breakage rate.
Drawings
FIG. 1 is a schematic diagram of a vertical cross-section of a prior art VCSEL chip;
FIG. 2 is a schematic diagram of a longitudinal cross-sectional structure of a preferred embodiment of a VCSEL chip of the present invention;
fig. 3a to 3n are schematic diagrams illustrating a manufacturing process of the VCSEL chip shown in fig. 2.
The meanings of the reference symbols in the figures are in particular as follows:
1. a GaAs substrate; 2. a buffer layer; 3. an N-type DBR;4. a quantum well; 5. an oxidation limiting layer; 6. a P-type DBR;7. a water oxygen barrier film; 8. p Ring Metal;9. p Metal;10. a Mesa groove; 11. n Metal;12. a stress compensation layer; 13. a metal heat conducting layer.
Detailed Description
Fig. 1 shows the basic structure of a prior VCSEL chip, from bottom to top: n Metal 11, gaAs substrate 1, buffer layer 2, N-type DBR 3, quantum well 4, oxidation limiting layer 5, P-type DBR 6, water-oxygen barrier film 7, P Ring Metal 8 and P Metal 9; the chip comprises a plurality of VCSEL units which independently emit light, wherein each VCSEL unit consists of an upper protruding active region platform (comprising a plurality of upper N-type DBRs and quantum wells 4, oxidation limiting layers 5 and P-type DBRs 6 which are generally called Mesa or Mesa platform in engineering) and an lower N Metal 11, a GaAs substrate 1, a plurality of lower light-emitting VCSEL units and a plurality of light-emitting semiconductor layers,The buffer layer 2 and a part of the N-type DBR 3 are separated by a Mesa 10. The VCSEL units of the VCSEL chip are divided as required, and then an individual VCSEL laser or VCSEL array can be obtained. Due to Al in the stacked DBR x Ga 1-x The compressive stress generated by the As layer can cause a great deal of warpage in the subsequent process (especially thinning process), and further cause chipping.
Aiming at the problem, the invention aims to improve the existing manufacturing process, and after the oxidation-limited active region platform is manufactured, a stress compensation layer with tensile stress is deposited at the bottom of a groove between the active region platforms so as to offset the compressive stress generated by the laminated DBR, thereby effectively reducing the warpage generated by a VCSEL chip in the subsequent process and greatly reducing the product breakage rate.
The technical scheme provided by the invention is as follows;
a VCSEL chip fabrication method, comprising: a step of forming a plurality of active region mesas having an oxide-confined structure on the epitaxial wafer, the method further comprising: and depositing a stress compensation layer with tensile stress at the bottom of the trench between the formed active region platforms.
Preferably, the tensile stress has a stress value of 300 MPa to 800 MPa.
Preferably, the stress compensation layer is one or a composite of at least two of the following materials: siN x 、SiO x 、SiON、Si。
Preferably, the thickness of the stress compensation layer is 500nm to 3000 nm.
Further, the manufacturing method further includes: depositing a metal heat conducting layer over the stress compensation layer.
Preferably, the metal heat conduction layer is one or a composite of at least two of the following metal materials: mo, al, ti.
Preferably, the thickness of the metal heat conduction layer is 100 nm-1000 nm.
Still further, the manufacturing method further includes: and coating a water and oxygen barrier film on the surface of the epitaxial wafer.
Preferably, the water and oxygen barrier film is one or a composite of at least two of the following materials: siN x 、SiO x 、SiON、AlO x 、TiO x 。
For the public understanding, the technical scheme of the invention is explained in detail by a specific embodiment and the accompanying drawings:
after the oxidation-limited active region platforms are manufactured, a stress compensation layer 12 with tensile stress is deposited at the bottom of a Mesa groove 10 between the active region platforms to offset the compressive stress generated by a stacked DBR, a metal heat conduction layer 13 is further deposited on the stress compensation layer 12 to conduct out Joule heat generated in the working process of the chip, the problem of reduction of the performance and reliability of the chip caused by temperature rise in the using process of the chip is effectively solved, and the finally obtained VCSEL chip is shown in FIG. 2.
The manufacturing process of the VCSEL chip is as follows:
step 1, coating photoresist on the surface of the epitaxial wafer shown in FIG. 3a, wherein the thickness of the photoresist is 5-15um; exposing and developing the photoresist to obtain a P-Mesa mask as shown in FIG. 3 b;
step 2, etching the epitaxial wafer obtained in the step 1 by adopting an ICP (inductively coupled plasma) dry etching process, wherein the etching gas is Cl 2 /BCl 3 Or Cl 2 /SiCl 4 Etching down to the lower layer 1-10 pairs of P-DBR of the quantum well layer to expose the high aluminum layer to be oxidized, as shown in FIG. 3 c; removing the photoresist to obtain P-Mesa, as shown in FIG. 3 d;
step 3, adopting a wet oxidation process to oxidize Al with high aluminum content in the P-Mesa x Ga 1-x The Al in the As layer oxidizes, resulting in P-Mesa with an oxidation-limited structure, as shown in FIG. 3 e;
step 4, depositing a stress compensation layer on the surface of the epitaxial wafer obtained in the step 3 by adopting a PECVD (plasma enhanced chemical vapor deposition) process, wherein the stress compensation layer has tensile stress, the stress value is 300 Mpa-800 Mpa, the material of the film layer can be SiNx, siOx, siON, si and the like, the film layer can be a single layer or a lamination of the film materials, and the film thickness is 500-3000 nm; after the completion, the epitaxial wafer shown in fig. 3f is obtained;
step 5, photoetching is carried out on the epitaxial wafer on which the stress compensation layer deposition is finished in the step 4, only the region in the P-Mesa groove is reserved with photoresist, and the rest part of the epitaxial wafer is not covered with the photoresist; etching the stress compensation layer of the area without the photoresist coverage by adopting a dry etching process, wherein the etching gas is CF4+ Ar; then removing the photoresist to obtain an epitaxial wafer with a stress compensation layer covered on the region in the P-Mesa groove, as shown in FIG. 3 g;
step 6, depositing a metal heat conduction layer on the surface of the epitaxial wafer obtained in the step 5 by adopting a Sputter process or an E-Gun process, wherein the film layer is made of materials which are easy to etch and have excellent heat conduction performance, such as Mo, al, ti or Ti/Al/Ti and the like, the film layer can be a single layer or a lamination of the film materials, and the film thickness is 100-1000 nm; photoetching the epitaxial wafer, only keeping the area in the P-Mesa groove with photoresist, and leaving the rest part of the epitaxial wafer without photoresist coverage; etching the metal heat conduction layer of the region without the photoresist coverage by adopting a dry etching process, wherein the etching gas of Mo is CF 4 + Ar, al, ti/Al/Ti etching gas is Cl 2 +BCl 3 + Ar; finally, removing the photoresist to obtain an epitaxial wafer with the P-Mesa groove inner region covering stress compensation layer and the metal heat conduction layer, as shown in fig. 3 h;
step 7, plating a water and oxygen barrier film on the surface of the epitaxial wafer obtained in the step 6, wherein the film plating process is PECVD or ALD, the film layers are SiNx, siOx, siON, alOx, tiOx and the like, the film layers can be single layers or stacked layers of the film materials, the film thickness is 20-1000nm, and the WVTR (moisture vapor barrier capacity) is 5E -2 ~1E -4 Oxygen barrier OTR of 5E 0 ~1E -1 The completed epitaxial wafer is shown in fig. 3 i;
step 8, etching the epitaxial wafer finished in the step 7 with metal Via holes, wherein the etching gas is CF 4 + Ar or BOE, resulting in an epitaxial wafer with Via holes, see fig. 3j;
step 9, filling Via holes with the epitaxial wafer deposition metal obtained in the step 8, wherein the metal is Au, pt, ag, al and the like, and is shown in figure 3k;
and step 10, plating the epitaxial wafer obtained in the step 9 with a P-Metal material of Au, wherein the thickness of the film is 1-5 um. The top of the light outlet hole is not provided with a P-Metal, and the area outside the light outlet hole completely covers the P-Metal, as shown in figure 3l;
step 11, thinning the GaAs substrate side on the back surface of the epitaxial wafer obtained in the step 10, wherein the overall thickness of the thinned epitaxial wafer is 70-150 um, which is shown in fig. 3m;
and step 12, plating N-Metal on the GaAs substrate side on the back surface of the thinned epitaxial wafer obtained in step 11, wherein the N-Metal is Ti/Au, and the thickness of the N-Metal is 1-5 um, as shown in FIG. 3N.
The VCSEL units of the VCSEL chip are divided as required, and then an individual VCSEL laser or VCSEL array can be obtained.

Claims (10)

1. A VCSEL chip fabrication method, comprising: a step of forming a plurality of active region mesas having an oxide-confined structure on the epitaxial wafer, wherein the method further comprises: and depositing a stress compensation layer with tensile stress at the bottom of the trench between the formed active region platforms.
2. The method of fabricating the VCSEL chip of claim 1, wherein the tensile stress has a stress value of 300 Mpa to 800 Mpa.
3. The VCSEL chip fabrication method of claim 1, wherein the stress compensation layer is one or a composite of at least two of the following materials: siN x 、SiO x 、SiON、Si。
4. The method of claim 1 wherein the stress compensation layer has a thickness of 500nm to 3000 nm.
5. The VCSEL chip fabrication method of claim 1, further comprising: depositing a metal heat conducting layer over the stress compensation layer.
6. The method for fabricating the VCSEL chip of claim 5, wherein the metal heat conduction layer is one of the following metal materials or a composite of at least two of the following metal materials: mo, al, ti.
7. The method for fabricating the VCSEL chip of claim 5, wherein the thickness of the metal heat conducting layer is 100 nm-1000 nm.
8. The VCSEL chip manufacturing method of any of claims 1 to 7, wherein the manufacturing method further comprises: and coating a water and oxygen barrier film on the surface of the epitaxial wafer.
9. The VCSEL chip fabrication method of claim 8, wherein the water oxygen barrier film is one or a combination of at least two of the following materials: siN x 、SiO x 、SiON、AlO x 、TiO x 。
10. A VCSEL array fabricated using the VCSEL chip fabrication method of any one of claims 1 to 9.
CN202210992271.4A 2022-08-18 2022-08-18 VCSEL chip manufacturing method and VCSEL array Pending CN115764545A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117153855A (en) * 2023-10-30 2023-12-01 合肥晶合集成电路股份有限公司 Semiconductor structure of back-illuminated image sensor and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117153855A (en) * 2023-10-30 2023-12-01 合肥晶合集成电路股份有限公司 Semiconductor structure of back-illuminated image sensor and manufacturing method thereof
CN117153855B (en) * 2023-10-30 2024-03-01 合肥晶合集成电路股份有限公司 Semiconductor structure of back-illuminated image sensor and manufacturing method thereof

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