JP2006066681A - Vertical resonance type high output surface-emitting laser - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simulate and validate constitutional conditions of a surface-emitting laser device, where the number of semiconductor multilayer film layers, the number of quantum well layers, the relative value in gain peaks of a reflector and a quantum well at room temperature or the like can be improved in output. <P>SOLUTION: A vertical resonance type surface emitting laser comprises a laminate structure having a pair of distribution Bragg-reflection-type semiconductor multilayer film reflectors provided on and under an active layer which is formed on a semiconductor substrate for emitting laser light from the side of an n-type multilayer film reflector 104. A p-type multilayer film reflector 108 comprises 39 or more pairs of p-type AlGaAs with different composition alternately laminated, the n-type multilayer film reflector 104 comprises n-type AlGaAs with different composition alternately laminated, and the number of laminates is smaller than the number of laminates of the reflector 108. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a vertical resonator type high output surface emitting semiconductor laser that emits laser light in a direction perpendicular to a substrate surface.

  A surface emitting laser is a semiconductor laser that emits light in a direction perpendicular to a substrate surface, and includes a vertical resonator type and a horizontal resonator type. The most common structure of a vertical cavity surface emitting laser is a pair of distributed Bragg reflection semiconductor multilayer mirrors (hereinafter referred to as “DBR mirrors”) on a semiconductor substrate above and below an active layer. A structure in which a current is injected from an electrode formed outside the DBR mirror via the DBR mirror is well known.

  Vertical cavity surface emitting semiconductor lasers (hereinafter referred to as “surface emitting lasers”) can be fabricated without cleaving at the end face, can be formed into a two-dimensional array, can be easily circularized, etc. It has been attracting attention because it has features not found in semiconductor lasers.

  On the other hand, in an optical information processing or optical communication system device, in order to realize high-density and high-speed parallel signal processing, a functional light that integrates optical elements in a direction perpendicular to the substrate and a surface-type light-emitting element capable of surface connection Achieve by configuring the element.

High power operation of a surface light emitting device is required for surface connection and optical operation of an integrated light source. In surface-emitting devices, research and development of conventional surface-emitting semiconductor lasers have been actively conducted. In the following Patent Document 1, an n-type DBR mirror in which 35 pairs of n-GaAs / n-Al _0.9 Ga _0.1 As are stacked, p-Al _0.2 Ga _0.8 As / p-Al _0. A surface emitting laser device including a p-type DBR mirror in which 25 pairs of ₉ Ga _0.1 As are stacked is disclosed.

JP 2004-055912 A

  The surface-emitting laser device disclosed in Patent Document 1 does not achieve a sufficiently high output operation because the number of stacked n-type DBR mirrors and p-type DBR mirrors is insufficient, and the conversion efficiency is not sufficient. . Thus, no clear design policy for higher output has been proposed.

  In the surface emitting laser device, the present invention simulates the configuration conditions that can increase the output such as the number of layers of the semiconductor multilayer film, the number of quantum well layers, and the relative value of the gain peak of the reflector and the quantum well at room temperature. The purpose is to demonstrate this.

As a result of intensive studies, the present inventors have found the following optimum conditions in the vertical cavity type high-power surface emitting laser device and have reached the present invention. That is, first, the present invention is an invention of a vertical-cavity high-power surface-emitting laser device in which a laminated structure in which a pair of distributed Bragg reflector type semiconductor multilayer reflectors are arranged above and below an active layer is formed on a semiconductor substrate. is there.
(1) In a vertical cavity surface emitting laser that extracts laser light from the n-type multilayer mirror side, 39 pairs or more of p-type multilayer reflectors of p-type AlGaAs having different compositions are stacked alternately, and n-type multilayer N-type AlGaAs layers having different compositions are alternately stacked on the film reflector, and the number of stacked layers is smaller than the number of stacked p-type multilayer mirrors.
(2) The vertical cavity type high output surface emitting laser according to (1), wherein the number of stacked p-type multilayer reflectors is 48 pairs or less.
(3) The vertical cavity type high-power surface emitting laser according to (1) or (2) above, wherein the n-type multilayer mirror is laminated in 28 to 30 pairs.
(4) In a vertical cavity surface emitting laser that takes out laser light from the p-type multilayer reflector side, 39 pairs or more of n-type AlGaAs reflectors alternately laminated with different compositions of n-type AlGaAs, and p-type multilayer P-type AlGaAs having a different composition is alternately laminated on the film reflector, and the number of laminated layers is smaller than the number of layers of the n-type multilayer reflector.
(5) The vertical cavity type high-power surface emitting laser according to (4), wherein the number of stacked n-type multilayer reflectors is 48 pairs or less.
(6) The vertical-cavity high-power surface emitting laser according to (4) or (5) above, wherein the number of stacked p-type multilayer reflectors is 28 to 30.
(7) The band offset of the active layer is 9 to 15 nm. Here, the band offset is the difference between the peak wavelength of the active gain at room temperature and the stop band wavelength of the resonator.
(8) The vertical cavity type high-power surface emitting laser according to any one of (1) to (6), wherein the active layer has a band offset of 9 to 15 nm.
(9) The vertical cavity type high output surface emitting laser according to any one of (1) to (8), wherein the active layer is a quantum well layer having 2 to 4 layers.
With the configurations (1) to (9), the output and the conversion efficiency can be increased.
Second, the present invention is an invention of a high-power surface-emitting laser device array, wherein the vertical cavity surface-emitting laser according to any one of the above (1) to (9) is two-dimensionally arranged to form an array. And a cooling device is brought into contact with the non-outgoing side of the array, and a condensing optical system is arranged on the outgoing side of the array.

  Here, it is preferable that the condensing optical system includes each light emitting laser microlens and a total light emitting laser condensing lens.

  According to the present invention, in the surface emitting laser device, the configuration conditions that can increase the output such as the number of layers of the semiconductor multilayer film, the number of layers of the quantum well, and the relative value of the gain peak of the reflector and the quantum well at room temperature are optimized. I was able to. The surface emitting laser device of the present invention has high output and high efficiency, and can be applied to various uses such as light sources for optical communication and copying machines.

  FIG. 1 shows the configuration of a surface emitting laser device according to the present invention. Here, the laser light is extracted from the N-type DBR mirror 104 side. The antireflection film 101 is made of silicon nitride or the like. The upper electrode 102 is made of AuGe / PtAu or the like. The substrate 103 is made of N-type GaAs or the like. The N-type DBR mirror 104 can be formed by alternately stacking N-type AlGaAs having different compositions. The number of stacked N-type DBR mirrors 104 needs to be smaller than the number of stacked P-type DBR mirrors 108 described below. 30 pairs are optimal. The resonator 105 is made of AlGaAs / GaAs or the like. The active layer quantum well 106 is composed of GaAs / InGaAs or the like, and optimally has a band offset of 9 to 15 nm with 2 to 4 layers. The resonator 107 is made of AlGaAs / GaAs or the like. The P-type DBR mirror 108 can be formed by alternately stacking P-type AlGaAs having different compositions, and 39 to 48 pairs are optimal. The insulating film 109 is made of SiN or the like. The lower electrode 110 is made of Ti / Pt / Au or the like.

In FIG. 1, the laser beam is extracted from the N-type DBR mirror side. However, in the present invention, the laser beam may be extracted from the P-type DBR mirror side. In that case, the optimum number of stacked layers of the N-type DBR mirror and the P-type DBR mirror is switched.
Hereinafter, the requirements (1) to (9) will be sequentially described by taking as an example a structure in which laser light is extracted from the N-type DBR mirror side.

[Optimum design of P-DBR mirror]
If the number of P-DBR mirrors is increased, the following phenomenon is considered to occur.
1. The reflectivity increases, the threshold decreases, and the maximum output and efficiency increases.
2. The extraction efficiency is increased, and the maximum output and efficiency are improved.
3. Thermal resistance increases, heat generation increases, maximum output and efficiency decreases.
4). Series electrical resistance increases, heat generation increases, maximum output and efficiency decreases.

  Thus, since 1, 2 and 3, 4 produce conflicting results, the number of P-DBR mirrors may not be increased or decreased too much. That is, there are optimum values for obtaining maximum output and maximum efficiency.

  FIG. 2 shows a graph in which the number of P-DBR mirrors is changed, the maximum output, the maximum efficiency, and the output at the maximum efficiency are plotted. In the graph, the solid line Pmax indicates the calculated maximum output power, the broken line WP indicates the power-light conversion efficiency, and the broken line P (@ Wallplug = max) indicates the light output when the power-light conversion efficiency is maximum. . The number of N-DBR mirrors is 28 pairs, the band offset is 12 nm, and the number of quantum wells is fixed at 3 layers.

  The lasers prototyped so far were an N-DBR 28 pair, a P-DBR 30 pair, a quantum well 3 layer, a band offset 12 nm, and a power-light conversion efficiency 14% (actual measurement value). From FIG. 2, it is expected that the efficiency can be improved to 42% by increasing the number of P-DBR mirrors to 45 pairs. Because this calculation has an effect that is not taken into account, the actual efficiency is expected to be less than 40%. It can also be seen that the optical output when the conversion efficiency is maximized hardly changes even if the number of P-DBRs is changed. After all, the optimum value of the number of P-DBR pairs is 39 to 48 pairs, and it can be seen that the maximum output is 39 pairs and the maximum efficiency is 45 pairs.

[Optimum design of N-DBR mirror]
It is considered that the following phenomenon occurs when the number of N-DBR mirrors is increased.
1. The reflectivity increases, the threshold decreases, and the maximum output and efficiency increases.
2. The extraction efficiency decreases, and the maximum output and efficiency decreases.
3. Series electrical resistance increases, heat generation increases, maximum output and efficiency decreases.

  Thus, since 1 and 2 and 3 produce conflicting results, the number of N-DBR mirrors may not be increased or decreased too much. That is, there are optimum values for obtaining maximum output and maximum efficiency.

FIG. 3 shows a graph in which the number of N-DBR mirrors is changed and the maximum output, the maximum efficiency, and the output at the maximum efficiency are plotted. In the graph, the solid line Pmax indicates the calculated value of the maximum output, the broken line WP indicates the power-light conversion efficiency, and the broken line P (@ Wallplug = max) indicates the light output when the power-light conversion efficiency is maximum. is there. The number of P-DBR mirrors is 39 pairs, the band offset is 12 nm, and the number of quantum wells is fixed at 3 layers.
FIG. 3 shows that the optimum value of the number of N-DBR pairs is 28 to 30 pairs.

[Optimum design of band offset]
The difference between the peak wavelength of the gain at room temperature and the wavelength of the stop band of the DBR mirror is called a band offset. Here, according to the convention, the case where the stop band of the DBR mirror is longer than the gain peak wavelength is positive. The increase in band offset is considered to produce the following effects.
1. 1. Increase oscillation threshold Increase in maximum output From 1 and 2, if the band offset is increased too much, the threshold current value becomes too large and the maximum output may decrease.

  FIG. 4 shows a graph in which the band offset is changed and the maximum output, the maximum efficiency, and the output at the maximum efficiency are plotted. In the graph, the solid line Pmax indicates the calculated value of the maximum output, the broken line WP indicates the power-light conversion efficiency, and the broken line P (@ Wallplug = max) indicates the light output when the power-light conversion efficiency is maximum. is there. The number of P-DBR mirrors is fixed to 40 pairs, the number of N-DBR mirrors is 29 pairs, and the number of quantum wells is fixed to 3 layers.

  Increasing the band offset increases the maximum output. On the other hand, the efficiency decreases as the band offset increases, but the efficiency rapidly decreases after 15 nm. From the viewpoint of efficiency, the band offset is considered to be best at 6 to 12 nm. After all, it can be seen that the optimum value of the band offset is 9 to 15 nm.

[Optimum design of the number of quantum wells]
An increase in the number of quantum wells is thought to produce the following effects.
1. The threshold current density increases and the threshold current value increases.
2. The confinement factor decreases and the threshold current value increases.
3. The gain increases and the threshold current value decreases.

  Surface-emitting lasers have a very thin active region due to the structure and low gain. Although it is desired to secure the number of active layers necessary for oscillation, if there are too many active layers, the threshold current value increases, which is disadvantageous for high output. Ensuring the minimum number of active layers is considered to produce the maximum output and maximum efficiency.

  FIG. 5 shows a graph in which the number of quantum wells is changed and the maximum output, the maximum efficiency, and the output at the maximum efficiency are plotted. In the graph, the solid line Pmax indicates the calculated value of the maximum output, the broken line WP indicates the power-light conversion efficiency, and the broken line P (@ Wallplug = max) indicates the light output when the power-light conversion efficiency is maximum. is there. The number of P-DBR mirrors is fixed at 40 pairs, the number of N-DBR mirrors is 29 pairs, and the band offset is fixed at 12 nm.

  From the results of FIG. 5, it is understood that the gain is insufficient in one quantum well layer, and that the best efficiency can be obtained when the quantum well has two layers. After all, it can be seen that the optimum number of quantum wells is 2-4.

[Optimized surface emitting laser layer structure]
As a result, the layer structure capable of realizing the maximum output is different from the layer structure capable of realizing the maximum efficiency. Further, the output at the maximum efficiency does not change greatly even if the maximum output increases. Considering the actual application situation, it is better to optimize the efficiency with the emphasis on efficiency because the cooling device does not take extra size and cost.

As a result of designing to optimize the efficiency of the surface emitting laser, the following was found in the structure in which the laser light is extracted from the N-type DBR mirror side.
N-DBR: 28 to 30 pairs P-DBR: 39 to 48 pairs [maximum output when 39 pairs, maximum efficiency when 45 pairs]
Band offset: 9-15nm
Number of quantum wells: 2-4

Since the surface emitting laser emits laser light perpendicular to the substrate, it is easy to produce a large number of lasers on the wafer and array them. While attempts have been made to produce a high-power laser array using this, it is also essential to increase the output of a single element. Hereinafter, fabrication of a surface emitting laser single element will be described. The manufactured surface emitting laser was designed as follows.
N-DBR: 28 pairs P-DBR: 40 pairs Band offset: 12 nm
Number of quantum wells: 3

  The back emission type surface emitting laser has a cooling efficiency improved by bonding the substrate surface side having a light emitting layer to a heat sink, and has a structure suitable for high output. However, since the laser beam is extracted from the back surface of the substrate, the manufacturing process is different from that of the front emission type. In addition, when the devices are arrayed, the manufacturing process requires high uniformity and reproducibility. In this example, the manufacturing process of the back-emitting type surface emitting laser is summarized.

[Outline of manufacturing procedure]
A manufacturing process of the back emission type surface emitting laser having the cross-sectional structure shown in FIG. 6 will be described. The manufacturing process is generally as shown in FIG. Since an epitaxial wafer for a surface emitting laser has a resonator structure already formed in an epitaxial layer as will be described later, an electrode formation is a main process in the wafer processing process. First, a mesa is formed by etching. Thereafter, lateral oxidation is performed to form a current confinement structure. Next, after covering the surface with an insulating film, an electrode in contact with the p-layer on the surface is formed. After polishing the back surface of the substrate and depositing an antireflection film on the laser beam emitting portion, an n-side electrode is formed. Below, the layer structure of an epitaxial wafer and the detail of each process are demonstrated.

[Layer structure of epitaxial wafer]
FIG. 8 shows a cross-sectional structure of an epitaxial wafer for a back emission type surface emitting laser that is currently used. A light emitting layer having an optical thickness corresponding to one wavelength of the light emission wavelength and a pair of plane mirrors sandwiching the light emitting layer are formed of semiconductors having different conductivity types. The light emitting layer uses In _0.2 Ga _0.8 As as a well layer and GaAs _0.92 P _0.08 as a barrier layer. It consists of three quantum wells and an AlGaAs spacer layer. The reflecting mirror is a distributed Bragg reflector (DBR) in which Al _0.9 Ga _0.1 As and Al _0.12 Ga _0.88 As are stacked. In order to reduce the resistance of the DBR, a composition gradient layer is inserted at the interface between layers having different compositions. Further, in order to form a current confinement structure by lateral oxidation, an Al _0.98 Ga _0.02 As layer is inserted above the light emitting layer.

  FIG. 9 shows a REM (reflection electron microscope image) photograph of the wafer cross section. Since the photographed wafer has a front emission type structure, the material of the light emitting layer and the number of DBR layers are different from those of the back emission type, but the same thing is observed even in the case of the back emission type. You may think. It can be observed that the portion showing the periodic contrast is DBR, and the light emitting layer is formed between them.

[Deposition of surface protective film]
SiO ₂ is deposited on the surface of the epitaxial wafer by sputtering. Al _0.98 Ga _0.02 As and Al _0.9 Ga _0.1 As constituting the epi-wafer are easily oxidized in the atmosphere and unstable, and thus easily deteriorate. Normally, the epitaxial surface is terminated with a GaAs cap layer, but when surface defects such as pits are present, there is a high possibility that oxidation will proceed inside. Further, the SiO ₂ deposited here serves as a mask material in the next mesa etching process and also serves as a surface protective film in the oxidation process. In addition, in the lateral oxidation process, the presence of SiO ₂ facilitates observation of the oxidized region with an infrared microscope. That is, it has been found that the contrast between the oxidized region and the non-oxidized region can be increased.

[Mesa etching]
FIG. 10 shows a process chart from mesa etching to lateral oxidation. First, a resist is patterned by photolithography. Next, SiO ₂ is etched with buffered hydrofluoric acid. Using the resist and SiO ₂ as a mask, anisotropic etching is performed by RIE using ICP (Inductive Coupled Plasma) to form a mesa shape. In this step, a vibration waveform corresponding to the etching depth can be observed by irradiating the etching surface with laser light and monitoring the reflected light intensity. Since the number of vibration periods corresponds to the number of etched DBR pairs, the etching depth can be estimated from the vibration waveform.

  After the etching is completed, the resist is stripped using a stripping solution. However, since the resist is cured by heat during etching, it is difficult to remove the resist with the stripping solution alone. At present, the resist is removed by rubbing the surface with a cotton swab or the like.

[Lateral oxidation]
In the oxidation step, the Al _0.98 Ga _0.02 As layer provided on the light emitting layer is oxidized in the lateral direction from the mesa side wall portion, thereby concentrating the current on the remaining mesa central portion. As a result, a high current density is achieved with a low drive current, and an inversion distribution required for laser oscillation can be obtained with a low current. This process is particularly important for an element having a small light emitting portion. Without such a current confinement structure, there is a problem that the contact resistance increases because the electrode becomes small in a small element, but avoiding the problem that the contact resistance increases by forming such a current confinement structure inside. However, a high current density can be obtained.

The oxidation was performed according to the following procedure. First, the natural oxide film is removed with ammonia water. Next, it was placed in an oxidation furnace and oxidation was performed with the temperature profile shown in FIG. Nitrogen containing water vapor is introduced into the oxidation furnace. The target lateral oxidation distance was 15 μm. The results of observation with an infrared microscope after oxidation are shown in FIG. The oxidized part looks whitish compared to the non-oxidized part. In the portion near the mesa edge, a region considered to be the oxidation of the Al _0.90 Ga _0.10 As layer in the DBR can also be observed. Although it can be seen that the mesa side wall is oxidized almost isotropically, anisotropy may appear depending on the structure of the epitaxial wafer and the oxidation conditions. The oxidation rate varies depending on the size of the mesa and the thickness of Al _0.90 Ga _0.10 As. Since the patterns used in this example have various mesa sizes, the oxidation time is set so that the oxidation distance becomes the design value in the smallest mesa.

This oxidation process has the following problems. Since the oxidation rate of the Al _0.98 Ga _0.02 As layer is affected by the film thickness and strain of the Al _0.98 Ga _0.02 As, the oxidation rate is confirmed for each wafer having a different layer structure. is required. The oxidation rate in this epi structure was about 3 μm / min. When trying to obtain a surface emitting laser that oscillates in a single mode, the diameter of the light emitting portion (non-oxidized portion) must be about 2 to 3 μm. There is a risk of being. In order to solve this problem, several research institutions have reported techniques for controlling oxidation while performing in-situ observations.

[Insulating film deposition]
After the oxidation is completed, an insulating film is deposited to protect the semiconductor surface. Here, first, after depositing SiO ₂ by sputtering, to insulate the surface protection by further applying a polyimide thereon.

  As the polyimide, a negative photosensitive polyimide was used. Although the spin coating is performed to a thickness of about 3 μm, the mesa portion has a height of 5 to 6 μm, so that the polyimide coating thickness is thinner in the upper portion of the mesa than in the lower portion of the mesa. For this reason, the following problems occur when the contact hole pattern is exposed. In addition, since the mask patterns currently used have mesa patterns of various sizes on the wafer, the polyimide film thickness on the top of the mesa varies depending on the size of the mesa. ing.

[Contact hole]
The contact hole pattern is exposed to photosensitive polyimide, and a hole for electrode contact is formed on the top of the mesa. The details of the process up to the next electrode formation are shown in FIG. Although the mask design is performed with the allowable value of the alignment error between the mesa and the contact hole pattern being 2 μm, an alignment error of 1 μm or more occurs because the mesa step is large. In some cases, an error of about 2 μm may occur, and in the future, it is necessary to change the pattern rule or flatten the mesa step. As one method, a trench structure in which only the periphery of the mesa is etched can be considered.

The film thickness of the polyimide applied to the mesa side wall is thin, and the polyimide may be peeled off from the mesa by stirring the solution during development. This phenomenon is particularly noticeable for elements having a large mesa. Peeling from the side wall is a problem because SiO ₂ and AlGaAs may be etched in the next etching process using buffered hydrofluoric acid.

  After patterning, heat treatment (curing) for curing the polyimide is performed. The curing temperature was 135 ° C. for 15 minutes, 350 ° C. for 60 minutes, and 400 ° C. for 1 minute. Since the volume of polyimide is reduced by curing, tensile stress is applied by contraction of the polyimide between mesas when the coating film thickness is thick. Since this stress may cause cracks in the mesa, it is necessary to pay attention to the coating film thickness.

  Next, a contact hole is opened in SiO using polyimide as a mask. Since etching is performed using buffered hydrofluoric acid (BHF), SiO under the polyimide is also side-etched at the end of the pattern. If the over-etching time is too long, BHF wraps around the mesa side wall and side-etches the AlGaAs layer, so management of the etching time is important.

[P electrode formation]
After the contact hole is opened, Au / Zn / Au serving as a p-electrode is deposited in this order on the entire surface of the wafer. After vapor deposition, annealing is performed in nitrogen at 420 ° C. for 2 minutes. Since this electrode has poor adhesion only by vapor deposition, it should be noted that the electrode may be peeled off when a subsequent process is performed without annealing.

  Next, etching is performed leaving a necessary electrode portion. Here, the region up to 10 μm outside the end of the mesa is covered with a p-electrode. The electrode pattern is patterned by photolithography, and the excess metal portion is etched with a potassium iodide iodide solution.

[Improved electrode adhesion and thickening]
Since the above-mentioned electrode metal alone is insufficient in adhesion, the electrode metal having high adhesion is covered from the top. In addition, since the electrode portion may be broken due to a step, it is necessary to increase the thickness of the electrode. Here, thickening of the gold electrode is performed by electrolytic plating. In addition, it is expected that the heat dissipation characteristics will be improved by covering the periphery of the mesa with gold.

  First, Cr / Au is deposited on the entire surface in this order as a base metal with high adhesion. After patterning for gold plating, gold is deposited by immersing the wafer in a plating electrolyte and passing an electric current. Thereby, an electrode pad having a thickness of about 3 μm is formed. Thereafter, the resist is removed, and in order to remove the unplated portion of the underlying metal, the substrate is immersed in a potassium iodide iodide solution and etched with gold.

[Substrate polishing]
Laser light is emitted from the back surface of the substrate through the GaAs substrate. In order to minimize the absorption of the laser beam by the substrate, the substrate is polished to about 100 μm. However, since the polished surface serves as a light exit surface, it needs to be a mirror surface so that light is not scattered.

  The sample was affixed to a glass substrate with wax and polished. Polishing is performed in three stages. First, roughing is performed to about 120 μm with a copper plate and a 2 μm diamond slurry. Thereafter, the polishing disk is replaced with a cloth and similarly polished using a 2 μm diamond slurry. At this point, a mirror surface can be obtained by polishing to 100 μm. Finally, the slurry is replaced with colloidal silica to further reduce the surface roughness. A photograph of the polished surface is shown in FIG. It can be seen that a mirror surface almost equivalent to the surface side is obtained by polishing.

[Deposition of antireflection film]
On the exit surface, approximately 30% of the output is returned to the inside by Fresnel reflection due to the refractive index difference between air and GaAs. In addition to the loss of the laser, this affects the operation of the laser as return light. Therefore, it is necessary to reduce reflection by depositing an antireflection film. Here, SiN (refractive index 1.92) deposited by PCVD was used. From the reflection spectrum when this SiN is deposited on a GaAs wafer, it can be seen that the lowest reflectivity is obtained at 980 nm almost as designed.

  In the future, when it is necessary to further reduce the reflectance, there is room for adjusting the refractive index by using SiON. It is also possible to form an antireflection film with a multilayer film.

[N-electrode formation]
In forming the n-electrode and the emission window, a process by etching of the deposited metal was originally considered. However, preliminary experiments revealed that residues were observed on the SiN surface when the annealed AuGe on SiN was etched. Therefore, here, a method of forming electrodes by lift-off is employed.

  The sample has already been thinned to 100 μm by the substrate polishing process. In order to prevent breakage of the sample due to stress, it is effective to attach the glass plate or the like using wax or the like, but it is necessary to remove the wax before vapor deposition in order to prevent contamination of the vapor deposition apparatus. Since the resist is also peeled off in this step, the treatment was performed here without being attached to glass. Here, since SiN is deposited on the back surface of the substrate, the substrate strength can be reinforced.

  Since the back surface of the substrate serves as a laser beam emission surface, it is necessary to leave SiN as an antireflection film in a portion where the laser beam passes and to deposit an ohmic electrode on the n-GaAs substrate in the other portion. Since the laser light is emitted toward the back surface of the substrate from the already processed center portion of the front surface side, it is necessary to align the electrode pattern on the back surface according to the position of the mesa.

  An n-electrode resist pattern is formed in alignment with the mesa pattern on the surface. Next, SiN in the portion where the n-electrode is deposited is etched with BHF. AuGe / Au is deposited in this order and lifted off in acetone.

  After lift-off, it can function as an ohmic electrode by heating to 420 ° C. in nitrogen and performing a heat treatment for 2 minutes.

[Gold plate]
Plating patterning is performed on the basis of the n-electrode pattern. The end is mask-designed to overlap about 5 μm on SiN. Initially, in the designed process, after vapor deposition was performed on the entire surface, plating was performed with this pattern, and the window of the emission part was to be opened by etching the lower electrode. Therefore, it was made to overlap on SiN so that GaAs might not be exposed to etching liquid. In order to avoid the reaction between the plating solution and GaAs, it is desirable that the plating pattern is smaller than the underlying electrode pattern. However, since the mask pattern does not correspond to the process change, the GaAs substrate is currently exposed to the plating solution. Is in a situation. There are no problems caused by the actual device characteristics.

  An electroplating solution was used, and gold plating with a thickness of 3 μm was performed. This improves the yield of wire bonding.

[Evaluation of surface emitting laser]
FIG. 15 shows the current-light intensity characteristics of the manufactured surface emitting laser by a solid line and the current-voltage characteristics by a broken line. From FIG. 15, the surface emitting laser device according to the present invention has been optimized with respect to the number of layers of the semiconductor multilayer film, the number of layers of the quantum well, the relative value of the gain peak of the reflector and the quantum well at room temperature, etc. It has been demonstrated that high power operation is taking place.

[Arraying surface emitting lasers]
In the present invention, the above-described vertical cavity surface emitting laser is two-dimensionally arranged to form an array, and the output can be further increased. Specifically, as shown in FIG. 16, a cooling device is brought into contact with the non-emission side of the array, and a condensing optical system is arranged on the emission side of the array. Here, the condensing optical system is composed of a microlens for each light emitting laser and a condensing lens for all light emitting lasers.

  According to the present invention, high output and high efficiency of the surface emitting laser device have been achieved. This makes it possible to apply in a wide range of fields including optical communication and light sources for copying machines.

The block diagram of the surface emitting laser apparatus of this invention. The graph which plotted the output at the time of changing the number of P-DBR mirrors, the maximum output, the maximum efficiency, and the maximum efficiency. The graph which plotted the output at the time of the maximum output, the maximum efficiency, and the maximum efficiency by changing the number of N-DBR mirrors. A graph plotting the maximum output, maximum efficiency, and output at maximum efficiency while changing the band offset. A graph plotting the maximum output, maximum efficiency, and output at maximum efficiency by changing the number of quantum wells. Cross-sectional structure of a back emission type surface emitting laser. Manufacturing process of back-emitting surface emitting laser. 3 is an example of a layer structure of a wafer for a back emission type surface emitting laser. The REM (reflection electron microscope image) photograph of the cross section of the epitaxial layer for surface emitting lasers. Process drawing from mesa etching to lateral oxidation. Temperature profile of the oxidation process. Observation of lateral oxidation with an infrared microscope. Details of the process from insulating film formation to p-electrode formation. A photograph of a wafer that has been mirror-polished on the back side. The graph which shows the electric current-light intensity characteristic of the produced surface emitting laser, and an electric current-voltage characteristic. The perspective view of the arrayed high output surface emitting laser device.

Explanation of symbols

101: antireflection film, 102: upper electrode, 103: substrate, 104: N-type DBR mirror, 105: resonator, 106: active layer quantum well, 107: resonator, 108: P-type DBR mirror, 109: insulating film 110: Lower electrode.

Claims (11)

  In a vertical cavity surface emitting laser in which a laminated structure in which a pair of distributed Bragg reflector type semiconductor multilayer reflectors are arranged above and below an active layer is formed on a semiconductor substrate, and laser light is extracted from the n type multilayer reflector side, The p-type multilayer reflector is alternately stacked with 39 pairs or more of p-type AlGaAs having different compositions, and the n-type multilayer reflector is alternately stacked with n-type AlGaAs having different compositions. A vertical-cavity high-power surface-emitting laser characterized in that the number is less than the number of reflecting mirrors.   The vertical cavity type high output surface emitting laser according to claim 1, wherein the number of stacked p-type multilayer mirrors is 48 pairs or less.   The vertical cavity type high-power surface emitting laser according to claim 1 or 2, wherein the number of stacked n-type multilayer mirrors is 28 to 30 pairs.   In a vertical cavity surface emitting laser in which a laminated structure in which a pair of distributed Bragg reflector type semiconductor multilayer reflectors are arranged above and below an active layer is formed on a semiconductor substrate, and laser light is extracted from the p type multilayer reflector side, The n-type multilayer mirror is alternately stacked with 39 pairs or more of n-type AlGaAs having different compositions, and the p-type multilayer mirror is alternately stacked with p-type AlGaAs having different compositions. A vertical-cavity high-power surface-emitting laser characterized in that the number is less than the number of reflecting mirrors.   The vertical cavity type high-power surface emitting laser according to claim 4, wherein the number of stacked n-type multilayer mirrors is 48 pairs or less.   6. The vertical-cavity high-power surface-emitting laser according to claim 4, wherein the number of stacked p-type multilayer reflectors is 28 to 30 pairs.   In a vertical cavity surface emitting laser in which a stacked structure in which a pair of distributed Bragg reflector type semiconductor multilayer reflectors are disposed above and below an active layer is formed on a semiconductor substrate, the band offset of the active layer is 9 to 15 nm. A vertical-cavity high-power surface-emitting laser that is characterized.   The vertical cavity type high-power surface emitting laser according to any one of claims 1 to 6, wherein the active layer has a band offset of 9 to 15 nm.   9. The vertical-cavity high-power surface emitting laser according to claim 1, wherein the active layer is a quantum well layer having 2 to 4 layers.   An array is configured by two-dimensionally arranging the vertical cavity surface emitting lasers according to any one of claims 1 to 9, and a cooling device is brought into contact with the non-emitting side of the array, and is concentrated on the emitting side of the array. A high-power surface-emitting laser device comprising an optical system for light.   The high-power surface-emitting laser device according to claim 10, wherein the condensing optical system includes a microlens for each light emitting laser and a condensing lens for all light emitting lasers.

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