CN216436399U

CN216436399U - VCSEL chip

Info

Publication number: CN216436399U
Application number: CN202123454845.2U
Authority: CN
Inventors: 张怡静; 陈明; 张海洋; 王冰雪; 钱富琛; 王建明
Original assignee: Wuhan Raycus Fiber Laser Technologies Co Ltd
Current assignee: Wuhan Raycus Fiber Laser Technologies Co Ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2022-05-03
Anticipated expiration: 2031-12-31

Abstract

The application provides a VCSEL chip, which comprises a first substrate, a first DBR layer, a quantum well layer, a second DBR layer and a micro lens, wherein the first substrate comprises a first surface and a second surface which are oppositely arranged, the first surface comprises a first sub-surface, a second sub-surface and a third sub-surface which are sequentially arranged, and the first substrate further comprises a third surface; the first DBR layer is positioned on the second surface; the quantum well layer is positioned on the surface of the first DBR layer far away from the first substrate; the second DBR layer is positioned on the surface of the quantum well layer far away from the first DBR layer, and the doping concentration of the first DBR layer is different from that of the second DBR layer; the micro lens is located on the third surface, and the second sub-surface is used for reflecting the incident light beam onto the micro lens. The incident light beams are reflected to the micro lens through the second sub-surface, the light beam direction output by the micro lens is guaranteed to be parallel to the first sub-surface, and the light beam deflection is realized without an additional lens device.

Description

VCSEL chip

Technical Field

The application relates to the field of laser chips, in particular to a VCSEL chip.

Background

A VCSEL (Vertical-cavity surface-emitting laser) is essentially a semiconductor laser, which is a device for emitting laser light. Semiconductor lasers can be classified into Edge Emitting Lasers (EELs) and Vertical Cavity Surface Emitting Lasers (VCSELs) according to the structure of a Laser chip. Different from the traditional edge-emitting laser, the laser emitting direction of the VCSEL is perpendicular to the surface of the substrate, and a circular light spot can be obtained. Because the resonant cavity length is close to the wavelength, the dynamic single-mode is better, and the LED light source has the characteristics of high luminous efficiency, extremely low power consumption and good light beam quality. VCSEL vertical extraction is more suitable for two-dimensional array formation. In addition, the threshold current of the VCSEL is small, and the VCSEL can work under low current of 1-2 mA.

VCSELs have mainly two basic structures, one being a top-emitting structure: the quantum well active region is grown on an n-type GaAs substrate by using a Metal Organic Chemical Vapor Deposition (MOCVD) technology, a Distributed Bragg Reflector (DBR) is used as a laser cavity mirror, and the quantum well active region is positioned between the n-DBR and the p-DBR. Because the quantum well is small in thickness and small in one-way gain, the reflectivity of the reflector is high, the reflectivity of a general total reflection cavity mirror is more than 99.9%, and then metal contact layers are manufactured on the outer surfaces of the substrate and the p-DBR. And a circular light-emitting window is manufactured on the p-DBR or the n-DBR to obtain a circular light beam, the diameter of the window can be from several micrometers to several hundred micrometers, and finally the window is bonded with a heat sink with good heat conductivity, so that the heat dissipation performance of the chip is improved. The other is a bottom emission structure which is generally used for generating a 976-1064 nm wave band, the substrate is usually thinned to be below 150 mu m to reduce the substrate absorption loss, an antireflection film is grown to improve the laser beam quality, and finally the gain chip is installed on a heat sink.

The light-emitting direction of the VCSEL can only be vertical to the substrate, and an additional lens device is generally needed to deflect the light beam. In addition, the current injection is concentrated, and the substrate is thick, so that the problems of poor heat dissipation effect and transverse mode phenomenon are often caused.

The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

SUMMERY OF THE UTILITY MODEL

The main objective of the present application is to provide a VCSEL chip to solve the problem that the VCSEL can only emit light perpendicular to the substrate in the prior art.

In order to achieve the above object, according to one aspect of the present application, there is provided a VCSEL chip, the VCSEL chip comprises a first substrate, a first DBR layer, a quantum well layer, a second DBR layer and a micro lens, wherein the first substrate comprises a first surface and a second surface which are oppositely arranged, the first surface comprises a first sub-surface, a second sub-surface and a third sub-surface which are sequentially arranged, the first sub-surface, the third sub-surface and the second surface are parallel to each other, the distance between the first sub-surface and the second surface is a first distance, the third sub-surface is a second distance from the second surface, the first distance being less than the second distance, the second sub-surface is in contact with the first sub-surface and the third sub-surface, respectively, the first substrate further comprising a third surface in contact with the third sub-surface and the second surface, respectively; the first DBR layer is located on the second surface; the quantum well layer is positioned on the surface of the first DBR layer far away from the first substrate; the second DBR layer is positioned on the surface of the quantum well layer far away from the first DBR layer, and the doping concentration of the first DBR layer is different from that of the second DBR layer; the micro lens is located on the third surface, and the second sub-surface is used for reflecting an incident light beam onto the micro lens.

Optionally, the VCSEL chip further includes a plurality of oxidation limiting parts, a first electrode, a second electrode, and a heat sink, wherein the oxidation limiting parts are spaced apart from each other between the second DBR layer and the quantum well layer, and each oxidation limiting part is in contact with the second DBR layer and the quantum well layer, respectively; the first electrode is located on the first sub-surface and the third sub-surface; the second electrode is positioned on the surface of the second DBR layer far away from the quantum well layer; the heat sink is located on a surface of the second electrode distal from the second DBR layer.

Optionally, the material of the oxidation limiting portion is aluminum, the material of the heat sink is a metal material, and the materials of the first electrode and the second electrode are Au, Ge, or Ni.

Optionally, the VCSEL chip further includes a second substrate and a passivation layer, wherein the second substrate is located between the heat sink and the quantum well layer, and the second substrate has a through hole; the passivation layer is located on the side wall of the through hole, the passivation layer is further located on the surface, close to the quantum well layer, of the second substrate and is in contact with the quantum well layer, and the second electrode, the second DBR layer and the oxidation limiting portion are sequentially filled in the through hole in the direction close to the quantum well layer.

Optionally, there are a plurality of the first substrate, the first DBR layer, the quantum well layer, the second DBR layer, the microlens, the second substrate, the passivation layer, and the second electrode, respectively, and the first substrate, the first DBR layer, the quantum well layer, the second DBR layer, the microlens, the second substrate, the passivation layer, and the second electrode correspond to one another.

Optionally, there are a plurality of the first DBR layer, the quantum well layer, the second DBR layer, the micro lens, the second substrate, the passivation layer, and the second electrode, respectively, and the first DBR layer, the quantum well layer, the second DBR layer, the micro lens, the second substrate, the passivation layer, and the second electrode correspond to one another, the plurality of micro lenses are located on the third surface at intervals, and each of the first DBR layers is located on the second surface at intervals.

Optionally, the material of the second substrate is In, and the material of the passivation layer is silicon dioxide.

Optionally, the angle of the normal to the second sub-surface to the incident beam is greater than 16.2 °.

Optionally, the first DBR layer and the second DBR layer respectively include M first sublayers and M second sublayers alternately stacked, where 20 ≦ M ≦ 40, and refractive indices of the first sublayers and the second sublayers are different.

Optionally, the material of the first substrate is GaAs, and the material of the microlens is GaAs.

By applying the technical scheme of the application, the VCSEL chip comprises a first substrate, a first DBR layer, a quantum well layer, a second DBR layer and a micro lens, wherein the first substrate comprises a first surface and a second surface which are oppositely arranged, the first surface comprises a first sub-surface, a second sub-surface and a third sub-surface which are sequentially arranged, and the first substrate further comprises a third surface; the first DBR layer is located on the second surface; the quantum well layer is positioned on the surface of the first DBR layer far away from the first substrate; the second DBR layer is positioned on the surface of the quantum well layer far away from the first DBR layer, and the doping concentration of the first DBR layer is different from that of the second DBR layer; the micro lens is located on the third surface, and the second sub-surface is used for reflecting an incident light beam onto the micro lens. Compare among the prior art problem that VCSEL can only be perpendicular to substrate light-emitting, the VCSEL chip, this application, through the second sub-surface with incident beam reflection extremely on the microlens, can realize the deflection of light beam, the rethread the microlens is to after deflecting the light beam is collimated and is assembled, has guaranteed the beam direction of microlens output is on a parallel with first sub-surface need not to add the deflection that the lens device realized the light beam again.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:

fig. 1 shows a schematic diagram of a VCSEL chip according to a first embodiment of the present application;

FIGS. 2-5 respectively illustrate a flow diagram for microlens fabrication according to the present application;

figure 6 shows a schematic diagram of a VCSEL chip according to a second embodiment of the present application;

figure 7 shows a schematic diagram of a VCSEL chip according to a third embodiment of the present application;

fig. 8 shows a schematic diagram of a VCSEL chip according to a fourth embodiment of the present application.

Wherein the figures include the following reference numerals:

10. a first substrate; 20. a first DBR layer; 30. a quantum well layer; 40. a second DBR layer; 50. a microlens; 60. an oxidation limiting section; 70. a first electrode; 80. a second electrode; 90. a heat sink; 100. a second substrate; 101. a GaAs layer; 110. A passivation layer; 120. SiO 2₂A layer; 130. photoresist; 140. SiO 2₂And (4) a section.

Detailed Description

It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.

As described in the background, the VCSEL chip in the prior art can only emit light perpendicular to the substrate, and in order to solve the above problem, the present application proposes a VCSEL chip.

According to an exemplary embodiment of the present invention, there is provided a VCSEL chip, as shown in fig. 1, the VCSEL chip includes a first substrate 10, a first DBR layer 20, a quantum well layer 30, a second DBR layer 40, and a microlens 50, wherein the first substrate 10 includes a first surface and a second surface that are oppositely disposed, the first surface includes a first sub-surface, a second sub-surface, and a third sub-surface that are sequentially arranged, the first sub-surface, the third sub-surface, and the second surface are parallel to each other, the first sub-surface is separated from the second surface by a first distance d1, the third sub-surface is separated from the second surface by a second distance d2, the first distance d1 is smaller than the second distance d2, the second sub-surface is in contact with the first sub-surface and the third sub-surface, respectively, the first substrate further includes a third surface, said third surface being in contact with said third sub-surface and said second surface, respectively; the first DBR layer 20 is located on the second surface; the quantum well layer 30 is located on the surface of the first DBR layer 20 away from the first substrate 10; the second DBR layer 40 is located on a surface of the quantum well layer 30 away from the first DBR layer 20, and the doping concentrations of the first DBR layer 20 and the second DBR layer 40 are different; the micro lens 50 is located on the third surface, and the second sub-surface is used for reflecting an incident beam onto the micro lens.

The VCSEL chip comprises a first substrate, a first DBR layer, a quantum well layer, a second DBR layer and a microlens, wherein the first substrate comprises a first surface and a second surface which are oppositely arranged, the first surface comprises a first sub-surface, a second sub-surface and a third sub-surface which are sequentially arranged, and the first substrate further comprises a third surface; the first DBR layer is positioned on the second surface; the quantum well layer is positioned on the surface of the first DBR layer far away from the first substrate; the second DBR layer is located on a surface of the quantum well layer away from the first DBR layer, and the doping concentrations of the first DBR layer and the second DBR layer are different; the micro lens is located on the third surface, and the second sub-surface is used for reflecting an incident beam to the micro lens. Compare among the prior art VCSEL can only be perpendicular to the problem of substrate light-emitting, the foretell VCSEL chip of this application can realize the deflection of light beam through above-mentioned second sub-surface with incident beam reflection to above-mentioned microlens on, the rethread above-mentioned microlens is to the above-mentioned light beam after the deflection collimation and assemble, has guaranteed that the beam direction of above-mentioned microlens output is on a parallel with above-mentioned first sub-surface, need not to add the deflection that lens device realized the light beam again.

Specifically, the quantum well layer is composed of several In layers with thickness of 5-10 nm_xGa_1-xAs quantum well and Ga 5-10 nm thick_yAs_1-yThe P barrier layer is composed of (x is more than 0 and less than or equal to 1, and y is more than 0 and less than or equal to 1), wherein the quantum well layer is not doped. The included angle range between the second sub-surface and the first sub-surface is more than 0 and less than 90.

In a specific embodiment, as shown in fig. 2, the above microlens is prepared by the following steps: providing a GaAs layer 101; growing SiO with the thickness of 200nm on the surface of the GaAs layer 101 by using a PECVD method₂Layer 120 as a mask, SiO₂The thickness of layer 120 is detected by a film thickness monitor; then using the traditional photoetching technology to form the SiO₂A series of round holes with different diameters are formed on the surface, and the edges of the round holes need to be complete; as shown in fig. 3, using AZ4330 photoresist 130, the exposure time is 60s, the development time is 30s, after the development is finished, hardening the film on a heating plate at 100 ℃ for 20 min; as shown in fig. 4, reuse 1: 1: NH of 8₄F. HF and H₂Etching solution consisting of O is used for etching SiO inside the circular hole₂Etching off the remaining SiO₂Layer 120 is formed of SiO₂A portion 140; as shown in fig. 5, mostAfter HBr and H₂O₂、H₂And (3) corroding the micro lens 50 in a corrosive liquid consisting of O for 30min, wherein the proportion of the corrosive liquid is 2: 1: 60, the microlens 50 is finally formed to have a height of 0.55 μm in the middle and a diameter of 20 μm. Due to Br₂The probability of collision is smaller at the edge of the mask, so Br₂The edge diffusion is fast, the middle diffusion is slow, so the reaction at the periphery of the round hole is faster than the center of the round hole, convex lenses with different curvature radiuses can be corroded by controlling the corrosion time and the proportion of the corrosion liquid, the micro-lens can realize the auto-collimation of the output light beam, a lens device is not needed to be added, the light beam quality of the output light beam can be improved, the cost and the volume of the device can be greatly reduced, the VCSEL chips can be arranged into a one-dimensional array and a two-dimensional array, the output of lateral multi-light beams is realized, the integration of the device is facilitated, the VCSEL chip can realize that the VCSEL device of lateral emission can replace the traditional edge emitting laser to a certain extent, and the quality of the output light beam is higher than that of the edge emitting laser.

According to an embodiment of the present invention, as shown in fig. 1, the VCSEL chip further includes a plurality of oxidation limiting parts 60, a first electrode 70, a second electrode 80, and a heat sink 90, wherein the plurality of oxidation limiting parts 60 are spaced apart from each other between the second DBR layer 40 and the quantum well layer 30, and each oxidation limiting part 60 is in contact with the second DBR layer 40 and the quantum well layer 30; the first electrode 70 is located on the first sub-surface and the third sub-surface; the second electrode 80 is located on a surface of the second DBR layer 40 away from the quantum well layer 30; the heat sink 90 is located on a surface of the second electrode 80 away from the second DBR layer 40. The oxidation limiting part ensures that the threshold value of the VCSEL chip is small and has the function of inhibiting a high-order transverse mode, the radiating fin ensures that the VCSEL chip has good heat radiating performance, and the first electrode and the second electrode are used for inputting or outputting current.

Specifically, the specific preparation process of the oxidation restriction part is as follows: an N-surface light emitting structure is adopted, and current is injected from a P-surface circular electrode. Second DBRThe layer is etched on the table-board by wet chemical etching, and in the temperature range of 400-500 deg.C, nitrogen gas carrying 90 deg.C water vapor is oxidized to form an oxidation limiting part to limit the injected current. Etching by Inductively Coupled Plasma (ICP) to form a mesa, and performing Plasma Enhanced Chemical Vapor Deposition (PECVD) on the mesa to form a layer of SiO with a thickness of 200-300 nm₂And the insulating layer prevents current from being injected from the side direction of the mesa to cause short circuit of the device. A P-side electrode is formed on the second DBR layer. Bonding one side of the P surface of the VCSEL device on the heat dissipation sheet by using In solder;

in a specific embodiment, the second electrode is bonded to the heat sink, and the first electrode and the second electrode have a thickness of 50nm to 200 nm.

According to another specific embodiment of the present application, the material of the oxidation restricting portion is aluminum, the material of the heat sink is a metal material, and the materials of the first electrode and the second electrode are Au, Ge, or Ni.

Specifically, the material of the heat sink is copper or aluminum.

In a specific embodiment, the thickness of the oxidation limiting part is 10 to 100 nm.

According to another embodiment of the present application, as shown in fig. 1, the VCSEL chip further includes a second substrate 100 and a passivation layer 110, wherein the second substrate 100 is located between the heat sink 90 and the quantum well layer 30, and the second substrate 100 has a through hole; the passivation layer 110 is located on the sidewall of the through hole, the passivation layer 110 is also located on the surface of the second substrate 100 close to the quantum well layer 30 and contacts the quantum well layer 30, and the second electrode 80, the second DBR layer 40, and the oxidation restriction part 60 are sequentially filled in the through hole in a direction close to the quantum well layer 30. The second substrate is used for fixing the second DBR layer on the heat dissipation sheet, so that the heat dissipation performance of the VCSEL chip is better guaranteed, the passivation layer guarantees the insulation effect between the electrodes on one hand, and guarantees the surface effect of the VCSEL chip to be smaller on the other hand, and the contamination of dust, water vapor, acid gas or metal particles on the VCSEL chip is avoided.

According to a specific embodiment of the present invention, as shown in fig. 6, a plurality of the first substrate, the first DBR layer, the quantum well layer, the second DBR layer, the microlens, the second substrate, the passivation layer, and the second electrode are provided, and the first substrate, the first DBR layer, the quantum well layer, the second DBR layer, the microlens, the second substrate, the passivation layer, and the second electrode are in one-to-one correspondence. Therefore, the output of the lateral multi-beam is realized, and the integration of the device is facilitated.

In order to further realize the output of the side multi-beam, according to another embodiment of the present invention, as shown in fig. 7, a plurality of the first DBR layer, the quantum well layer, the second DBR layer, the microlens, the second substrate, the passivation layer, and the second electrode are provided, the first DBR layer, the quantum well layer, the second DBR layer, the microlens, the second substrate, the passivation layer, and the second electrode are provided in a one-to-one correspondence, a plurality of the microlenses are located at intervals on the third surface, and the first DBR layers are located at intervals on the second surface.

According to another embodiment of the present application, the material of the second substrate is In, and the material of the passivation layer is silicon dioxide.

According to an embodiment of the present application, the normal to the second sub-surface is at an angle greater than 16.2 ° to the incident beam. The angle between the normal of the second sub-surface and the incident beam is larger than 16.2 degrees, so that the light can be totally reflected by the second sub-surface, the direction of the beam output by the micro-lens is further ensured to be parallel to the first sub-surface, and the quality of the beam output by the micro-lens is also ensured to be better.

In a specific embodiment, the preparing process of the second sub-surface includes: performing inclined plane etching on the N-type GaAs substrate by utilizing ICP etching technology, wherein Cl is selected as etching gas₂/BCl₃Gas flow ratio 1: 3, Cl₂A flow rate of10sccm～30sccm， BCl₃The flow rate is 30-90 sccm, the power is 500-700W, and the gas pressure is 1-10 mTorr.

According to another embodiment of the present application, the first DBR layer and the second DBR layer respectively include M first sublayers and M second sublayers alternately stacked, wherein M is greater than or equal to 20 and less than or equal to 40, and refractive indexes of the first sublayers and the second sublayers are different. The first DBR layer and the DBR layer reflect light more than 99%, and light can be emitted according to a preset path.

In one embodiment, the first DBR layer is grown by growing 20-40 pairs of Al_xGa_1-xAs/Al_yGa_1-yAs (x is more than 0 and less than or equal to 1, y is more than 0 and less than or equal to 1). The P-type DBR is formed by growing 20-40 pairs of Al_xGa_1-xAs/Al_yGa_1-yAs (x is more than 0 and less than or equal to 1, y is more than 0 and less than or equal to 1). Wherein each of the first and second DBR layers has a thickness of 10-100 nm and a doping concentration of 1 × 10¹⁸/cm³～1×10¹⁹/cm³The optical thickness of each layer of material is 1/4 of the central reflection wavelength, and the electromagnetic wave with the frequency within the energy gap range can not pass through, thereby ensuring that the reflectivity of the first DBR layer and the second DBR layer can reach more than 99%.

According to another specific embodiment of the present application, the material of the first substrate is GaAs, and the material of the microlens is GaAs.

Specifically, when light is incident from an optically dense medium into an optically thinner medium, refraction and reflection occur simultaneously. If the angle of incidence is increased, the refracted light is further away from the normal and weaker, but the reflected light is stronger. When the angle of incidence is increased to an angle such that the angle of refraction reaches 90 deg., the refracted light disappears completely, leaving only the reflected light, a phenomenon known as total reflection. The angle of incidence at which the light happens to undergo the phenomenon of total reflection (i.e. the angle of refraction is equal to 90 °) is called the critical angle of the medium and is denoted by the letter C. When the material of the first substrate is GaAs, the refractive index of the GaAs material is 3.6, and the refractive index of air is 1, the critical angle at which total reflection occurs when light is emitted from GaAs to air is known as

The critical angle C is known to be about 16.2 °.

In a specific embodiment, the first DBR layer, the quantum well layer, the oxidation confining portion, the second DBR layer, the first electrode, and the second electrode are sequentially grown by Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE); the passivation layer is prepared by a Laser pulse Deposition (PLD) method.

Example 1: the structure of a single flip-chip side-emitting VCSEL chip and its fabrication process are shown in fig. 1.

Step 1: and sequentially growing an N-type DBR, a quantum well active region, an oxidation limiting layer and a P-type DBR on the N-type GaAs substrate by Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE). The N-type DBR is formed by growing 40 pairs of Al_0.90Ga_0.10As/Al_0.10Ga_0.90As material, each layer has a thickness of 20nm and N-type doping concentration of 4 × 10¹⁸/cm³. The P-type DBR is formed by growing 40 pairs of Al_0.90Ga_0.10As/Al_0.10Ga_0.90As material, each layer has a thickness of 20nm and a P-type doping concentration of 4 × 10¹⁸/cm³. The oxidation limiting layer is made of Al with high Al component_0.90Ga_0.10As (y is more than 0 and less than or equal to 1) material is obtained by oxidation, the thickness is 30nm, the P-type doping concentration is 5 multiplied by 10¹⁸/cm³. The quantum well active region is composed of 3 pairs of In_0.17Ga_0.83As quantum well and Ga_0.08As_0.92A P barrier layer. The quantum well thickness is 6nm and is undoped. The thickness of the barrier layer is 4nm and is not doped. The doping concentration of the N-type GaAs substrate is 1 × 10¹⁸/cm³；

Step 2: an N-surface light emitting structure is adopted, and current is injected from a P-surface circular electrode. Etching the mesa of the P-type DBR by wet chemical etching, and oxidizing the mesa at 450 ℃ for 4 hours by nitrogen carrying 90 ℃ water vapor to form Al_xO_yAnd the insulating layer limits the injection current. Forming a mesa by Inductively Coupled Plasma (ICP) etching, and forming a layer of SiO with a thickness of 200nm on the mesa by Plasma Enhanced Chemical Vapor Deposition (PECVD)₂And the insulating layer prevents the current from being injected from the side direction of the mesa to cause short circuit of the device. And preparing a P-plane electrode on the second DBR layer. Bonding one side of the P surface of the VCSEL device on the heat dissipation sheet by using In solder;

and step 3: performing bevel etching on the N-type GaAs substrate by using ICP (inductively coupled plasma) etching technology, wherein Cl is selected as etching gas₂/BCl₃The gas flow ratio is 1: 3, Cl₂Flow rate of 20sccm, BCl₃The flow rate is 60sccm, the power is 500W, and the air pressure is 1 mTorr;

and 4, step 4: as shown in FIG. 2, SiO is grown on GaAs surface by PECVD to a thickness of 200nm₂As a mask, SiO₂The thickness of the thin film is detected by a film thickness monitor. If the thickness is thinner, pinholes are easy to generate during photoetching corrosion, and the surface flatness is influenced; if the thickness is thicker, the etching time after photoetching is too long, so that the edge is irregular, and the surface appearance of the micro lens is influenced. Then, using a conventional photolithography process, as shown in FIG. 3, on SiO₂A series of round holes with different diameters are formed on the surface, the edges of the round holes need to be complete, and the SiO is corroded later₂And the formation of microlenses is very influential. Mainly the exposure time and the development time are controlled. And adopting AZ4330 photoresist, wherein the exposure time is 60s, the developing time is 30s, and after the development is finished, hardening the film on a heating plate at 100 ℃ for 20 min. As shown in fig. 4, reuse 1: 1: NH of 8₄F. HF and H₂Etching solution consisting of O is used for etching SiO in the round hole₂And (4) corroding. As shown in fig. 5, finally in HBr, H₂O₂、H₂Corroding the micro-lens in a corrosive liquid consisting of O for 30min, wherein the proportion of the corrosive liquid is 2: 1: 60, adding a solvent to the mixture;

and 5, after the GaAs micro lens is prepared, preparing an N-surface electrode of the VCSEL laser. Finally, the inverted side-emitting VCSEL laser is formed.

Example 2: the one-dimensional array emits light from different sides, and integrates VCSEL laser chips such as 2 × 4, 2 × 8, 2 × 12, 2 × 16, 2 × 32, etc., and the specific schematic diagram is shown in fig. 6. The main difference between embodiment 2 and embodiment 1 is that two mutually symmetrical VCSEL laser arrays are bonded on the same heat sink.

Step 1: and sequentially growing an N-type DBR, a quantum well active region, an oxidation limiting layer and a P-type DBR on the N-type GaAs substrate by Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE). The N-type DBR is formed by growing 30 pairs of Al_0.80Ga_0.20As/Al_0.20Ga_0.80As material, each layer has a thickness of 15nm and an N-type doping concentration of 4.5 × 10¹⁸/cm³. The P-type DBR is formed by growing 30 pairs of Al_0.80Ga_0.20As/Al_0.20Ga_0.80As material, each layer has a thickness of 15nm and a P-type doping concentration of 4.5 × 10¹⁸/cm³. The oxidation limiting layer is made of Al with high Al content_0.90Ga_0.10As (y is more than 0 and less than or equal to 1) material is obtained by oxidation, the thickness is 40nm, the P-type doping concentration is 6 multiplied by 10¹⁸/cm³. The quantum well active region is composed of 3 pairs of In_0.17Ga_0.83As quantum well and Ga_0.08As_0.92A P barrier layer. The quantum well thickness is 6nm and is undoped. The thickness of the barrier layer is 4nm and is not doped. The doping concentration of the N-type GaAs substrate is 1 × 10¹⁸/cm³；

Step 2: an N-surface light emitting structure is adopted, and current is injected from a P-surface circular electrode. Etching the mesa of the P-type DBR by wet chemical etching, and oxidizing the mesa at 400 ℃ for 5 hours by nitrogen carrying 90 ℃ water vapor to form Al_xO_yAnd the insulating layer limits the injection current. Forming a mesa by Inductively Coupled Plasma (ICP) etching, and forming a layer of SiO with a thickness of 200nm on the mesa by Plasma Enhanced Chemical Vapor Deposition (PECVD)₂And the insulating layer prevents the current from being injected from the side direction of the mesa to cause short circuit of the device. And preparing a P-plane electrode on the second DBR layer. The P-side of the VCSEL device is bonded to the heat sink with In solder. Forming a 2 × 4, 2 × 8, 2 × 12, 2 × 16, 2 × 32, etc. VCSEL array;

and 3, step 3: performing bevel etching on the N-type GaAs substrate by using ICP (inductively coupled plasma) etching technology, wherein Cl is selected as etching gas₂/BCl₃The gas flow ratio is 1: 3, Cl₂Flow rate of 20sccm, BCl₃The flow rate was 60sccm, the power was 500W, and the gas pressure was 1 mTorr. The inclined planes of the two VCSEL chips in each row form a symmetrical structure;

and 4, step 4: as shown in FIG. 2, SiO is grown on GaAs surface by PECVD to a thickness of 200nm₂As a mask, SiO₂The thickness of the thin film is detected by a film thickness monitor. If the thickness is thinner, pinholes are easy to generate during photoetching corrosion, and the surface flatness is influenced; if the thickness is thicker, the etching time after photoetching is too long, so that the edge is irregular, and the surface appearance of the micro lens is influenced. Then, using a conventional photolithography process, as shown in FIG. 3, on SiO₂A series of round holes with different diameters are formed on the surface, the edges of the round holes need to be complete, and the SiO is corroded later₂And the formation of microlenses is very influential. Mainly the exposure time and the development time are controlled. And adopting AZ4330 photoresist, wherein the exposure time is 60s, the developing time is 30s, and after the development is finished, hardening the film on a heating plate at 100 ℃ for 20 min. As shown in fig. 4, reuse 1: 1: NH of 8₄F. HF and H₂Etching solution consisting of O is used for etching SiO in the round hole₂And (4) corroding. As shown in fig. 5, finally in HBr, H₂O₂、H₂Corroding the micro-lens in a corrosive liquid consisting of O, wherein the corrosion time is 30min, and the proportion of the corrosive liquid is 3: 1: 55;

and 5: after the GaAs micro lens is prepared, SiO is deposited between the two VCSEL lasers₂And (3) a layer. The current interference between the two VCSEL laser chips is prevented, and the photoelectric conversion efficiency between the two VCSEL laser chips is further influenced;

step 6: and after the GaAs micro lens is prepared, preparing an N-surface electrode of the VCSEL laser. Finally, the inverted side-emitting VCSEL laser is formed.

Example 3: the one-dimensional array emits light from the same side, and integrates VCSEL laser chips of 2 × 4, 2 × 8, 2 × 12, 2 × 16, 2 × 32, and the like, and the specific schematic diagram is shown in fig. 7. The main difference between embodiment 3 and embodiment 1 is that a plurality of VCSEL devices are fabricated on the same GaAs substrate.

Step 1: sequentially growing an N-type DBR, a quantum well active region and oxygen on an N-type GaAs substrate by Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE)A confinement layer and a P-type DBR. The N-type DBR is formed by growing 30 pairs of Al_0.70Ga_0.30As/Al_0.30Ga_0.70As material, each layer has a thickness of 15nm and an N-type doping concentration of 4.5 × 10¹⁸/cm³. The P-type DBR is formed by growing 30 pairs of Al_0.70Ga_0.30As/Al_0.30Ga_0.70As material, each layer has a thickness of 15nm and a P-type doping concentration of 4.5 × 10¹⁸/cm³. The oxidation limiting layer is made of Al with high Al component_0.90Ga_0.10As (y is more than 0 and less than or equal to 1) material is obtained by oxidation, the thickness is 40nm, the P-type doping concentration is 6 multiplied by 10¹⁸/cm³. The quantum well active region is composed of 3 pairs of In_0.17Ga_0.83As quantum well and Ga_0.08As_0.92A P barrier layer. The quantum well thickness is 6nm and is undoped. The thickness of the barrier layer is 4nm and is not doped. The doping concentration of the N-type GaAs substrate is 1 × 10¹⁸/cm³；

and 3, step 3: performing bevel etching on the N-type GaAs substrate by using ICP (inductively coupled plasma) etching technology, wherein Cl is selected as etching gas₂/BCl₃The gas flow ratio is 1: 3, Cl₂Flow rate of 20sccm, BCl₃The flow rate was 60sccm, the power was 500W, and the gas pressure was 1 mTorr. The laser emitted by a plurality of VCSEL lasers can be reflected on the same inclined plane;

and 4, step 4: as shown in FIG. 2, SiO is grown on GaAs surface by PECVD to a thickness of 200nm₂As a mask, SiO₂The thickness of the thin film is detected by a film thickness monitor. If the thickness is thinner, pinholes are easy to generate during photoetching corrosion, and the surface flatness is influenced; if the thickness is thicker, the etching time after photoetching is too long, so that the edge is irregular, and the surface appearance of the micro lens is influenced. Then, using a conventional photolithography process, as shown in FIG. 3, on SiO₂A series of round holes with different diameters are formed on the surface, the edges of the round holes need to be complete, and the SiO is corroded later₂And the formation of microlenses is very influential. Mainly controls the exposure time and the development time. And adopting AZ4330 photoresist, wherein the exposure time is 60s, the developing time is 30s, and after the development is finished, hardening the film on a heating plate at 100 ℃ for 20 min. As shown in fig. 4, reuse 1: 1: NH of 8₄F. HF and H₂Etching solution consisting of O is used for etching SiO in the round hole₂And (4) corroding. As shown in fig. 5, finally in HBr, H₂O₂、H₂Corroding the micro-lens in a corrosive liquid consisting of O, wherein the corrosion time is 30min, and the proportion of the corrosive liquid is 3: 1: 55. etching a plurality of GaAs micro lenses on the side surface of the GaAs substrate;

and 5: and after the GaAs micro lens is prepared, preparing an N-surface electrode of the VCSEL laser. Finally, the inverted side-emitting VCSEL laser is formed.

Example 4: two-dimensional array light is emitted from different sides, and VCSEL laser chips such as 4 × 4, 4 × 8, 4 × 12, 4 × 16, 4 × 32, etc. are integrated, and the specific schematic diagram is shown in fig. 8.

Step 1: and sequentially growing an N-type DBR, a quantum well active region, an oxidation limiting layer and a P-type DBR on the N-type GaAs substrate by Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE). The N-type DBR is formed by growing 40 pairs of Al_0.60Ga_0.40As/Al_0.40Ga_0.60As material, each layer has a thickness of 15nm and an N-type doping concentration of 4.5 × 10¹⁸/cm³. The P-type DBR is formed by growing 30 pairs of Al_0.60Ga_0.40As/Al_0.40Ga_0.60As material, each layer has a thickness of 15nm and a P-type doping concentration of 4.5 × 10¹⁸/cm³. The oxidation limiting layer is made of Al with high Al component_0.90Ga_0.10As (y is more than 0 and less than or equal to 1) material is obtained by oxidation, the thickness is 40nm, and the P type doping concentration isDegree of 6X 10¹⁸/cm³. The quantum well active region is composed of 3 pairs of In_0.17Ga_0.83As quantum well and Ga_0.08As_0.92A P barrier layer. The quantum well thickness is 6nm and is undoped. The thickness of the barrier layer is 4nm and is not doped. The doping concentration of the N-type GaAs substrate is 1 × 10¹⁸/cm³；

and step 3: performing bevel etching on the N-type GaAs substrate by using ICP (inductively coupled plasma) etching technology, wherein Cl is selected as etching gas₂/BCl₃The gas flow ratio is 1: 3, Cl₂Flow rate of 20sccm, BCl₃The flow rate was 60sccm, the power was 500W, and the gas pressure was 1 mTorr. The laser emitted by a plurality of VCSEL lasers can be reflected on the same inclined plane;

and 4, step 4: as shown in FIG. 2, SiO is grown on GaAs surface by PECVD to a thickness of 200nm₂As a mask, SiO₂The thickness of the thin film is detected by a film thickness monitor. If the thickness is thinner, pinholes are easy to generate during photoetching corrosion, and the surface flatness is influenced; if the thickness is thicker, the etching time after photoetching is too long, so that the edge is irregular, and the surface appearance of the micro lens is influenced. Then, using a conventional photolithography process, as shown in FIG. 3, on SiO₂A series of round holes with different diameters are formed on the surface, the edges of the round holes need to be complete, and the SiO is corroded later₂And the formation of microlenses is very influential. Mainly controls the exposure time and the development time. Using AZ4330 photoresist, exposure time is 60s, development time is 30s, developingAfter the development, the film was hardened on a hot plate at 100 ℃ for 20 min. As shown in fig. 4, reuse 1: 1: NH of 8₄F. HF and H₂Etching solution consisting of O is used for etching SiO in the round hole₂And (4) corroding. As shown in fig. 5, finally in HBr, H₂O₂、H₂Corroding the micro-lens in a corrosive liquid consisting of O, wherein the corrosion time is 30min, and the proportion of the corrosive liquid is 3: 1: 55. etching a plurality of GaAs micro lenses on the side surface of the GaAs substrate;

and 5: after the GaAs micro lens is prepared, SiO is deposited between the two VCSEL laser arrays prepared in the step 2₂And (3) a layer. The mutual current interference between the two VCSEL laser arrays is prevented, and the photoelectric conversion efficiency between the two VCSEL laser arrays is further prevented from being influenced;

step 6: and after the GaAs micro lens is prepared, preparing an N-surface electrode of the VCSEL laser. Finally, a flip-chip side-emitting VCSEL laser is formed.

In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.

From the above description, it can be seen that the above-mentioned embodiments of the present application achieve the following technical effects:

the VCSEL chip comprises a first substrate, a first DBR layer, a quantum well layer, a second DBR layer and a microlens, wherein the first substrate comprises a first surface and a second surface which are oppositely arranged, the first surface comprises a first sub-surface, a second sub-surface and a third sub-surface which are sequentially arranged, and the first substrate further comprises a third surface; the first DBR layer is located on the second surface; the quantum well layer is positioned on the surface of the first DBR layer far away from the first substrate; the second DBR layer is located on a surface of the quantum well layer away from the first DBR layer, and the doping concentrations of the first DBR layer and the second DBR layer are different; the micro lens is located on the third surface, and the second sub-surface is used for reflecting an incident beam to the micro lens. Compared with the problem that the VCSEL can only emit light perpendicular to the substrate in the prior art, the VCSEL chip can reflect incident light beams to the micro lens through the second sub-surface, deflection of the light beams can be achieved, the deflected light beams are collimated and converged through the micro lens, the light beam direction output by the micro lens is parallel to the first sub-surface, and deflection of the light beams is achieved without an additional lens device.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A VCSEL chip, comprising:

the first substrate comprises a first surface and a second surface which are oppositely arranged, the first surface comprises a first sub-surface, a second sub-surface and a third sub-surface which are sequentially arranged, the first sub-surface, the third sub-surface and the second surface are parallel to each other, the distance between the first sub-surface and the second surface is a first distance, the distance between the third sub-surface and the second surface is a second distance, the first distance is smaller than the second distance, the second sub-surface is respectively in contact with the first sub-surface and the third sub-surface, the first substrate further comprises a third surface, and the third surface is respectively in contact with the third sub-surface and the second surface;

a first DBR layer on the second surface;

a quantum well layer located on a surface of the first DBR layer remote from the first substrate;

a second DBR layer located on a surface of the quantum well layer away from the first DBR layer, the first DBR layer and the second DBR layer having different doping concentrations;

a microlens located on the third surface, the second sub-surface for reflecting an incident beam onto the microlens.

2. The VCSEL chip of claim 1, wherein the VCSEL chip further comprises:

a plurality of oxidation limiting parts which are arranged between the second DBR layer and the quantum well layer at intervals, and are respectively contacted with the second DBR layer and the quantum well layer;

a first electrode located on the first sub-surface and the third sub-surface;

a second electrode on a surface of the second DBR layer remote from the quantum well layer;

a heat sink on a surface of the second electrode distal from the second DBR layer.

3. The VCSEL chip of claim 2, wherein a material of the oxidation limiting portion is aluminum, a material of the heat sink is a metal material, and materials of the first electrode and the second electrode are Au, Ge or Ni.

4. The VCSEL chip in accordance with claim 2, wherein the VCSEL chip further comprises:

a second substrate between the heat sink and the quantum well layer, the second substrate having a through-hole;

and the passivation layer is positioned on the side wall of the through hole, is also positioned on the surface, close to the quantum well layer, of the second substrate and is in contact with the quantum well layer, and the second electrode, the second DBR layer and the oxidation limiting part are sequentially filled in the through hole along the direction close to the quantum well layer.

5. The VCSEL chip of claim 4, wherein the first substrate, the first DBR layer, the quantum well layer, the second DBR layer, the microlens, the second substrate, the passivation layer, and the second electrode are respectively plural in number, and the first substrate, the first DBR layer, the quantum well layer, the second DBR layer, the microlens, the second substrate, the passivation layer, and the second electrode are in one-to-one correspondence.

6. The VCSEL chip of claim 4, wherein the first DBR layer, the quantum well layer, the second DBR layer, the microlens, the second substrate, the passivation layer, and the second electrode are respectively provided in plural numbers, the first DBR layer, the quantum well layer, the second DBR layer, the microlens, the second substrate, the passivation layer, and the second electrode are provided in one-to-one correspondence, the plurality of microlenses are located at intervals on the third surface, and the first DBR layers are located at intervals on the second surface.

7. A VCSEL chip according to any of claims 4 to 6, wherein a material of the second substrate is In and a material of the passivation layer is silicon dioxide.

8. The VCSEL chip of any of claims 1 to 6, wherein a normal of the second sub-surface is at an angle greater than 16.2 ° to the incident beam.

9. The VCSEL chip of any of claims 1 to 6, wherein the first DBR layer and the second DBR layer respectively include M alternately stacked first sub-layers and second sub-layers, wherein 20M 40, the first sub-layers and the second sub-layers have different refractive indices.

10. The VCSEL chip of any of claims 1 to 6, wherein a material of the first substrate is GaAs and a material of the microlens is GaAs.