CN117054861A - Isolation test method for multichannel digital isolation chip - Google Patents
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Abstract
The application relates to the field of isolation test of output signals of precision electronic equipment and integrated circuit digital isolation chips, which is suitable for an isolation test method of a multichannel digital isolation chip.
Description
Technical Field
The application relates to the field of isolation test of output signals of precision electronic equipment and integrated circuit digital isolation chips, and is suitable for an isolation test method of a multichannel digital isolation chip.
Background
With the continuous progress of integrated circuit technology, the multichannel digital isolation chip realizes higher integration level. Modern multichannel digital isolation chips can realize a plurality of input channels and output channels on a single chip, so that the complexity and cost of the system are reduced, and along with the increase of the requirements of digital communication and data processing, the transmission rate of the multichannel digital isolation chips is also improved. The prior multichannel digital isolation chip supports higher data transmission rate, meets the requirement of a high-speed communication system, and gradually reduces the power consumption of the multichannel digital isolation chip along with the improvement of the energy efficiency requirement. The low power consumption design makes the chip suitable for low energy consumption equipment and portable equipment, prolongs the service life of the battery, and has obvious improvement in the aspect of resisting external interference. Modern chip structures and designs enable them to effectively suppress electromagnetic interference and noise, providing more reliable data isolation and transmission, security: for some critical application fields, such as industrial control, medical equipment and the like, the security requirement of the multichannel digital isolation chip is higher and higher. Modern chips protect the safety of data and systems by adopting a safety isolation technology and protective measures, and are used in the fields of industrial automation, power system monitoring, instruments and meters, medical equipment, electric automobile charging piles and the like so as to realize the functions of signal isolation, data transmission, system protection and the like.
An implementation method and an implementation system for providing a multi-channel digital isolation chip are disclosed in, for example, patent application publication number CN111600593a, where the method includes: the number of the isolators is configured according to the number of the system transmission signal channels by adding mutually matched coder and decoder at two ends of the isolators; configuring the number of coding modes of an encoder according to the number of system transmission signal channels and the number of isolators; wherein n is less than m, cn is more than 2m, m is more than or equal to 2, m represents the number of system transmission signal channels, n represents the number of isolators, and C represents the number of coding patterns adopted by an encoder; in the data transmission process, a transmitting end transmits multichannel signal source data, encodes the multichannel signal source data to form an encoded signal and transmits the encoded signal to an isolator; and the receiving end receives the coded signal, decodes and reconstructs the coded signal to recover the original multi-channel signal, and outputs the multi-channel signal. The application reduces the size area of the digital isolation chip by reducing the number of the digital isolators.
The above patents exist: only the encoder is finely improved, the influence of environmental factors is not considered too much, and the temperature is not strictly controlled, so that the digital isolation signal is easily influenced by external electromagnetic influence or temperature influence, the encoding and decoding efficiency is influenced, and even the encoding and decoding accuracy is influenced.
The application has the advantages that: the problem of external interference signals under low-frequency signals is reduced, the modulation encoder separates rising edges and falling edges from input signals which are subjected to deburring through the filter, the filter circuit processes interference signals such as burrs on the external input signals so as not to influence the pulse generation circuit, and refresh signals can be fed into the pulse generation circuit at regular time according to the timing of the internal timing circuit, so that the influence of the external interference signals on pulses under the condition of larger signal period is avoided.
Disclosure of Invention
This section is intended to outline some aspects of embodiments of the application and to briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section as well as in the description of the application and in the title of the application, which may not be used to limit the scope of the application.
In order to solve the technical problems, the main purpose of the application is to provide an isolation test method of a multichannel digital isolation chip;
the problems in the background technology can be effectively solved: only the encoder is finely improved, the influence of environmental factors is not considered too much, and the temperature is not strictly controlled, so that the digital isolation signal is easily influenced by external electromagnetic influence or temperature influence, the encoding and decoding efficiency is influenced, and even the encoding and decoding accuracy is influenced.
In order to achieve the above purpose, the application provides an isolation test method of a multi-channel digital isolation chip:
s1, receiving an input signal, and processing the input signal to obtain a processed input signal;
s2, generating a pulse signal through the input signal after the encoding processing;
s3, through eliminating pulse signal electromagnetic interference signals and recovering pulse signals into rising edge signals and falling edge signals, the rising edge signals and the falling edge signals are input into an on-chip transformer, and digital signals are converted into power signals;
s4, the power signal drives the on-chip transformer to generate a high-quality signal, and the high-quality signal is transmitted to the secondary side;
s5, the secondary side outputs an output signal and records a result;
s6, verifying the recorded result.
As a preferable scheme of the isolation test method of the multichannel digital isolation chip, the application comprises the following steps:
the input signal is subjected to cancellation filtering and rectification processing by signal input processing.
As a preferable scheme of the isolation test method of the multichannel digital isolation chip, the application comprises the following steps:
the pulse signals comprise double pulse signals and single pulse signals;
the signal after the elimination filtering and rectifying processing is received by an encoder, and a double pulse signal and a single pulse signal are respectively generated by rising and falling edges of the signal after the elimination filtering and rectifying processing.
As a preferable scheme of the isolation test method of the multichannel digital isolation chip, the application comprises the following steps:
the electromagnetic interference signals in the pulse signals are eliminated, the pulse signals are recovered to be rising edge signals and falling edge signals, the pulse signals are subjected to delay adjustment through the refreshing circuit, the delay time is adjusted through the delay circuit, and the rising edge signals and the falling edge signals are subjected to temperature adjustment through the bias current circuit.
As a preferable scheme of the isolation test method of the multichannel digital isolation chip, the application comprises the following steps:
the power signal drives the on-chip transformer to generate a high-quality signal, and the high-quality signal is transmitted into the secondary side receiving module and comprises the following components;
converting the digital signal through an inductance coil in the transformer to obtain the power signal;
the high-quality signal is subjected to width limitation on an extra pulse signal generated by the interference of the external electromagnetic signal, so that the interference of the external electromagnetic signal is eliminated.
As a preferable scheme of the isolation test method of the multichannel digital isolation chip, the application comprises the following steps:
the recorded results comprise an input channel test result, an output channel test result, an isolation test result, a response time test result, an anti-interference test result, a temperature change test result and a reliability test result;
the input channel test: determining the number of input channels of the multi-channel digital isolation chip, and testing the function and performance of each input channel, wherein the input channel test content comprises an input voltage range, input current and power consumption;
the output channel test: determining the number of output channels of the multi-channel digital isolation chip, and testing the function and performance of each output channel, wherein the test content of the output channels comprises an output voltage range, output current and driving capability;
the isolation test: testing isolation performance among input channels of the multichannel digital isolation chip, ensuring that input signals cannot interfere with each other, sending different signals to each input channel, and detecting whether the output signals are interfered or not;
the response time test: testing response time of an output channel of the multichannel digital isolation chip, namely changing time of an output signal after the input signal is changed;
the anti-interference performance test comprises the following steps: testing the anti-interference capability of the multichannel digital isolation chip to external interference, and ensuring the normal operation of the chip in an interference environment;
the temperature change test: testing the working performance and stability of the multichannel digital isolation chip at different temperatures, wherein the channel test content comprises the temperature drift and temperature influence of an input channel and an output channel;
the reliability test: the reliability and stability of the multichannel digital isolation chip under the conditions of long-time operation and high load are tested, and the channel test content comprises a persistence test and a high load test.
As a preferable scheme of the isolation test system of the multichannel digital isolation chip, the application comprises the following steps:
the transmitting module comprises a signal input processing unit for receiving an input signal and processing the input signal; an encoder for generating pulse signals corresponding to the rising edge and the falling edge according to the input signal; a refresh circuit unit for solving the problem that the two ends of the on-chip transformer are kept at low/high level for a long time due to the fact that the long-time input signal is at high level or low level; a bias current unit for generating a zero temperature current;
the secondary side receiving module comprises a monostable unit for performing width limitation on extra pulse generated by electromagnetic signal interference; the pulse recovery unit is used for converting the double pulse signal and the single pulse signal into a rising edge signal and a falling edge signal respectively, so that the signals are recovered into a shape before being encoded, when one edge of an input signal arrives, the timing unit is used for generating narrow timing pulses with equal discharge flow velocity every fixed time, and when a new edge signal arrives, the accumulated time length of the counting pulses is cleared, so that the operation is restarted; the error reporting unit is used for receiving the error reporting signal and sending out an error reporting indicator lamp;
the on-chip transformer driving module is used for converting the digital signals generated by encoding into power signals, so that the on-chip transformer is driven to transmit the signals to the secondary side with high quality, and an inductance coil in the transformer is used for converting the digital signals to obtain the power signals.
As a preferable scheme of the isolation test system of the multichannel digital isolation chip, the application comprises the following steps:
the signal input processing unit rectifies an input signal through the difference of the positive and negative turning level thresholds of the Schmitt trigger, filters interference signals superimposed on the input signal, and resets the processed filtering signal through the SR latch;
the encoder generates a double pulse signal and a single pulse signal respectively according to the rising edge and the falling edge of the input signal by receiving the interference signal and the reset input signal;
the refreshing circuit unit generates pulses for refreshing signals, which respectively correspond to rising edges and falling edges of input signals, and the default value of the pulses is 1, wherein the refreshing circuit unit further comprises a delay circuit, and the delay time is controlled by adjusting the size of the capacitor;
the bias current unit comprises a timing circuit, the timing circuit generates zero-temperature current by receiving one path of CTAT current and one path of PTAT current, VDDA is started to exceed PMOS conduction voltage, R1 is always pulled down to M1 grid electrode, M1 pipe is opened, conduction current is conducted, M2 deletion voltage is increased, when the voltage reaches the M2 conduction voltage value, M2 is conducted, the grid voltage of M4-M7-M12-M13 is pulled down, thus M4-M7-M12-M13 starts to have current to pass, PTAT current is generated, and the circuit is completely conducted.
As a preferable scheme of the isolation test system of the multichannel digital isolation chip, the application comprises the following steps:
the monostable unit limits the width of extra pulses generated by the interference of external electromagnetic signals received by an input end, IN is connected to the output of the Schmitt trigger, if the external signals are unchanged, the output of the trigger is unchanged by two reset ends of the capacitor charging timing module, and if the input signals have rising edges, the value IN the last state is output by the D trigger;
the pulse recovery unit receives the clock signal generated by the monostable unit, converts the input single pulse signal and double pulse signal into a falling edge and a rising edge respectively, and finally recovers the signal into a shape before encoding;
and the error reporting unit is used for reporting all input signals which do not arrive for more than 8 mu s as input signal errors, triggering an error mode by the error reporting unit and outputting a high level to light an error reporting indicator lamp.
As a preferable scheme of the isolation test system of the multichannel digital isolation chip, the application comprises the following steps:
the on-chip transformer driving module converts a digital signal into a power signal through the inductance coil, so that the signal is transmitted to the secondary side receiving module, if ENB and EN are both effective, the secondary side receiving module is equivalent to short circuit or open circuit, IN is equivalent to being directly connected to the NMOS driving tube through an inverter, if IN=H, NMOS driving voltage is low level, the grid electrode of the PMOS driving tube is grounded, VOUT is input with high level current, if IN=L, the grid voltage of the NMOS is high voltage, the driving tube of the NMOS is pulled up to VDD, and VOUT outputs large current.
A computer device comprising, a memory for storing instructions; and the processor is used for executing the instructions to enable the equipment to execute an isolation test method for realizing the multichannel digital isolation chip.
A computer readable storage medium having stored thereon a computer program which, when executed by the processor, implements a method of isolation testing of a multi-channel digital isolation chip.
The application has the beneficial effects that:
the application reduces the problem of external interference signals under low-frequency signals, and the modulation encoder separates rising edges and falling edges from the input signals which are subjected to deburring through the filter.
The filter circuit of the application processes the interference signals such as burrs and the like on the external input signals so as not to influence the pulse generation circuit, and can also feed the refresh signals to the pulse generation circuit at regular time according to the timing of the internal timing circuit, thereby avoiding the influence of the external interference signals on the pulses under the condition of larger signal period.
The application sets the delay circuit, the specific length of delay is controllable, and the delay time control can be realized by changing the size of the capacitor or the number of the inverters. The schmitt trigger is connected after the capacitor, so that the uncertainty influence caused by unstable voltage at two ends of the capacitor is avoided.
The bias current bias unit generates zero-temperature current and processes the influence of ambient temperature on an input signal.
The method solves the problem that the influence of environmental factors is not considered too much, the temperature is not strictly controlled, and thus, the digital isolation signal is easily influenced by external electromagnetic influence or temperature influence, thereby influencing the coding and decoding efficiency and even influencing the accuracy of coding and decoding.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
FIG. 1 is a flow chart of an isolation test method for a multi-channel digital isolation chip according to the present application;
FIG. 2 is a diagram showing the components of an isolation test system of a multi-channel digital isolation chip according to the present application;
FIG. 3 is a schematic diagram of an encoder circuit of an isolation test system of a multi-channel digital isolation chip according to the present application;
FIG. 4 is a schematic diagram of a monostable circuit of an isolation test system of a multi-channel digital isolation chip according to the present application;
FIG. 5 is a schematic diagram of a portion of an on-chip transformer driving module of an isolation test system for a multi-channel digital isolation chip according to the present application.
Detailed Description
In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the application will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.
Further, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic can be included in at least one implementation of the application. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
Further, in describing the embodiments of the present application in detail, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of description, and the schematic is only an example, which should not limit the scope of protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
Example 1
Referring to fig. 1, an isolation test method of a multi-channel digital isolation chip includes:
s1, receiving an input signal, and processing the input signal to obtain a processed input signal;
the method comprises the steps of performing elimination filtering and rectification processing on an input signal through a signal input processing unit;
s2, generating a pulse signal through the input signal after the encoding processing;
wherein the pulse signal comprises a double pulse signal and a single pulse signal;
further, the encoder receives the signal after the cancellation filtering and rectifying process, and generates a double pulse signal and a single pulse signal by respectively generating a rising edge and a falling edge of the signal after the cancellation filtering and rectifying process.
S3, through eliminating pulse signal electromagnetic interference signals and recovering pulse signals into rising edge signals and falling edge signals, the rising edge signals and the falling edge signals are input into an on-chip transformer, and digital signals are converted into power signals;
the pulse recovery unit is used for recovering and eliminating electromagnetic interference signals in the pulse signals and recovering the pulse signals into rising edge signals and falling edge signals;
furthermore, the refresh circuit unit carries out delay adjustment on the pulse signal, the delay time is adjusted through the delay circuit, and the temperature adjustment is carried out on the rising edge signal and the falling edge signal through the bias current unit.
S4, the power signal drives the on-chip transformer to generate a high-quality signal, and the high-quality signal is transmitted to the secondary side;
the inductance coil in the transformer driving module converts the digital signal to obtain the power signal;
further, the high-quality signal is subjected to width limitation on an extra pulse signal generated by interference of the external electromagnetic signal through the monostable unit, so that the interference of the external electromagnetic signal is eliminated;
s5, the secondary side outputs an output signal and records a result;
s6, verifying a recording result;
the test results comprise an input channel test result, an output channel test result, an isolation test result, a response time test result, an anti-interference test result, a temperature change test result and a reliability test result;
further, input channel test: determining the number of input channels of the multi-channel digital isolation chip, and testing the function and performance of each input channel, including input voltage range, input current and power consumption;
further, output channel test: determining the number of output channels of the multi-channel digital isolation chip, and testing the function and performance of each output channel, including output voltage range, output current and driving capability;
further, isolation test: testing isolation performance among input channels of the multichannel digital isolation chip, ensuring that input signals cannot interfere with each other, sending different signals to each input channel, and detecting whether the output signals are interfered or not;
further, response time test: and testing the response time of the output channel of the multichannel digital isolation chip, namely the change time of the output signal after the input signal is changed.
Further, interference immunity test: testing the anti-interference capability of the multichannel digital isolation chip on external interference (such as electromagnetic interference and noise) to ensure the normal operation of the chip in an interference environment;
temperature change test: testing the working performance and stability of the multichannel digital isolation chip at different temperatures, including temperature drift and temperature influence of input and output channels;
further, reliability test: the reliability and stability of the multichannel digital isolation chip under the conditions of long-time operation and high load are tested, including a persistence test and a high load test.
Example two
Referring to fig. 2, an isolation test system of a multi-channel digital isolation chip includes: the device comprises a sending module, a secondary side receiving module and an on-chip transformer driving module;
the signal input processing unit rectifies an input signal through the difference of the positive and negative turning level thresholds of the Schmitt trigger, filters interference signals superimposed on the input signal, and resets the processed filtering signal through the SR latch;
further, referring to fig. 3, the input of the encoder IO pin includes the output signal Vin of the filter and the refresh signals R1 and R2 of the refresh module, and the output is a modulated pulse signal.
Generating a double pulse signal and a single pulse signal respectively according to the rising edge and the falling edge of the input signal by receiving the interference-eliminating signal and the reset input signal;
further, the refresh circuit unit generates pulses for refresh signals, which respectively correspond to rising edges and falling edges of the input signals, and the default value of the pulses is 1, wherein the refresh circuit unit further comprises a delay circuit, and the delay time is controlled by adjusting the size of the capacitor;
further, the bias current unit comprises a timing circuit, the timing circuit generates zero-temperature current by receiving one path of CTAT current and one path of PTAT current, VDDA is started to exceed PMOS conduction voltage, R1 is always pulled down to M1 grid electrode, M1 tube is opened, conduction current is conducted, M2 deletion voltage is increased, when the voltage reaches the M2 conduction voltage value, M2 is conducted, the grid voltage of M4-M7-M12-M13 is pulled down, thus M4-M7-M12-M13 starts to have current to pass through, PTAT current is generated, and the circuit is completely conducted.
Referring to fig. 4, the monostable unit needs to be a D-flip-flop, a schmitt-trigger, a simple even-module and a corresponding digital logic circuit, the width of extra pulse generated by the interference of the external electromagnetic signal received by the input end is limited, the input Vin of the monostable circuit is used as the clock signal of the D-flip-flop, and the timing circuit is similar to the timing module, and the capacitor is charged by using the current which is obtained by mirror image copying from the timing module and is approximately irrelevant to the temperature coefficient. When the external input Vin pulses, if the output Q of the D flip-flop is low and the output QN of the D flip-flop is high, the output Vcap of the timing module is low due to the control action of QN, the output Vout of the monostable circuit is low, and then the outputs Q and QN are inverted under the action of the clock signal Vin, Q is high and QN is low. At this time, the timing module circuit starts to work, vcap starts to be charged and gradually rises, so that the output of the Schmitt trigger is pulled high, the output Vout is pulled high, the reset signal of the D trigger is pulled low after the circuit delay time of the Schmitt trigger and the inverter, and then Q and QN are reset and return to the initial circuit state. Thus throughout the process, the output Vout is pulled high from low to back low, generating a pulse. Conversely, if the D flip-flop output Q is high and QN is low when the external input Vin pulses come, the reset RST signal of the D flip-flop will be pulled low and reset.
Further, the pulse recovery unit receives the clock signal generated by the monostable unit, converts the input single pulse signal and double pulse signal into a falling edge and a rising edge respectively, and finally recovers the signal into a shape before encoding;
furthermore, the error reporting unit receives an input signal which does not come for any 8 mu s or longer time and generates a trigger pulse for the slow signal every 2 mu s, and the error reporting unit triggers an error mode and outputs a high-level electric-lighting error reporting indicator lamp.
Referring to fig. 5, the on-chip transformer driving module converts a digital signal into a power signal through an inductance coil, so that the signal is transmitted to the secondary side, if ENB and EN are both effective, the secondary side receiving module is equivalent to short circuit or open circuit, IN is equivalent to directly connecting to the NMOS driving tube through an inverter, if in=h, the NMOS driving voltage is low level, the gate of the PMOS driving tube is grounded, VOUT is input with a high level current, if in=l, the gate voltage of the NMOS is high voltage, the NMOS driving tube is pulled up to VDD, and VOUT outputs a large current.
Example III
A computer readable storage medium having stored thereon a computer program which, when executed, implements an isolation test method for a multi-channel digital isolation chip.
Example IV
A computer device comprising, a memory for storing instructions;
and the processor is used for executing the instructions to enable the equipment to execute an isolation test method for realizing the multichannel digital isolation chip.
The implementation of the embodiment can be realized: the application reduces the problem of external interference signals under low-frequency signals, and the modulation encoder separates rising edges and falling edges from the input signals which are subjected to deburring through the filter.
The filter circuit processes the interference signals such as burrs on the external input signals so as not to influence the pulse generation circuit, and can also feed refresh signals to the pulse generation circuit at regular time according to the timing of the internal timing circuit, so that the influence of the external interference signals on the pulses under the condition of larger signal period is avoided.
The specific length of the delay is controllable by arranging the delay circuit, and the delay time control can be realized by changing the size of the capacitor or the number of the inverters. The schmitt trigger is connected after the capacitor, so that the uncertainty influence caused by unstable voltage at two ends of the capacitor is avoided.
And the bias current bias unit generates zero-temperature current and processes the influence of the ambient temperature on an input signal.
It is important to note that the construction and arrangement of the application as shown in the various exemplary embodiments is illustrative only. Although only two embodiments have been described in detail in this disclosure, those skilled in the art who review this disclosure will readily appreciate that many modifications are possible (e.g., variations in sizes, dimensions, structures, shapes and proportions of the various elements, values of parameters (e.g., temperature, pressure, etc.), mounting arrangements, use of materials, colors, orientations, etc.) without materially departing from the novel teachings and advantages of the subject matter described in this application. For example, elements shown as integrally formed may be constructed of multiple parts or elements, the position of elements may be reversed or otherwise varied, and the nature or number of discrete elements or positions may be altered or varied. Accordingly, all such modifications are intended to be included within the scope of present application. The order or sequence of any process or method steps may be varied or re-sequenced according to alternative embodiments. In the claims, any means-plus-function clause is intended to cover the structures described herein as performing the function and not only structural equivalents but also equivalent structures. Other substitutions, modifications, changes and omissions may be made in the design, operating conditions and arrangement of the exemplary embodiments without departing from the scope of the present applications. Therefore, the application is not limited to the specific embodiments, but extends to various modifications that nevertheless fall within the scope of the appended claims.
Furthermore, in an effort to provide a concise description of the exemplary embodiments, all features of an actual implementation may not be described (i.e., those not associated with the best mode presently contemplated for carrying out the application, or those not associated with practicing the application).
It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made. Such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.
It should be noted that the above embodiments are only for illustrating the technical solution of the present application and not for limiting the same, and although the present application has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present application may be modified or substituted without departing from the spirit and scope of the technical solution of the present application, which is intended to be covered in the scope of the claims of the present application.
Claims (12)
1. An isolation test method of a multichannel digital isolation chip is characterized by comprising the following steps of: comprising the steps of (a) a step of,
s1, receiving an input signal, and processing the input signal to obtain a processed input signal;
s2, generating a pulse signal through the input signal after the encoding processing;
s3, through eliminating pulse signal electromagnetic interference signals and recovering pulse signals into rising edge signals and falling edge signals, the rising edge signals and the falling edge signals are input into an on-chip transformer, and digital signals are converted into power signals;
s4, the power signal drives the on-chip transformer to generate a high-quality signal, and the high-quality signal is transmitted to the secondary side;
s5, the secondary side outputs an output signal and records a result;
s6, verifying the recorded result.
2. The isolation test method of the multi-channel digital isolation chip according to claim 1, wherein the isolation test method comprises the following steps:
the input signal is subjected to cancellation filtering and rectification processing by signal input processing.
3. The isolation test method of the multi-channel digital isolation chip according to claim 2, wherein the isolation test method comprises the following steps:
the pulse signals comprise double pulse signals and single pulse signals;
the signal after the elimination filtering and rectifying processing is received by an encoder, and a double pulse signal and a single pulse signal are respectively generated by rising and falling edges of the signal after the elimination filtering and rectifying processing.
4. The isolation test method of the multi-channel digital isolation chip according to claim 1, wherein the isolation test method comprises the following steps:
the electromagnetic interference signals in the pulse signals are eliminated, the pulse signals are recovered to be rising edge signals and falling edge signals, the pulse signals are subjected to delay adjustment through the refreshing circuit, the delay time is adjusted through the delay circuit, and the rising edge signals and the falling edge signals are subjected to temperature adjustment through the bias current circuit.
5. The isolation test method of the multi-channel digital isolation chip according to claim 4, wherein the isolation test method comprises the following steps: the power signal drives the on-chip transformer to generate a high-quality signal, and the high-quality signal is transmitted into the secondary side receiving module, which comprises the following contents:
converting the digital signal through an inductance coil in the transformer to obtain the power signal;
the high-quality signal is subjected to width limitation on an extra pulse signal generated by the interference of the external electromagnetic signal, so that the interference of the external electromagnetic signal is eliminated.
6. The isolation test method of the multi-channel digital isolation chip according to claim 5, wherein the isolation test method comprises the following steps:
the recorded results comprise an input channel test result, an output channel test result, an isolation test result, a response time test result, an anti-interference test result, a temperature change test result and a reliability test result;
the input channel test: determining the number of input channels of the multi-channel digital isolation chip, and testing the function and performance of each input channel, wherein the input channel test content comprises an input voltage range, input current and power consumption;
the output channel test: determining the number of output channels of the multi-channel digital isolation chip, and testing the function and performance of each output channel, wherein the test content of the output channels comprises an output voltage range, output current and driving capability;
the isolation test: testing isolation performance among input channels of the multichannel digital isolation chip, ensuring that input signals cannot interfere with each other, sending different signals to each input channel, and detecting whether the output signals are interfered or not;
the response time test: testing response time of an output channel of the multichannel digital isolation chip, namely changing time of an output signal after the input signal is changed;
the anti-interference performance test comprises the following steps: testing the anti-interference capability of the multichannel digital isolation chip to external interference, and ensuring the normal operation of the chip in an interference environment;
the temperature change test: testing the working performance and stability of the multichannel digital isolation chip at different temperatures, wherein the channel test content comprises the temperature drift and temperature influence of an input channel and an output channel;
the reliability test: the reliability and stability of the multichannel digital isolation chip under the conditions of long-time operation and high load are tested, and the channel test content comprises a persistence test and a high load test.
7. An isolation test system of a multichannel digital isolation chip is characterized in that:
the transmitting module comprises a signal input processing unit for receiving an input signal and processing the input signal; an encoder for generating pulse signals corresponding to the rising edge and the falling edge according to the input signal; a refresh circuit unit for solving the problem that the two ends of the on-chip transformer are kept at low/high level for a long time due to the fact that the long-time input signal is at high level or low level; a bias current unit for generating a zero temperature current;
the secondary side receiving module comprises a monostable unit for performing width limitation on extra pulse generated by electromagnetic signal interference; the pulse recovery unit is used for converting the double pulse signal and the single pulse signal into a rising edge signal and a falling edge signal respectively, so that the signals are recovered into a shape before being encoded, when one edge of an input signal arrives, the timing unit is used for generating narrow timing pulses with equal discharge flow velocity every fixed time, and when a new edge signal arrives, the accumulated time length of the counting pulses is cleared, so that the operation is restarted; the error reporting unit is used for receiving the error reporting signal and sending out an error reporting indicator lamp;
the on-chip transformer driving module is used for converting the digital signals generated by encoding into power signals, so that the on-chip transformer is driven to transmit the signals to the secondary side with high quality, and an inductance coil in the transformer is used for converting the digital signals to obtain the power signals.
8. The isolation test system of a multi-channel digital isolation chip of claim 7, wherein:
the signal input processing unit rectifies an input signal through the difference of the positive and negative turning level thresholds of the Schmitt trigger, filters interference signals superimposed on the input signal, and resets the processed filtering signal through the SR latch;
the encoder generates a double pulse signal and a single pulse signal respectively according to the rising edge and the falling edge of the input signal by receiving the interference signal and the reset input signal;
the refreshing circuit unit generates pulses for refreshing signals, which respectively correspond to rising edges and falling edges of input signals, and the default value of the pulses is 1, wherein the refreshing circuit unit further comprises a delay circuit, and the delay time is controlled by adjusting the size of the capacitor;
the bias current unit comprises a timing circuit, the timing circuit generates zero-temperature current by receiving one path of CTAT current and one path of PTAT current, VDDA is started to exceed PMOS conduction voltage, R1 is always pulled down to M1 grid electrode, M1 pipe is opened, conduction current is conducted, M2 deletion voltage is increased, when the voltage reaches the M2 conduction voltage value, M2 is conducted, the grid voltage of M4-M7-M12-M13 is pulled down, thus M4-M7-M12-M13 starts to have current to pass, PTAT current is generated, and the circuit is completely conducted.
9. The isolation test system of a multi-channel digital isolation chip of claim 7, wherein:
the monostable unit limits the width of extra pulses generated by the interference of external electromagnetic signals received by an input end, IN is connected to the output of the Schmitt trigger, if the external signals are unchanged, the output of the trigger is unchanged by two reset ends of the capacitor charging timing module, and if the input signals have rising edges, the value IN the last state is output by the D trigger;
the pulse recovery unit receives the clock signal generated by the monostable unit, converts the input single pulse signal and double pulse signal into a falling edge and a rising edge respectively, and finally recovers the signal into a shape before encoding;
and the error reporting unit is used for reporting all input signals which do not arrive for more than 8 mu s as input signal errors, triggering an error mode by the error reporting unit and outputting a high level to light an error reporting indicator lamp.
10. The isolation test system of a multi-channel digital isolation chip of claim 7, wherein:
the on-chip transformer driving module converts a digital signal into a power signal through the inductance coil, so that the signal is transmitted to the secondary side receiving module, if ENB and EN are both effective, the secondary side receiving module is equivalent to short circuit or open circuit, IN is equivalent to being directly connected to the NMOS driving tube through an inverter, if IN=H, NMOS driving voltage is low level, the grid electrode of the PMOS driving tube is grounded, VOUT is input with high level current, if IN=L, the grid voltage of the NMOS is high voltage, the driving tube of the NMOS is pulled up to VDD, and VOUT outputs large current.
11. A computer readable storage medium having stored thereon a computer program, which when executed, implements a method of isolation testing of a multi-channel digital isolation chip according to any of claims 1-6.
12. An electronic device, comprising:
a memory for storing instructions;
a processor for executing the instructions to cause the apparatus to perform an isolation test method implementing a multi-channel digital isolation chip as claimed in any of claims 1-6.
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