TWI680649B - Decoding method for signal processing circuit and signal processing circuit using the same - Google Patents

Abstract

A decoding method for a signal processing circuit that receives a modulation data carried by a coil signal. The decoding method includes determining a jitter characteristic of the coil signal; when the jitter characteristic appears, obtaining a trigger gap; when When the length of the trigger gap is within a preset range, a gap indication signal is output; it is determined whether a plurality of gap indication signals appear in a first period and the plurality of gap indication signals are scattered in the first period; according to the above judgment result Mark a flag as a dithering signal; within a second period, determine whether the flag is marked as a dithering signal and fill in a value within a time slot corresponding to the second period; and Obtain a data code of the modulation data according to the values filled in the plurality of time grids.

Description

Decoding method for signal processing circuit and signal processing circuit

The present invention relates to a decoding method, and more particularly to a decoding method applicable to a signal processing circuit in an inductive power supply.

In an inductive power supply, in order to operate safely, the supply side needs to confirm that the induction area on its power supply coil is the correct power receiving device, and the power is transmitted only when it can receive power. In order for the power supply end to identify the power receiving end Whether it is the correct power receiving device needs to be identified through data code transmission. The data code is transmitted by the power supply end driving the power supply coil to generate resonance, and sending electromagnetic energy to the power receiving end for power transmission. When the power receiving end receives power, the impedance state on the receiving coil can be changed by signal modulation technology. The feedback affects the change of the resonant carrier signal on the power supply coil to transmit the data code.

In the above-mentioned inductive power supply, because the data code is transmitted between the power supply coil and the power receiving coil, the transmission of the data code is often accompanied by the transmission of power with different strengths, making the data code received by the power supply end vulnerable to the power Noise interference. Therefore, how to effectively interpret data codes under the noise interference of different strengths has become one of the goals that the industry is eager to work on.

Therefore, the main object of the present invention is to provide a decoding method that can be used in a signal processing circuit in an inductive power supply, to effectively obtain the data code corresponding to the coil signal, and to eliminate power noise or other noise interference.

The invention discloses a decoding method for a signal processing circuit. The signal processing circuit receives a modulation data carried by a coil signal. The decoding method includes: receiving the coil signal and determining a jitter characteristic of the coil signal. ; When the jitter characteristic appears at the peak position of one of a plurality of peaks on the coil signal, a trigger gap is obtained; the length of the trigger gap is judged; when the length of the trigger gap is within a preset range, a gap indication signal is output ; Determine whether a plurality of gap indication signals appear in a first period, and determine whether the plurality of gap indication signals are scattered in the first period; based on determining whether the plurality of gap indication signals appear in the first period and determine the A plurality of gaps indicate whether a signal is scattered in the first period, and a flag is marked as a dither signal; in a second period, whether the flag is marked as the dither signal, and based on this Fill in a number in the time grid corresponding to the second period in the plurality of time grids used to judge the modulation data ; And The filled within the plurality of cells plurality of time values, one of the modulation data to obtain data symbols.

The invention further discloses a signal processing circuit for receiving a modulation data carried by a coil signal and decoding the modulation data. The signal processing circuit includes at least a comparator module and a processor. The at least one comparator module can be used to receive the coil signal and determine a jitter characteristic of the coil signal. The processor is coupled to the comparator module and can be used to perform the following steps: when the jitter characteristic appears at one of the peak positions of a plurality of peaks on the coil signal, obtain a trigger gap; determine the length of the trigger gap, when When the length of the trigger gap is within a preset range, a gap indication signal is output; it is determined whether a plurality of gap indication signals appear in a first period, and the complex Whether the plurality of gap indication signals are scattered in the first period; based on a judgment result of determining whether the plurality of gap indication signals appear in the first period and whether the plurality of gap indication signals are scattered in the first period, Mark a flag as a dither signal; within a second period, determine whether the flag is marked as the dither signal and correspondingly correspond to the second in a plurality of time grids used to determine the modulation data A value is filled in one of the time grids during the period; and a data code of the modulation data is obtained according to the plurality of values filled in the plurality of time grids.

1‧‧‧power supply module

110‧‧‧Signal Processing Circuit

111‧‧‧ processor

112, 113‧‧‧ Comparator Module

120‧‧‧ Clock Generator

121, 122‧‧‧ Power supply drive unit

130‧‧‧Divided voltage circuit

131, 132‧‧‧ divided voltage resistor

141, 142‧‧‧Resonant capacitor

151, 153‧‧‧ voltage generating unit

152, 154‧‧‧ Comparator

16‧‧‧Power supply coil

161‧‧‧ magnetic conductor

C1‧‧‧coil signal

20‧‧‧ decoding process

200 ~ 216‧‧‧ steps

CP1, CP2‧‧‧ comparison results

V_P‧‧‧ peak voltage level

V_D‧‧‧ Discrimination voltage level

TMR3‧‧‧ Flag

During P1 ~ P4‧‧‧‧

FIG. 1 is a schematic diagram of a power supply module according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a decoding process according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of judging jitter characteristics to obtain a trigger gap according to an embodiment of the present invention.

4A and 4B are schematic diagrams of recording jitter and triggering gaps through a queue register according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of marking a flag and correspondingly writing a value into a jitter signal queue register according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of judging a start bit and a data code according to an interval of a time grid according to an embodiment of the present invention.

FIG. 7 is a waveform diagram of a coil signal carrying a complete data string according to an embodiment of the present invention.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a power supply module 1 according to an embodiment of the present invention. The power supply module 1 can be used for an inductive power supply, for sending power to the power receiving module of the inductive power supply, and receiving modulation data from the power receiving module. The modulation data can be used to notify the power supply status, adjust the power, etc. Features. The power supply module 1 includes a power supply coil 16 and resonance capacitors 141 and 142. The power supply coil 16 can be used to send electromagnetic energy to the power receiving module for power supply, and the resonance capacitors 141 and 142 are coupled to the power supply coil 16 and can be used with the power supply coil 16 for resonance. In addition, in the power supply module 1, a magnetic conductor 161 made of a magnetic material may be selectively used to improve the electromagnetic induction capability of the power supply coil 16 while avoiding electromagnetic energy from affecting objects in the direction of the non-inductive surface of the coil.

In order to control the operation of the power supply coil 16 and the resonance capacitors 141 and 142, the power supply module 1 further includes a clock generator 120, power supply driving units 121 and 122, a signal processing circuit 110, and a voltage dividing circuit 130. Among them, the clock generator 120 and the power supply driving units 121 and 122 are used to drive the power supply coil 16 to transmit power. The detailed operation mode should be familiar to those skilled in the art and will not be described in detail here. The voltage dividing circuit 130 includes voltage dividing resistors 131 and 132, which can attenuate the coil signal C1 on the power supply coil 16 and output it to the signal processing circuit 110. In some embodiments, if the signal processing circuit 110 has sufficient withstand voltage, the voltage processing circuit 110 may also be used to directly receive the coil signal C1 on the power supply coil 16 without using the voltage dividing circuit 130.

The signal processing circuit 110 can detect the modulation signal on the coil signal C1 and retrieve the modulation data by decoding. Generally, the power supply module 1 and its corresponding power receiving module transmit data through a rated communication method. In one embodiment, encoding can be performed by transmitting an interval time length of a modulation signal, which will be described in detail later. As shown in FIG. 1, the signal processing circuit 110 includes a processor 111 and comparator modules 112 and 113. It should be noted that, in some embodiments, in addition to being used for data interpretation, the processor 111 also has the function of starting the power supply driving units 121 and 122 to output driving signals. Therefore, the setting of the processor 111 can also be independent of the signal processing circuit 110, and is not limited thereto.

Please refer to FIG. 2. FIG. 2 is a schematic diagram of a decoding process 20 according to an embodiment of the present invention. decoding Process 20 can be used for the signal processing circuit in the power supply module of the inductive power supply. The signal processing circuit 110 shown in Figure 1 is used to decode the modulation data from the power receiving end. The modulation data is the coil signal C1. It is carried to the signal processing circuit 110. As shown in FIG. 2, the decoding process 20 includes the following steps: Step 200: Start.

Step 202: Receive the coil signal C1 and determine a jitter characteristic of the coil signal C1.

Step 204: Obtain a trigger gap when the jitter feature appears at the peak position of one of the plurality of peaks on the coil signal C1.

Step 206: Determine the length of the trigger gap. When the length of the trigger gap is within a preset range, a gap indication signal is output.

Step 208: Determine whether a plurality of gap indication signals appear in a first period, and determine whether the plurality of gap indication signals are dispersed in the first period.

Step 210: A flag is marked as a dithering signal according to a judgment result of determining whether a plurality of gap indication signals appear in the first period and whether the plurality of gap indication signals are dispersed in the first period.

Step 212: In a second period, determine whether the flag is marked as a jitter signal, and fill in a value in one of the time slots corresponding to the second period among the plurality of time slots used to determine the modulation data.

Step 214: Obtain one data code of the modulation data according to the plurality of values filled in the plurality of time grids.

Step 216: End.

According to the decoding process 20, the signal processing circuit 110 may first determine a jitter characteristic of the coil signal C1. (Step 202), and then obtain a trigger gap (step 204). In detail, please refer to FIG. 3, which is a schematic diagram of judging jitter characteristics to obtain a trigger gap according to an embodiment of the present invention. FIG. 3 shows a comparison result CP1 of one of the coil signals C1, a comparator module 112, and a comparison result CP2 of one of the comparator modules 113. In detail, the comparator module 112 or 113 is composed of a comparator and a voltage generating unit. The comparator module 112 includes a voltage generating unit 151 and a comparator 152. The comparator module 113 includes a voltage generating unit. 153 and a comparator 154. The comparator module 112 can be used to track the peak voltage of the coil signal C1. Specifically, the processor 111 can output a setting data to the comparator module 112 to control the voltage generating unit 151 to generate a peak voltage level V_P. The comparator 152 can compare the peak voltage level V_P with the coil signal C1. In a coil oscillation cycle, when the peak height of the coil signal C1 exceeds the peak voltage level V_P, a comparison signal CP1 output by the comparator 152 appears a pulse signal (that is, a trigger occurs). In this case, the processor 111 changes to provide Setting data for the voltage generating unit 151 to increase the peak voltage level V_P; in a coil oscillation period, when the peak height of the coil signal C1 is lower than the peak voltage level V_P, the comparison result of the comparator 152 continues to output a low level (Ie, no trigger occurs). In this case, the processor 111 changes the setting data provided to the voltage generating unit 151 to reduce the peak voltage level V_P. In the above manner, the peak voltage level V_P continuously tracks the peak voltage of the coil signal C1, and the comparison result CP1 shows a state of being triggered from time to time without triggering, as shown in FIG. 3.

Then, the processor 111 may reduce the peak voltage level V_P by a predetermined value to obtain a discrimination voltage level V_D, and output related setting data to the voltage generating unit 153 of the comparator module 113 to control the voltage generating unit 153 to generate The voltage level V_D is determined, so that the comparator 154 can compare the voltage level V_D with the coil signal C1. Under normal normal oscillation conditions, since the peak voltage level V_P continues to track the peak voltage of the coil signal C1, it is determined that the voltage level V_D is continuously lower than the peak voltage of the coil signal C1. In this case, the comparison result CP2 triggers in every coil oscillation cycle. However, when the modulation signal or data is received to make the coil signal C1 jitter, the peak voltage will appear larger. If the peak voltage drops below the discrimination voltage level V_D, the comparison result CP2 will have a short-term trigger gap (ie, no trigger signal appears in at least one coil oscillation cycle, as shown in Figure 3).

The processor 111 may further determine the length of the trigger gap, that is, the number of trigger signals that does not appear in the continuous oscillation cycle. Generally speaking, the reception of the modulation signal / data will only produce a short-term fluctuation up and down at the peak of the coil signal C1, so that the length of the trigger gap falls within a certain range. A too long trigger gap may come from changes in coil output power or load, and a too short trigger gap may come from noise interference. In this case, the processor 111 may set a preset range, and determine whether the length of the trigger gap falls within the preset range on each coil oscillation cycle. For example, the processor 111 may set a range of 3 to 5, and when the length of the trigger gap is greater than or equal to the length of three coil oscillation periods and less than or equal to the length of five coil oscillation periods (that is, 3 to 5 consecutive periods) The comparison result of the coil oscillation period CP2 is not triggered), and a gap indication signal is output (step 206).

In an embodiment, the processor 111 can record the state of the jitter and the trigger gap through the queue of the register. The queue register will update the value in each coil oscillation cycle. For example, the latest value will enter the queue. For the smallest bit, each value previously stored on the queue is shifted sequentially to a larger bit, and the value of the largest bit is shifted out of the queue. Please refer to Figs. 4A and 4B. Figs. 4A and 4B are schematic diagrams of recording jitter and triggering gaps through a queue register according to an embodiment of the present invention. Among them, the comparator trigger status queue register is used to record the comparison results CP1 and CP2 output by the comparator modules 112 and 113. Among them, if there is a trigger, it is recorded as 1, and if there is no trigger, it is recorded as 0. As shown in FIG. 4A, when there is no trigger gap, the register corresponding to the comparison result CP2 continues to be 1, so that the gap status queue register is continuously recorded as 0. Figure 4B shows the trigger gap situation. Among them, the minimum bit of the register corresponding to CP2 has 3 consecutive zeros, which represents a trigger gap of length 3. At this time, the above gap information can be transmitted to The gap status queues the register and records 1 as the gap indication signal. In other words, for each coil oscillation period, The processor 111 can start from the minimum bit of the comparator trigger status queue register and determine the number of consecutive zeros. If the number meets the preset range, it can be converted into a gap indication signal and output to the gap status. Column register. Take Figure 4B as an example. If the comparison result CP2 is still no trigger in the next coil oscillation cycle, it means that the corresponding register data is 0. At this time, the trigger gap of length 4 appears in the minimum bit, and the processor 111 judges The length of the trigger gap is within a preset range, and the register 1 is queued in the gap state. In this example, the gap status queue register 1 indicates that there is a trigger gap, and 0 indicates that there is no trigger gap or the trigger gap is too long or too short. In each coil oscillation cycle, the comparator trigger status queue register and the gap status queue register are continuously updated. The queue can indicate the trigger gap status within a period of time.

In the above manner, the processor 111 can record the trigger gap status in a specific period of time in the gap status queue register to determine whether there are multiple gap indication signals in the specific period. At the same time, the processor 111 also determines whether the plurality of gap indication signals are scattered within the specific period (step 208). In detail, the inductive power supply of the present invention is a high-speed system, so the coil oscillation period is very short, that is, the queue register is updated very quickly. Therefore, the upper and lower jitter of the coil signal caused by the modulation signal should span several or dozens of coil oscillation cycles. Correspondingly, the coil signal should include multiple trigger gaps caused by the drop in peak voltage, and the trigger gaps should be distributed in Longer periods (for example, within tens of coil oscillation cycles) rather than focusing on one point in time. In this case, the processor 111 needs to determine whether the gap indication signal is in a dispersed state.

For example, the processor 111 may set a first period, which is approximately equal to the length of the 16 coil oscillation periods, which corresponds to the data of the 16 consecutive gap state queue registers. Then, the first period can be divided into a first sub-period and a second sub-period. For example, the first period can be divided into two, so that the first sub-period corresponds to the first 8 segments of the gap status queue register. Data, second sub-period pair In the gap state, the eight data in the back of the register should be queued. Next, the processor 111 may determine whether a gap indication signal appears in the first sub-period, that is, whether the first 8 pieces of data in the gap status queue register appear 1; and determine whether a gap indication signal appears in the second sub-period, that is, the gap state. Whether the 8 pieces of data in the lower part of the column register appear 1. When the gap indication signal appears in both the first sub-period and the second sub-period, the processor 111 can determine that the gap indication signal is scattered in the first period. Conversely, if the gap indication signal appears in only one of the sub-periods, the processor 111 determines that the gap indication signal is not scattered in the first period.

In another embodiment, the processor 111 may also determine the dispersion of the gap indication signals through other methods, for example, the length of the first period may be modified. In detail, the length of the first period can be set to be equal to the length of the 32 coil oscillation periods and correspond to the data of the 32 consecutive gap state queue registers. In this case, the processor 111 may judge the distribution of the gap indication signal according to the first 16 data and the last 16 data in the gap status queue register.

Further, when the processor 111 determines that a gap indication signal is present in the first period and the gap indication signal is dispersed in the first period, the processor 111 may mark a flag as a jitter signal (step 210). This flag is used to Indicates whether the coil signal C1 has a jitter characteristic over a period of time. In detail, the aforementioned jitter signals and trigger gap records all use the coil oscillation period as the judgment period, that is, new data is inputted for each coil oscillation period. However, the flag is used as the basis for subsequent decoding, and the period of the output signal is set according to the encoding period. In a power supply system with a high-speed signal oscillation, the cycle length of the flag output signal is often greater than the length of the coil oscillation cycle. In one embodiment, the processor 111 may set a jitter signal queue register to record the flag result of the flag. According to the encoding and decoding method, the jitter signal queue register is fixed to input a new data every 0.25 milliseconds (millisecond, ms) to indicate whether the coil signal has a jitter characteristic during this 0.25 millisecond period. In other words, each bit of the jitter signal queue register can correspond to a time grid of 0.25 milliseconds, if the flag is in the corresponding 0.25 millisecond period When marked as a jitter signal, a value of 1 may be filled in the time grid; if the flag is not marked during the corresponding 0.25 millisecond period, a value of 0 may be filled in the time grid (step 212).

Please refer to FIG. 5. FIG. 5 is a schematic diagram of marking a flag TMR3 and correspondingly writing a value into a jitter signal queue register according to an embodiment of the present invention. Figure 5 shows four segments of the jitter signal discrimination period P1 ~ P4, where the length of each segment P1 ~ P4 is equal to 0.25 milliseconds. In this example, the flag TMR3 can be represented by a single bit signal. When the signal is low, it means that the flag TMR3 is not marked, and the marked flag TMR3 is represented by a high potential. During the period of P1, the flag TMR3 is marked as a jitter signal (that is, it rises to a high potential) due to the occurrence of 1 in both the front-stage data and the back-stage data in the gap status queue register. When the P1 period ends, the flag result of the flag TMR3 is written into the jitter signal queue register, that is, the value 1 is filled in the corresponding time grid. At the same time, the flag of the flag TMR3 is cleared and reset to a low potential. For interpretation of subsequent jitter signals. Similarly, at the end of the P2 period, since the flag TMR3 is marked as a dithering signal (ie rising to a high potential), a value of 1 is filled in the corresponding time grid of the dithering signal queue register. Then, at the end of the periods P3 and P4, because the flag TMR3 is not marked as a dithering signal (that is, maintained at a low potential) during the above period, a value of 0 is filled in the corresponding time grid of the dithering signal queue register. In this example, at the end of each period, the marking result of the flag TMR3 is written into the maximum bit of the jitter signal queue register. When new data enters the jitter signal queue register, the queue is queued. Each value previously stored in Uehara is shifted sequentially to the smaller bit, and the value of the smallest bit is shifted out of the queue. This value writing method is opposite to the writing direction for the comparator trigger status queue register and gap status queue register. In fact, those with ordinary knowledge in the field can use the The value is written into the temporary register. The above writing methods can be used interchangeably and should not be limited to this.

It is worth noting that in each period P1 ~ P4, whenever the gap status occurs at any point in time, both the front and back data of the queue register appear 1 and the flag TMR3 is marked as shaking. Signal until the end of the period TMR3 flag is cleared. During the period from when the flag TMR3 is marked to before it is cleared, the flag TMR3 remains in the state of being marked as a jitter signal regardless of whether a gap state occurs in the previous and subsequent data of the queue register. .

It should also be noted that in the inductive power supply system of the present invention, the data period of the jitter signal queue register used for decoding is 0.25 milliseconds, which is a predetermined and fixed time that is encoded with the power receiving end. The data period corresponds. In comparison, the period of the data displacement in the comparator trigger state queue register and the gap state queue register corresponds to the coil oscillation period. In general, the coil oscillation period is offset according to the load size and coil power, and its operating frequency is about 100 仟 Hertz (kHz), that is, the period is about 0.01 milliseconds. In this case, each time the data is output to the jitter signal queue register, it has experienced about 25 judgments of the jitter signal, but the number of judgments will change depending on the coil oscillation cycle / operation frequency.

In an embodiment, the processor 111 may know the period during which the modulation signal / data may occur according to the system setting, and perform the reading within the period, and the reading of the modulation data is suspended during other periods to save its computing resources. In an embodiment, according to the communication specification of the inductive power supply system, the power receiving end transmits one byte of data every 50 milliseconds, together with a start bit and a parity check code. In this case, if within a 50 millisecond period, if the processor 111 judges that one byte of data, the start bit, and the parity check code have been received, the data interpretation operation may be suspended until the next 50 millisecond period. Interpretation.

In this example, the bit data can be transmitted as shown in Table 1:

It can be known from the above that the data period of the jitter signal queue register is 0.25 milliseconds, that is, each time division is 0.25 milliseconds. Therefore, the time lengths of the different data codes can correspond to each other according to the manner in Table 1. In this case, the minimum time length of a complete data string (including a byte of data, a start bit and parity check code) is 21.25 milliseconds (including 8 bit 0 and parity check code 0), the longest The time length is 29.25 milliseconds (including 8 bit 1 and parity check code 0, taking the parity as an example). The processor 111 can obtain the data code of the modulation data according to the value filled in each time grid (step 214). In detail, the processor 111 may take one of the first time grid filled with 1 and the next with one time grid filled with 1, and calculate the interval between the first time grid and the second time grid to determine whether the interval is The bit length of the data code is matched, and the data code is obtained according to the interval size. For example, when the interval size of the time grid is 8, it can be judged that the data code is 0; when the interval size of the time grid is 12, it can be judged that the data code is 1.

Please refer to FIG. 6, which is a schematic diagram of judging a start bit and a data code according to an interval of a time grid according to an embodiment of the present invention. As shown in Fig. 6, each time grid can be sequentially filled with the value of the jitter signal queue register according to the aforementioned flag TMR3, and its number is 0 ~ 31. First, the processor 111 first determines whether a start bit appears, that is, whether the time divisions of the numbers 0 and 10 are filled with the value 1. For example, the processor 111 may determine whether the position of the interval of 10 time intervals is the value 1 after filling the value 1 in a time division. If yes, it is determined that the start bit is received. In addition to the start bit, it can be used to determine whether the data code has started to be transmitted. It can also be used to define the time correspondence of the data code. That is, the processor 111 can The time grid position of the start bit is used to determine the position in the jitter signal queue register that may be filled with the value 1. Taking Figure 6 as an example, the time grids of numbers 0 and 10 have defined the position of the starting bit. Therefore, the time grids of numbers 18, 22, 26, and 30 are positions that may be filled with the value 1. If a data code is 0, the time grid of number 18 is the value 1. If the first data code is 1, the time grid of number 22 is the value 1. In an embodiment, the processor 111 may fetch the value of each time division for subsequent reading. Alternatively, the processor 111 may only extract the time grid that may be filled with the value 1 and / or its adjacent time grid for subsequent interpretation to save computing resources. The value 1 filled in the remaining time grids does not conform to the encoding mechanism. , Which must be caused by noise, negligible. Finally, the processor 111 can judge the parity check code according to the interval of the time grid to complete the judgment of a set of modulation data.

It is worth noting that finding the trigger gap from the comparator module to determine the jitter signal on the coil, and then writing the relevant information of the jitter signal into the jitter signal queue register does not work perfectly. For example, the modulation of the receiving end will generate a period of jitter on the power supply coil, and the corresponding jitter signal may have a time offset, so it appears in advance or delay to the adjacent time grid. Or, when the signal quality is good, the jitter signal is maintained for a long time. If the jitter signal is not synchronized with the detection period of the time grid, a value of 1 may be entered in two consecutive time grids. Case. Therefore, in addition to judging the time grid that may be filled with the value 1, the processor 111 also judges the adjacent time grid at the same time, so as to respond to the above-mentioned jitter signal shift or extension.

In an embodiment, the processor 111 may take the number of the time slot filled with the value 1 in the time slot and the adjacent time slot where the value 1 may be filled in, and fill it into a jittering time slot sequence PIN. , As shown in Table 2:

In Table 2, the jitter time grid sequence PIN_01 ~ PIN_18 represents a time grid number that is filled with a value of 1 when a jitter signal is detected in a sequence of time grids. The numbering is the same as that in Figure 6 and includes the figure. Subsequent extensions. The jitter time grid intervals GAP_01 ~ GAP_18 are recorded separately Jitter time grid sequence PIN_01 ~ PIN_18 interval between two adjacent time grids, for example, GAP_01 records the interval between PIN_01 and the start bit end time (time grid number 10), GAP_02 records the interval between PIN_02 and PIN_01 , GAP_03 records the interval between PIN_03 and PIN_02, and so on.

Then, the processor 111 may perform decoding according to the values recorded in the jitter time interval GAP_01 ~ GAP_18. As described above (see Table 1), bit 0 and bit 1 correspond to time interval 8 and 12, respectively, and can be decoded accordingly. First, GAP_01 is equal to 8, which means that the first bit is 0. GAP_02 is equal to 1, which means that the first bit crosses the adjacent time grid, and then it is judged that GAP_03 is equal to 7, plus the part where the first bit crosses, we can see that GAP_02 + GAP_03 = 8, which means that the second bit is 0. GAP_04 is equal to 1, which means that the second bit also crosses the adjacent time grid, and then judges that GAP_05 is equal to 11, plus the part where the second bit crosses, we can see that GAP_04 + GAP_05 = 12, which means that the third bit is 1. By analogy, one-byte modulation data can be obtained as "00110101". Then, the processor 111 can determine the parity check code. Since GAP_16 is equal to 1 and GAP_17 is equal to 10, GAP_16 + GAP_17 = 11, which means that the parity check code is 0. According to the encoding of the parity check, it can be known that the data of this byte is correct, and the processor 111 further receives this modulation data for subsequent processing. After the modulation data is received, the processor 111 may clear the content recorded in the jitter time grid sequence PIN_01 ~ PIN_18 and the jitter time grid interval GAP_01 ~ GAP_18 for subsequent data code processing.

It can be known from the above that according to the coding specifications, bit 0 and bit 1 can be defined to correspond to time grid intervals 8 and 12, respectively, and time grid intervals 7 and 11 are permissible errors, which can be processed correctly according to the above-mentioned complement method. coding. In another embodiment, a time grid interval of 9 or 13 may also occur, and the time grid interval may also be adjusted to 8 or 12 in a similar manner, so as to determine the data code.

Therefore, each complete data string (including a byte of data, a start bit, and Bit check code) transmission contains 11 jitter characteristics, as shown in Figure 7. Figure 7 shows the waveform of the coil signal C1 with the complete data string. After analyzing and marking each jitter feature, at least 11 different time grids (and their adjacent time grids) are recorded respectively, and then 10 sets of time grids are generated. For the interval data, the processor 111 can judge the value of the data code accordingly and determine whether the data code is correct through the parity check code.

It is worth noting that the object of the present invention is to provide a data decoding method that can be used in an inductive power supply, which can decode the modulation data entrained on the coil signal. Those skilled in the art can make modifications or changes based on this, without being limited thereto. For example, the foregoing encoding method is only an exemplary embodiment. The decoding method of the present invention can also be applied to different data code architectures, such as using different time lengths to define the encoding, or multiple bits can be transmitted in a complete data string. The data code of the group is not limited to this. In addition, the decoding method of the present invention can be used in various data transmission systems that encode by time, and is not limited to the modulation data transmission of the aforementioned inductive power supply. In addition, those with ordinary knowledge in the art should understand that the aforementioned various numerical values, bit values, numbers and other settings are only one of many embodiments of the present invention, and the defined numbers can be adjusted according to system requirements.

In summary, the present invention provides a decoding method that can be used in a signal processing circuit in an inductive power supply to decode the modulation data received by the power supply module. The modulation data / signal received by the power supply module will cause jitter on the power supply coil to generate a trigger gap during the detection process of the comparator module. According to the number of consecutively triggered trigger gaps, gap indication signals can be generated. The processor determines whether the gap indication signals are dispersed over a period of time to ensure that the gap is caused by the jitter of the modulation signal, and then input the jitter signal through the flag mark. Enter the value 1 in the corresponding time box of the jitter signal queue register. Then, the processor can take out the position or number of the time grid filled with the value 1, and judge the bit value of the data code through its interval. Through the multi-level decoding method of the present invention, even under the interference of power noise, correct modulation data can be effectively taken out.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the present invention.

Claims (20)

A decoding method is used for a signal processing circuit. The signal processing circuit receives a modulation data carried by a coil signal. The decoding method includes: receiving the coil signal and determining a jitter characteristic of the coil signal; when the When the jitter characteristic appears at the peak position of one of a plurality of peaks on the coil signal, a trigger gap is obtained; the length of the trigger gap is determined; when the length of the trigger gap is within a preset range, a gap indication signal is output; Whether a plurality of gap indication signals appear in the first period, and determine whether the plurality of gap indication signals are dispersed in the first period; based on determining whether the plurality of gap indication signals appear in the first period and determining the plurality of gaps A judgment result indicating whether the signal is scattered in the first period, and a flag is marked as a dither signal; in a second period, it is determined whether the flag is marked as the dither signal, and is used in the Judging that a plurality of time grids of the modulation data corresponds to a time grid corresponding to the second period; and a root value; and Fill the grid within the plurality of time a plurality of values, has made one of the modulation data information code. The decoding method according to claim 1, wherein the coil signal is received, and the jitter characteristic of the coil signal is judged, and the trigger is obtained when the jitter characteristic appears at the peak position of the plurality of peaks on the coil signal. The step of notch includes: setting a peak voltage level to track the peak voltages of the plurality of peaks; lowering the peak voltage level by a predetermined value to obtain a discrimination voltage level; comparing the discrimination voltage level with The coil signal; and when a peak voltage of one of the plurality of peaks is detected to be less than the discrimination voltage level, it is determined that a trigger gap occurs. The decoding method according to claim 1, wherein the first period is divided into a first sub period and a second sub period, and the step of determining whether the plurality of gap indication signals are dispersed in the first period includes: : Determine whether the gap indication signal appears in the first sub-period; determine whether the gap indication signal appears in the second sub-period; and when the gap indication signal appears in both the first sub-period and the second sub-period , Determine that the plurality of gap indication signals are scattered in the first period. The decoding method according to claim 1, wherein according to the judgment result of determining whether the plurality of gap indication signals appear in the first period and whether the plurality of gap indication signals are scattered in the first period, the flag The step of marking the jitter signal includes: when the plurality of gap indication signals appear in the first period and the plurality of gap indication signals are dispersed within the first period, marking the flag as the jitter signal. The decoding method according to claim 1, wherein in the second period, it is judged whether the flag is marked as the jitter signal, and corresponding to the plurality of time divisions used to judge the modulation data corresponding to the The step of filling the value in the time grid of the second period includes: when the flag is marked as the jitter signal, filling in a first value in the time grid corresponding to the second period; and when When the flag is not marked as the jitter signal, a second value is filled in the time grid corresponding to the second period. The decoding method according to claim 5, wherein the step of obtaining the data code of the modulation data according to the plurality of values filled in the plurality of time slots includes: taking out and filling in the plurality of time slots One of the first time grid of the first value and one of the second time grid filled with the first value; calculate the interval between the first time grid and the second time grid to determine whether the interval meets the data A bit length of the code; and obtaining the data code according to the size of the interval. The decoding method according to claim 6, further comprising: determining at least one of a start bit and a parity check code of the modulation data according to the interval. The decoding method according to claim 7, further comprising: obtaining the starting bit of the modulation data, a data code of one byte, and the parity check code within a third period. The decoding method according to claim 8, wherein the third period is equal to 50 ms and the second period is equal to 0.25 ms. The decoding method according to claim 1, further comprising: at the end of the second period, if the flag is marked as the jitter signal, clearing the flag of the flag. A signal processing circuit is used for receiving and decoding a modulation data carried by a coil signal. The signal processing circuit includes: at least one comparator module for receiving the coil signal and determining A jitter characteristic of the coil signal; and a processor coupled to the comparator module, the processor is configured to perform the following steps: when the jitter characteristic appears at a peak position of one of a plurality of peaks on the coil signal, obtain A trigger gap; determine the length of the trigger gap; when the length of the trigger gap is within a preset range, output a gap indication signal; determine whether a plurality of gap indication signals appear in a first period, and determine the plurality of gaps Whether the indication signal is scattered in the first period; according to a judgment result of determining whether the plurality of gap indication signals appear in the first period and whether the plurality of gap indication signals are scattered in the first period, a flag The tag is marked as a dither signal; within a second period, it is determined whether the flag is marked as the dither signal, and according to Fill in a value in the time grid corresponding to the second period in the plurality of time grids used to judge the modulation data; and obtain one of the modulation data according to the plurality of values filled in the plurality of time grids Data code. The signal processing circuit according to claim 11, wherein the comparator module includes a first comparator module and a second comparator module, wherein the first comparator module and the second comparator module The group and the processor execute the following steps to receive the coil signal and determine the jitter characteristic of the coil signal, and then obtain the trigger gap when the jitter characteristic appears at the peak position of the plurality of peaks on the coil signal: The processor sets a peak voltage level so that the first comparator module is used to track the peak voltages of the plurality of peaks; the processor reduces the peak voltage level by a predetermined value to obtain a discriminating voltage level The second comparator module compares the discrimination voltage level with the coil signal; and when the second comparator module detects that the peak voltage of one of the plurality of peaks is less than the discrimination voltage level, the The processor determines that a trigger gap has occurred. The signal processing circuit according to claim 11, wherein the first period is divided into a first sub period and a second sub period, and the processor executes the following steps to determine whether the plurality of gap indicating signals are scattered in In the first period: determine whether the gap indication signal appears in the first sub-period; determine whether the gap indication signal appears in the second sub-period; and when both the first sub-period and the second sub-period appear When the gap indication signal is judged, the plurality of gap indication signals are scattered in the first period. The signal processing circuit according to claim 11, wherein the processor executes the following steps to determine whether the plurality of gap indication signals appear in the first period and whether the plurality of gap indication signals are dispersed in the first period. The judgment result in the flag marks the jitter signal: when the plurality of gap indication signals appear in the first period and the plurality of gap indication signals are dispersed in the first period, the flag is marked Is the jitter signal. The signal processing circuit according to claim 11, wherein the processor executes the following steps to determine whether the flag is marked as the jitter signal during the second period, and is used to determine the modulation data. Fill in the value in the time grid corresponding to the second period in the plurality of time grids: when the flag is marked as the jitter signal, fill in a first number in the time grid corresponding to the second period A value; and when the flag is not marked as the dither signal, a second value is filled in the time grid corresponding to the second period. The signal processing circuit according to claim 15, wherein the processor executes the following steps to obtain the data code of the modulation data according to the plurality of values filled in the plurality of time divisions: in the plurality of time divisions Take out a first time cell filled in with the first value and a second time cell filled in with the first value; calculate the interval between the first time cell and the second time cell to determine the Whether the interval matches a bit length of the data code; and obtaining the data code according to the size of the interval. The signal processing circuit according to claim 16, wherein the processor further performs the following steps: judging at least one of a start bit and a parity check code of the modulation data according to the interval. The signal processing circuit according to claim 17, wherein the processor further performs the following steps: in a third period, obtaining the starting bit of the modulation data, a byte data code, and the parity check code. The signal processing circuit according to claim 18, wherein the third period is equal to 50 ms and the second period is equal to 0.25 ms. The signal processing circuit according to claim 11, wherein the processor further performs the following steps: at the end of the second period, if the flag is marked as the dither signal, the flag of the flag is cleared.