CN109586734B

CN109586734B - Decoding method for signal processing circuit and signal processing circuit thereof

Info

Publication number: CN109586734B
Application number: CN201811196022.4A
Authority: CN
Inventors: 蔡明球; 詹其哲
Original assignee: Fu Da Tong Technology Co Ltd
Current assignee: Fu Da Tong Technology Co Ltd
Priority date: 2018-08-30
Filing date: 2018-10-15
Publication date: 2022-11-25
Anticipated expiration: 2038-10-15
Also published as: TW201842736A; TWI680649B; CN109586734A

Abstract

The invention discloses a decoding method for a signal processing circuit and the signal processing circuit thereof, the signal processing circuit receives a modulation data carried by a coil signal, the decoding method comprises judging a jitter characteristic of the coil signal; when the jitter characteristic appears, a trigger gap is obtained; when the length of the trigger gap is within a preset range, outputting a gap indication signal; judging whether a plurality of gap indication signals appear in a first period and are dispersed in the first period; marking a mark as a jitter signal according to the judgment result; judging whether the mark is marked as a jitter signal in a second period, and filling a numerical value in a time slot corresponding to the second period according to the judgment; and acquiring a data code of the modulation data according to the numerical values filled in the time grids.

Description

Decoding method for signal processing circuit and signal processing circuit thereof

Technical Field

The present invention relates to a decoding method, and more particularly, to a decoding method for a signal processing circuit in an inductive power supply.

Background

In an inductive power supply, for safe operation, the power supply end needs to confirm that the inductive area on the power supply coil is the correct power receiving device, and power transmission is performed only in a condition that power can be received. The transmission of the data code can drive the power supply coil to generate resonance through the power supply end, the electromagnetic energy is transmitted to the power receiving end to carry out power transmission, when the power receiving end receives power, the impedance state on the receiving coil can be changed through a signal modulation technology, and the resonance carrier signal on the power supply coil is influenced through feedback to change so as to transmit the data code.

In the above-mentioned inductive power supply, since the data code is transmitted between the power supply coil and the power receiving coil, the transmission of the data code is often accompanied by power transmission with different intensities, so that the data code received by the power supply terminal is susceptible to interference of power supply noise. Therefore, how to effectively interpret the data codes under the noise interferences with different intensities has become one of the goals of the urgent efforts in the industry.

Disclosure of Invention

Therefore, it is a primary objective of the present invention to provide a decoding method for a signal processing circuit in an inductive power supply, so as to effectively obtain a data code corresponding to a coil signal and eliminate interference of power noise or other noises.

The invention discloses a decoding method, which is used for a signal processing circuit, the signal processing circuit receives a modulation data carried by a coil signal, and the decoding method comprises the following steps: receiving the coil signal and judging a jitter characteristic of the coil signal; when the jitter characteristic appears at a peak position of a plurality of peaks on the coil signal, obtaining a trigger notch; judging the length of the trigger gap, and outputting a gap indication signal when the length of the trigger gap is within a preset range; judging whether a plurality of gap indication signals appear in a first period, and judging whether the plurality of gap indication signals are dispersed in the first period; marking a mark as a jitter signal according to a judgment result of judging whether the plurality of notch indicating signals appear in the first period and judging whether the plurality of notch indicating signals are dispersed in the first period; judging whether the mark is marked as the jitter signal or not in a second period, and filling a value in a time slot corresponding to the second period in a plurality of time slots for judging the modulation data according to the judgment; and obtaining a data code of the modulation data according to the numerical values filled in the time grids.

The invention also discloses a signal processing circuit, which is used for receiving the modulation data carried by a coil signal and decoding the modulation data, and the signal processing circuit comprises at least one comparator module and a processor. The at least one comparator module can be used for receiving the coil signal and judging a jitter characteristic of the coil signal. The processor is coupled to the comparator module and is configured to perform the following steps: when the jitter characteristic appears at a peak position of a plurality of peaks on the coil signal, obtaining a trigger notch; judging the length of the trigger gap, and outputting a gap indication signal when the length of the trigger gap is within a preset range; judging whether a plurality of gap indication signals appear in a first period, and judging whether the plurality of gap indication signals are dispersed in the first period; marking a mark as a jitter signal according to a judgment result of judging whether the plurality of notch indicating signals appear in the first period and judging whether the plurality of notch indicating signals are dispersed in the first period; judging whether the mark is marked as the jitter signal or not in a second period, and filling a value in a time slot corresponding to the second period in a plurality of time slots for judging the modulation data according to the judgment; and obtaining a data code of the modulation data according to the numerical values filled in the time grids.

Drawings

Fig. 1 is a schematic diagram of a power supply module according to an embodiment of the invention.

FIG. 2 is a diagram illustrating a decoding process according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating determining jitter characteristics to obtain a trigger gap according to an embodiment of the present invention.

Fig. 4A and 4B are schematic diagrams illustrating recording jitter and trigger gaps through a queue register according to an embodiment of the invention.

FIG. 5 is a diagram illustrating an embodiment of marking a flag and writing a value into a jitter queue register.

FIG. 6 is a diagram illustrating an embodiment of determining start bits and data codes according to a time interval.

FIG. 7 is a waveform diagram of a coil signal carrying a complete data string according to an embodiment of the present invention.

Wherein the reference numerals are as follows:

1. power supply module

110. Signal processing circuit

111. Processor with a memory for storing a plurality of data

112. 113 comparator module

120. Clock generator

121. 122 power supply driving unit

130. Voltage divider circuit

131. 132 voltage dividing resistor

141. 142 resonance capacitance

151. 153 voltage generating unit

152. 154 comparator

16. Power supply coil

161. Magnetic conductor

C1 Coil signal

20. Decoding process

200 to 216 steps

CP1, CP2 comparison result

V _ P Peak Voltage level

V _ D discrimination Voltage level

TMR3 sign

During periods P1 to P4

Detailed Description

Referring to fig. 1, fig. 1 is a schematic diagram of a power supply module 1 according to an embodiment of the invention. The power supply module 1 may be used in an inductive power supply, and is configured to send power to a power receiving module of the inductive power supply, and receive modulation data from the power receiving module, where the modulation data may be used to inform a power supply status, adjust power, and so on. The power supply module 1 includes a power supply coil 16 and

resonant capacitors

141 and 142. The power supply coil 16 can be used for sending electromagnetic energy to the power receiving module for supplying power, and the

resonant capacitors

141 and 142 are coupled to the power supply coil 16 and can be used for cooperating with the power supply coil 16 for resonance. In addition, in the power supply module 1, a magnetic conductor 161 made of magnetic material can be selectively used to enhance the electromagnetic induction capability of the power supply coil 16, and at the same time, to prevent the electromagnetic energy from affecting objects in the direction of the non-inductive surface of the coil.

In order to control the operations of the power supply coil 16 and the

resonant capacitors

141, 142, the power supply module 1 further includes a clock generator 120, power

supply driving units

121 and 122, a signal processing circuit 110, and a voltage divider circuit 130. The clock generator 120 and the power

supply driving units

121 and 122 are used to drive the power supply coil 16 to send power, and the detailed operation thereof is well known to those skilled in the art and will not be described herein. The voltage dividing circuit 130 includes

voltage dividing resistors

131 and 132, which attenuate the coil signal C1 on the power supply coil 16 and output the attenuated signal to the signal processing circuit 110. In some embodiments, if the signal processing circuit 110 has a sufficient withstand voltage, the coil signal C1 of the power supply coil 16 may be directly received by the signal processing circuit 110 without using the voltage dividing circuit 130.

The signal processing circuit 110 can detect the modulation signal on the coil signal C1 and extract the modulation data by decoding. Generally, the power module 1 and the corresponding power receiving module transmit data in a rated communication manner, and in one embodiment, the data is encoded by a time interval length of transmitting a modulation signal, which will be described in detail later. As shown in fig. 1, the signal processing circuit 110 includes a processor 111 and

comparator modules

112 and 113. It should be noted that in some embodiments, the processor 111 is also capable of starting the power

supply driving units

121 and 122 to output driving signals, in addition to being used for data reading. Therefore, the processor 111 may be provided independently of the signal processing circuit 110, without being limited thereto.

Referring to fig. 2, fig. 2 is a schematic diagram of a decoding process 20 according to an embodiment of the invention. The decoding process 20 can be applied to a signal processing circuit in a power supply module of an inductive power supply, such as the signal processing circuit 110 shown in fig. 1, for decoding modulated data from a power receiving end, where the modulated data is carried by the coil signal C1 and transmitted to the signal processing circuit 110. As shown in fig. 2, the decoding process 20 includes the following steps:

step 200: and starting.

Step 202: the coil signal C1 is received, and a jitter (jitter) characteristic of the coil signal C1 is determined.

Step 204: when the jitter characteristic appears at a peak position of a plurality of peaks on the coil signal C1, a trigger notch is obtained.

Step 206: and judging the length of the trigger gap, and outputting a gap indication signal when the length of the trigger gap is within a preset range.

Step 208: whether a plurality of gap indication signals appear in a first period is judged, and whether the plurality of gap indication signals are dispersed in the first period is judged.

Step 210: according to a judgment result of judging whether a plurality of gap indication signals appear in the first period and judging whether the plurality of gap indication signals are dispersed in the first period, a mark is marked as a jitter signal.

Step 212: during a second period, it is determined whether the flag is marked as a wobble signal, and a time bin corresponding to the second period among a plurality of time bins for determining the modulated data is filled with a value accordingly.

Step 214: according to the values filled in the time grids, a data code of the modulation data is obtained.

Step 216: and (6) ending.

According to the decoding process 20, the signal processing circuit 110 can first determine a jitter characteristic of the coil signal C1 (step 202), and further obtain the trigger gap (step 204). In detail, referring to fig. 3, fig. 3 is a schematic diagram illustrating determining jitter characteristics to obtain a trigger gap according to an embodiment of the present invention. Fig. 3 shows the coil signal C1, a comparison result CP1 of the comparator module 112, and a comparison result CP2 of the comparator module 113. In detail, the

comparator module

112 or 113 is composed of a comparator and a voltage generating unit, the comparator module 112 includes a voltage generating unit 151 and a comparator 152, and the comparator module 113 includes a voltage generating unit 153 and a comparator 154. The comparator module 112 is configured to track a peak voltage of the coil signal C1, and in detail, the processor 111 may output a setting data to the comparator module 112 to control the voltage generating unit 151 to generate a peak voltage level V _ P, so that the comparator 152 may compare the peak voltage level V _ P with the coil signal C1. In a coil oscillation period, when the peak height of the coil signal C1 exceeds the peak voltage level V _ P, the comparison result CP1 output by the comparator 152 appears as a pulse signal (i.e., a trigger occurs), in which case the processor 111 changes the setting data supplied to the voltage generating unit 151 to raise the peak voltage level V _ P; in a coil oscillation period, when the peak height of the coil signal C1 is lower than the peak voltage level V _ P, the comparison result of the comparator 152 continuously outputs a low level (i.e., no trigger occurs), in which case the processor 111 changes the setting data supplied to the voltage generating unit 151 to lower the peak voltage level V _ P. In this way, the peak voltage level V _ P is continuously tracked to the peak voltage of the coil signal C1, and the comparison result CP1 is shown in a state of being triggered but not triggered, as shown in fig. 3.

Next, the processor 111 may decrease the peak voltage level V _ P by a predetermined value to obtain a determination voltage level V _ D, and output related setting data to the voltage generating unit 153 of the comparator module 113 to control the voltage generating unit 153 to generate the determination voltage level V _ D, so that the comparator 154 may compare the determination voltage level V _ D with the coil signal C1. In the case of normal oscillation, the peak voltage level V _ P continuously tracks the peak voltage of the coil signal C1, and therefore the determination voltage level V _ D continuously falls below the peak voltage of the coil signal C1. In this case, the comparison result CP2 is triggered at each coil oscillation period. However, when the coil signal C1 is jittered by receiving the modulation signal or the data, the peak voltage is greatly decreased, and if the peak voltage is decreased to be less than the determination voltage level V _ D, the comparison result CP2 has a short trigger gap (i.e. at least one coil oscillation period has no trigger signal, as shown in fig. 3).

The processor 111 may further determine the length of the trigger gap, i.e. the number of trigger signals that do not occur in consecutive oscillation cycles. Generally, the reception of the modulation signal/data will only produce a short up-and-down fluctuation in the peak value of the coil signal C1, so that the length of the trigger gap falls within a certain range. Too long a triggering gap may result from a change in coil output power or load, and too short a triggering gap may result from noise interference. In this case, the processor 111 may set a predetermined range, and determine whether the length of the trigger gap falls within the predetermined range in each coil oscillation period. For example, the processor 111 may set a range of 3 to 5, and output a gap indication signal when the length of the trigger gap is greater than or equal to the length of three coil oscillation periods and less than or equal to the length of five coil oscillation periods (i.e. the comparison result CP2 is not triggered in 3 to 5 consecutive coil oscillation periods) (step 206).

In one embodiment, the processor 111 may record the jitter and trigger gap status through a queue of registers that update values each coil oscillation cycle, for example, the latest value enters the least significant bit of the queue, each value originally stored on the queue is sequentially shifted to a greater bit, and the greatest value is shifted out of the queue. Referring to fig. 4A and 4B, fig. 4A and 4B are schematic diagrams illustrating recording jitter and trigger gaps through a queue register according to an embodiment of the present invention. The comparator trigger state queue register is used to record the comparison results CP1 and CP2 output by the

comparator modules

112 and 113, where a trigger is marked as 1 and no trigger is marked as 0. As shown in fig. 4A, when there is no trigger gap, the register corresponding to the comparison result CP2 is continuously 1, so that the gap state queue register is continuously marked as 0. Fig. 4B shows the case of existence of a trigger gap, in which the minimum bit of the register corresponding to the comparison result CP2 has 3 consecutive 0 s, which represents a trigger gap with a length of 3, and at this time, the gap information may be transmitted to the gap status queue register, and record 1 as the gap indication signal. In other words, for each coil oscillation period, the processor 111 may determine the number of consecutive 0 s starting from the minimum bit of the comparator trigger status queue register, and if the number meets the predetermined range, convert the number into the gap indication signal and output the gap indication signal to the gap status queue register. Taking fig. 4B as an example, if the comparison result CP2 in the next coil oscillation period is still no trigger, which indicates that the corresponding register data is 0, at this time, a trigger gap with a length of 4 appears in the minimum bit, and the processor 111 determines that the length of the trigger gap is within the preset range, and further records 1 in the gap state queue register. In this example, a 1 recorded in the gap status queue register represents that there is a trigger gap, and a 0 represents that there is no trigger gap or the length of the trigger gap is too long or too short. During each coil oscillation cycle, the comparator trigger state queue register and the gap state queue register both continuously update values, which queue may indicate the trigger gap state over a period of time.

In this way, the processor 111 may record the trigger gap state in the gap state queue register for a certain period of time to determine whether a plurality of gap indication signals are present in the certain period of time. At the same time, the processor 111 also determines whether the plurality of gap indication signals are scattered in the specific period (step 208). In detail, the inductive power supply of the present invention is a high-speed system, so the oscillation period of the coil is very short, i.e. the queue register is updated very fast. Therefore, the up-and-down jitter of the coil signal caused by the modulation signal should span several or tens of oscillation cycles of the coil, and correspondingly, the coil signal should include a plurality of trigger gaps caused by the peak voltage drop, and the trigger gaps should be distributed in a longer period (for example, within tens of oscillation cycles of the coil) rather than being concentrated at a time point. In this case, the processor 111 needs to determine whether the gap indication signal is in a scattered state.

For example, the processor 111 may set a first period substantially equal to the length of 16 coil oscillation periods, which corresponds to the data of 16 consecutive gap state queue registers. Then, the first period can be divided into a first sub-period and a second sub-period, for example, the first period can be divided into two, so that the first sub-period corresponds to the front section 8 data of the gap status queue register, and the second sub-period corresponds to the rear section 8 data of the gap status queue register. Then, the processor 111 may determine whether a gap indication signal appears in the first sub-period, that is, whether 1 appears in the front segment 8 data of the gap status queue register; and judging whether a gap indication signal appears in the second sub-period, namely whether 1 appears in the rear section 8 data of the gap state queue register. When the gap indication signal occurs in both the first sub-period and the second sub-period, the processor 111 can determine that the gap indication signal is scattered in the first period. On the contrary, if the gap indication signal appears in only one of the sub-periods, the processor 111 determines that the gap indication signal is not dispersed in the first period.

In another embodiment, the processor 111 may also determine the gap indicator signal dispersion by other means, such as modifying the length of the first period. In detail, the first period length may be set equal to the length of 32 coil oscillation periods and corresponds to data of consecutive 32 gap state queue registers. In this case, the processor 111 can determine the distribution of the gap indication signal according to the first 16 data and the last 16 data in the gap status queue register.

Further, when the processor 111 determines that the gap indication signal occurs in the first period and the gap indication signal is dispersed in the first period, the processor 111 may mark a flag as the jitter signal (step 210), where the flag is used to indicate whether the coil signal C1 has a jitter characteristic in a period. In detail, the recording of the jitter signal and the trigger gap takes the coil oscillation period as the determination period, i.e. new data is input every coil oscillation period. However, the flag is used as the basis for the subsequent decoding, and the period of the output signal is set according to the encoding period. In a power supply system in which a signal oscillates at a high speed, the period length of a flag output signal is often longer than the length of the oscillation period of the coil. In one embodiment, the processor 111 may set a jitter queue register for recording the marked result of the flag. According to the encoding and decoding method, the jitter signal queue register is fixed to input a new data every 0.25 milliseconds (ms) for indicating whether the jitter characteristic occurs in the coil signal during the 0.25 ms period. That is, each bit of the jitter queue register may correspond to a time bin of 0.25 ms, which may be filled with a value of 1 if the flag is marked as a jitter signal during the corresponding 0.25 ms; if the flag is not marked during the corresponding 0.25 ms, the time bin may be filled with a value of 0 (step 212).

Referring to fig. 5, fig. 5 is a schematic diagram illustrating an embodiment of the present invention for marking a mark TMR3 and writing a value into a jitter signal queue register. Fig. 5 shows 4 jitter signal discrimination periods P1 to P4, where each period P1 to P4 is equal to 0.25 ms in length. In this case, the flag TMR3 may be represented by a one-bit signal, which indicates that the flag TMR3 is unmarked when the signal is low, and the marked flag TMR3 is represented by high. During the period P1, since the notch state queue register has a condition that 1 appears in both the preceding data and the succeeding data, the flag TMR3 is marked as a dither signal (i.e., raised to a high potential). When the period P1 ends, the mark result of the mark TMR3 is written into the jitter signal queue register, i.e. the corresponding time bin is filled with the value 1, and at the same time, the mark of the mark TMR3 is cleared and reset to low potential for the interpretation of the subsequent jitter signal. Similarly, at the end of the period P2, the flag TMR3 is marked as the jitter signal (i.e. rising to high), and the corresponding time bin of the jitter signal queue register is filled with the value 1. Next, at the end of the periods P3 and P4, since the flag TMR3 is not marked as the jitter signal (i.e. maintained at the low voltage level) in the above period, the corresponding time bin of the jitter signal queue register is filled with the value 0. In this example, at the end of each segment period, the flag result for flag TMR3 is written into the maximum bit of the jitter signal queue register, and each value originally stored on the queue is sequentially shifted to a smaller bit and the minimum bit value is shifted out of the queue each time new data enters the jitter signal queue register. The writing of the value is opposite to the writing of the comparator trigger status queue register and the gap status queue register, and in fact, the skilled person can write the value into the register in a preferable way according to the system requirement, and the writing ways can be used alternatively and should not be limited to these.

Note that, in each of the segment periods P1 to P4, as long as 1 appears in both the preceding segment data and the succeeding segment data of the notch state queue register at any point in time, the flag TMR3 is marked as a dither signal until the flag of the end flag TMR3 of the segment period is cleared. During the period from when flag TMR3 is marked to before it is cleared, flag TMR3 is maintained in the state marked as a dither signal regardless of whether or not the occurrence of 1 in both the preceding stage data and the following stage data of the notch state queue register occurs.

It should be noted that, in the inductive power supply system of the present invention, the data cycle of the jitter signal queue register for decoding is 0.25 ms, which is a predetermined and fixed time corresponding to the data cycle of the power receiving end for encoding. In contrast, the period of data displacement in the comparator trigger state queue register and the gap state queue register corresponds to the coil oscillation period. In general, the coil oscillation period shifts corresponding to the load magnitude and coil power, and its operating frequency falls around 100 kilohertz (kHz), i.e., a period of about 0.01 milliseconds. In this case, the determination of the wobble signal is performed about 25 times every time the data is outputted to the wobble signal queue register, but the determination times vary depending on the change of the oscillation period/operation frequency of the coil.

In one embodiment, the processor 111 can know the period of the modulation signal/data according to the system setting, and perform the interpretation during the period, and suspend the interpretation of the modulation data during other periods, so as to save the computing resources. In one embodiment, according to the communication specification of the inductive power supply system, the power receiving end transmits a byte of data in every 50 ms period, together with a start bit and a parity check code. In this case, if the processor 111 determines that a byte of data, the start bit and the parity have been received within a 50 ms period, the data interpretation operation may be suspended until the interpretation is started within the next 50 ms period.

In this example, bit data may be transmitted in the manner of Table one:

	length of time	Corresponding time grid interval
			Start bit	2.5 milliseconds	10
Bit value 0	2 milliseconds	8
			Bit value 1	3 milliseconds	12
Parity check code 0	2.75 milliseconds	11
			Parity check code 1	3.25 milliseconds	13

Watch 1

As can be seen from the above, the data cycle of the jitter signal queue register is 0.25 ms, i.e. each time slot is 0.25 ms, so the time lengths of the different data codes can be corresponded to each other in the manner of table one. In this case, the minimum time length of a complete data string (including a byte of data, a start bit and a parity code) is 21.25 ms (including 8 bit values 0 and parity code 0), and the maximum time length is 29.25 ms (including 8 bit values 1 and parity code 0, for example, even parity). The processor 111 obtains the data code of the modulated data according to the value filled in each time slot (step 214). In detail, the processor 111 can take out a first time slot filled with 1 and a second time slot filled with 1 next, and calculate the interval between the first time slot and the second time slot to determine whether the interval conforms to the bit length of the data code, so as to obtain the data code according to the size of the interval. For example, when the interval size of the time grid is 8, the data code may be determined to be 0; when the interval size of the time lattice is 12, the data code is judged to be 1.

Referring to fig. 6, fig. 6 is a diagram illustrating an embodiment of determining start bits and data codes according to intervals of time slots. As shown in FIG. 6, each time bin can be sequentially filled with values from 0 to 31 in the jitter signal queue register according to the aforementioned flag TMR 3. First, the processor 111 determines whether the start bit, i.e., the time slots numbered 0 and 10, is present and filled with the value 1. For example, the processor 111 may determine whether the positions separated by 10 time slots are the value 1 after the time slots are filled with the value 1, and if so, determine that the start bit is received. The start bit may be used to determine whether the data code has started to be transmitted, or may be used to define the time mapping relationship of the data code, that is, the processor 111 may determine the position of the wobble signal queue register that may be filled with the value 1 according to the position of the time slot at which the start bit is received. Taking fig. 6 as an example, the time slots numbered 0 and 10 define the position of the start bit, so the time slots numbered 18, 22, 26, and 30 are the positions that can be filled with the value 1, and if the first data code is 0, the time slot numbered 18 is the value 1; if the first data code is 1, the time grid of the number 22 is the value 1. In one embodiment, the processor 111 may retrieve the value of each time bin for subsequent interpretation. Alternatively, the processor 111 may only take out the time bin into which the value 1 may be filled and/or the time bins adjacent to the time bin to perform the subsequent interpretation, so as to save the operation resources, and the value 1 filled in the remaining time bins does not conform to the encoding scheme, which is inevitably the jitter caused by the noise, and is negligible. Finally, the processor 111 may determine the parity check code according to the interval of the time grid to complete the determination of the set of modulation data.

It should be noted that it is not ideal to find the trigger gap from the comparator module to determine the jitter signal on the coil, and then write the information related to the jitter signal into the jitter signal queue register. For example, the modulation at the power receiving end generates a time jitter on the power supply coil, and the corresponding jitter signal may have a time offset and thus appear in advance or delayed to an adjacent time bin. Alternatively, when the signal quality is good, the jitter signal is maintained for a long time, and when the jitter signal is not synchronized with the detection period of the time cell, the condition that the values 1 are filled in two consecutive adjacent time cells may occur. Therefore, in addition to determining the time bin that may be filled with the value 1, the processor 111 also determines the adjacent time bins to respond to the jitter signal being shifted or extended.

In one embodiment, the processor 111 may take the time bin number filled with the value 1 from the time bin possibly filled with the value 1 and the adjacent time bins, and fill the time bin number into a jitter time bin sequence PIN, as shown in table two:

watch two

In Table two, the jitter time bin sequences PIN _01 through PIN _18 represent the time bin numbers filled with the value 1 when the jitter signal is detected in a sequence of time bins, which are the same as the numbers in FIG. 6 and include the subsequent extensions of the figure. The jitter cell intervals GAP _01 to GAP _18 respectively describe the interval between every two adjacent time cells in the jitter cell sequences PIN _01 to PIN _18, for example, GAP _01 records the interval between PIN _01 and the time (cell number 10) when the start bit ends, GAP _02 records the interval between PIN _02 and PIN _01, GAP _03 records the interval between PIN _03 and PIN _02, and so on.

Next, the processor 111 decodes the jitter cell interval according to the values recorded in the jitter cell intervals GAP _01 to GAP _ 18. As described above (see Table one), bit values of 0 and 1 correspond to time cell intervals 8 and 12, respectively, from which decoding can occur. First, GAP _01 equals 8, representing a first bit of 0.GAP _02 equals 1, indicating the first bit crossing to the adjacent time bin, and then GAP _03 equals 7, and the portion of GAP _02+ GAP_03=8, indicating the second bit is 0.GAP _04 equals 1, indicating that the second bit also spans to the adjacent time bin, then GAP _05 equals 11, and the portion of the second bit span is added, GAP _04+ GAP_05 =12, representing that the third bit is 1. And so on, one byte of modulation data can be obtained as "00110101". Then, the processor 111 may determine the parity code, which represents that the parity code is 0 since GAP _16 is equal to 1 and GAP _17 is equal to 10, GAP _16+ GAP _17= 11. From the encoding of the parity check, the byte of data is correct, and the processor 111 receives the modulated data for subsequent processing. After the modulated data is received, the processor 111 may clear the contents of the jitter cell sequences PIN _01 to PIN _18 and the jitter cell intervals GAP _01 to GAP _18 for the subsequent data code processing.

As can be seen from the above, bit value 0 and bit value 1 can be defined according to the encoding specification to correspond to time bin intervals 8 and 12, respectively, and time bin intervals 7 and 11 are allowable errors, which can be processed in the complementary manner to obtain the correct code. In another embodiment, the time interval may be 9 or 13, and may be adjusted to be 8 or 12 in a similar manner, so as to determine the data code.

Thus, each complete data string (including a byte of data, a start bit, and a parity) transmission includes 11 jitter characteristics, as shown in FIG. 7. Fig. 7 shows a waveform of a coil signal C1 carrying a complete data string, after each jitter characteristic is analyzed and marked, at least 11 time slots (and adjacent time slots thereof) at different positions are respectively recorded, and then 10 groups of data at intervals of the time slots are generated, and the processor 111 can judge the value of the data code according to the data characteristic and judge whether the data code is correct through the parity check code.

It is noted that an object of the present invention is to provide a data decoding method for an inductive power supply, which can decode the modulated data carried on the coil signal. Those skilled in the art can make modifications or changes thereto without being limited thereto. For example, the encoding method is only an exemplary embodiment, and the decoding method of the present invention can also be applied to different data code architectures, for example, using different time lengths to define encoding, or transmitting multi-byte data codes in a complete data string, but not limited thereto. In addition, the decoding method of the present invention can be used in various data transmission systems that encode data by time, and is not limited to the modulated data transmission of the aforementioned inductive power supply. In addition, those skilled in the art will appreciate that the various values, numbers, etc. set forth above are only one of many embodiments of the present invention, and the number defined can be adjusted according to system requirements.

In summary, the present invention provides a decoding method for a signal processing circuit in an inductive power supply, which is used to decode modulated data received by a power supply module. The modulation data/signal received by the power supply module can generate jitter on the power supply coil so as to generate a trigger gap in the detection process of the comparator module. The processor can generate a gap indication signal according to the number of trigger gaps which continuously occur, and judges whether the gap indication signal is dispersed in a period of time to ensure that the gap is generated by the jitter of the modulation signal, and then the jitter signal is input through the mark of the mark to fill the value 1 in the corresponding time slot of the jitter signal queue register. Then, the processor can take out the position or number of the time cell filled with the value 1 and judge the bit value of the data code according to the distance. The multilevel decoding method can effectively extract correct modulation data even under the interference of power supply noise.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A decoding method for a signal processing circuit that receives a modulated data carried by a coil signal, the decoding method comprising:

receiving the coil signal and judging a jitter characteristic of the coil signal;

when the jitter characteristic appears at a peak position of a plurality of peaks on the coil signal, obtaining a trigger notch;

judging the length of the trigger gap, and outputting a gap indication signal when the length of the trigger gap is within a preset range;

judging whether a plurality of gap indication signals appear in a first period, and judging whether the plurality of gap indication signals are dispersed in the first period;

marking a mark as a jitter signal according to a judgment result of judging whether the plurality of notch indicating signals appear in the first period and judging whether the plurality of notch indicating signals are dispersed in the first period;

judging whether the mark is marked as the jitter signal in a second period, and filling a numerical value in a time slot corresponding to the second period in a plurality of time slots for judging the modulation data according to the judgment; and

and acquiring a data code of the modulation data according to the numerical values filled in the time grids.

2. The decoding method of claim 1, wherein the steps of receiving the coil signal, determining the jitter characteristic of the coil signal, and obtaining the trigger notch when the jitter characteristic occurs at the peak position of the plurality of peaks on the coil signal comprise:

setting a peak voltage level for tracking the peak voltages of the plurality of peaks;

reducing the peak voltage level by a predetermined value to obtain a discrimination voltage level;

comparing the discrimination voltage level with the coil signal; and

when the peak voltage of one of the plurality of wave crests is detected to be smaller than the judging voltage level, a trigger gap is judged to appear.

3. The decoding method of claim 1, wherein the first period is divided into a first sub-period and a second sub-period, and the step of determining whether the gap indication signal is scattered in the first period comprises:

judging whether the notch indicating signal appears in the first sub-period;

judging whether the gap indication signal appears in the second sub-period; and

when the gap indication signal appears in the first sub-period and the second sub-period, the gap indication signal is judged to be dispersed in the first period.

4. The decoding method of claim 1, wherein the step of marking the flag as the wobble signal according to the determination result of whether the plurality of gap indication signals appear in the first period and whether the plurality of gap indication signals are scattered in the first period comprises:

when the gap indication signal appears in the first period and the gap indication signal is dispersed in the first period, the mark is marked as the jitter signal.

5. The decoding method of claim 1, wherein determining whether the flag is marked as the wobble signal during the second period, and accordingly filling the time bin corresponding to the second period among the plurality of time bins for determining the modulated data comprises:

filling a first value in the time slot corresponding to the second period when the mark is marked as the wobble signal; and

when the mark is not marked as the wobble signal, filling the time frame corresponding to the second period with a second value.

6. The decoding method of claim 5, wherein the step of obtaining the data code of the modulated data according to the values filled in the time bins comprises:

taking out a first time cell filled with the first value and a second time cell filled with the first value next from the plurality of time cells;

calculating an interval between the first time interval and the second time interval to determine whether the interval conforms to a bit length of the data code; and

and obtaining the data code according to the size of the interval.

7. The decoding method of claim 6, further comprising:

at least one of a start bit and a parity of the modulated data is determined according to the interval.

8. The decoding method of claim 7, further comprising:

during a third period, the start bit, a byte of data code, and the parity code of the modulated data are obtained.

9. The decoding method of claim 8, wherein the third period equals 50 ms and the second period equals 0.25 ms.

10. The decoding method of claim 1, further comprising:

at the end of the second period, if the flag is marked as the wobble signal, the mark of the flag is cleared.

11. A signal processing circuit for receiving a modulated data carried by a coil signal and decoding the modulated data, the signal processing circuit comprising:

at least one comparator module for receiving the coil signal and determining a jitter characteristic of the coil signal; and

a processor, coupled to the at least one comparator module, for performing the following steps:

judging whether the mark is marked as the jitter signal or not in a second period, and filling a value in a time slot corresponding to the second period in a plurality of time slots for judging the modulation data according to the judgment; and

12. The signal processing circuit of claim 11, wherein the at least one comparator module comprises a first comparator module and a second comparator module, wherein the first comparator module, the second comparator module and the processor perform the following steps to receive the coil signal and determine the jitter characteristic of the coil signal, and further obtain the trigger notch when the jitter characteristic occurs at the peak position of the peaks on the coil signal:

the processor sets a peak voltage level so that the first comparator module is used for tracking the peak voltage of the plurality of peaks;

the processor reduces the peak voltage level by a predetermined value to obtain a discrimination voltage level;

the second comparator module compares the discrimination voltage level with the coil signal; and

when the second comparator module detects that the peak voltage of one of the wave crests is smaller than the judgment voltage level, the processor judges that a trigger gap is formed.

13. The signal processing circuit of claim 11 wherein the first period is divided into a first sub-period and a second sub-period, and the processor performs the following steps to determine whether the gap indication signal is scattered within the first period:

judging whether the notch indicating signal appears in the first sub-period;

judging whether the notch indicating signal appears in the second sub-period; and

when the gap indication signal appears in both the first sub-period and the second sub-period, the gap indication signal is judged to be dispersed in the first period.

14. The signal processing circuit of claim 11 wherein the processor performs the following steps to mark the flag as the wobble signal according to the determination of whether the plurality of hole indication signals are present in the first period and whether the plurality of hole indication signals are scattered in the first period:

15. The signal processing circuit of claim 11 wherein the processor performs the following steps to determine whether the flag is marked as the wobble signal during the second period, and accordingly fill the time bin corresponding to the second period in the plurality of time bins for determining the modulated data with the value:

16. The signal processing circuit of claim 15 wherein the processor performs the following steps to obtain the data code of the modulated data according to the values filled in the time bins:

calculating an interval between the first time interval and the second time interval to judge whether the interval conforms to a bit length of the data code; and

and obtaining the data code according to the size of the interval.

17. The signal processing circuit of claim 16 wherein the processor further performs the steps of:

18. The signal processing circuit of claim 17 wherein the processor further performs the steps of:

19. The signal processing circuit of claim 18 wherein the third period is equal to 50 milliseconds and the second period is equal to 0.25 milliseconds.

20. The signal processing circuit of claim 11, wherein the processor further performs the steps of: