CN107919861B - Digital signal isolator - Google Patents
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- CN107919861B CN107919861B CN201610878162.4A CN201610878162A CN107919861B CN 107919861 B CN107919861 B CN 107919861B CN 201610878162 A CN201610878162 A CN 201610878162A CN 107919861 B CN107919861 B CN 107919861B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/52—One-way transmission networks, i.e. unilines
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
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Abstract
The invention provides a digital signal isolator, comprising: a sending end and a receiving end; the transmitting end includes: the device comprises a first filter circuit, a refreshing circuit, a delay circuit, a refreshing pulse combination circuit, a differential signal conversion circuit, a first isolation gate capacitor and a second isolation gate capacitor; the receiving end includes: a third isolation gate capacitor, a fourth isolation gate capacitor, a hysteresis comparator, a watchdog circuit, a second filter circuit, and an OR gate. The digital signal isolator in the invention can not be interfered by a common mode level even if the level is kept unchanged for a long time when a low-speed signal is transmitted, thereby effectively avoiding the problem of false triggering.
Description
Technical Field
The invention relates to the technical field of digital signal transmission, in particular to a digital signal isolator based on double-isolation-gate capacitors.
Background
Isolation is a hot topic at present, and the research on isolation and isolation type devices has important significance. At present, a plurality of groups of ground wires are arranged in a plurality of systems, and a ground wire loop can pass through a large current, so that large noise can be brought, the system performance can be influenced, and system components can be burnt. In order to prevent the above problems, the prior art generally adopts an isolation method to solve the problems. Secondly, the human operation control interface is sometimes desired to be isolated from the system execution end, on one hand, the system execution end may have a high-voltage dangerous environment, and on the other hand, the circuit instability caused by human factors is also reduced. In this case, an isolator is also indispensable. The digital signal isolator is mainly used for transmitting digital signals, and the digital isolation technology is commonly used in field buses, military electronic systems, aerospace electronic equipment and medical equipment in industrial network environments, especially in some occasions with severe application environments.
The isolation methods of the mainstream today are generally three types: optical coupling isolation, isolation type on-chip transformer magnetic coupling isolation and capacitive coupling isolation. The optical coupling isolator is low in cost, slow in reaction, large in power consumption and easy to age. The power consumption of the magnetic coupling isolator of the isolation type on-chip transformer is 1/10-1/15 of an optical coupling isolation mode, the reaction speed is high, the reliability is high, but a special process is needed to be adopted for manufacturing the micro-on-chip transformer, and the process difficulty and the manufacturing cost are very high. The capacitive coupling isolator has the advantages of high reaction speed and low power consumption, the isolation material of the capacitive isolator is generally silicon dioxide, the silicon dioxide is easy to grow on a silicon wafer, the cost is low, and the silicon dioxide also has good insulating property.
For example, ISO72x series chips of Texas Instruments (TI) company are chips with capacitors as isolation cores, and have a structure shown in fig. 1a, an input signal is processed through a high-speed channel and a low-speed channel at the same time to perform data transmission, waveforms of key nodes are shown in fig. 1b, the high-speed signal is processed through the high-speed channel, the signal is first converted into a single-ended signal M and N through a differential signal conversion circuit 103, then two weak pulse signals P and Q with opposite phases are generated through an isolation capacitor 104, and a data signal R is recovered through a hysteresis comparator 105. The detection circuit 106 includes a watchdog timer that measures the time duration between transitions of the signal R. If the duration between two consecutive transitions exceeds the timing window (as in the case of a low frequency signal or a dc signal), the detection circuit 106 output signal S is low indicating that the output multiplexer 107 switches from the high speed channel to the low speed channel. The capacitance value required for the transmission of low frequency signals is very large, which makes implementation very difficult. Therefore, the input of the low-speed signal has a pulse width modulator 109, and the pulse width modulator 109 modulates the low-frequency input signal with a high-frequency carrier of an internal oscillator 108 to obtain a signal L, wherein the modulated frame has a length of 10 clock cycles, which includes a start bit, a data bit, and an end bit. The modulated signal L is processed in the same manner as the high-speed signal, and the data signal R is recovered through the differential signal conversion circuit 110, the isolation capacitor 111, and the hysteresis comparator 112. However, before submitting the signal to the output multiplexer 107, the high frequency carrier needs to be filtered out by a low pass filter 113 to recover the original low frequency input signal T.
On the one hand, the capacitive isolation element has some defects, for example, the improvement of the voltage resistance is limited by the process and the thickness of the insulating medium, so if the requirement of high voltage resistance is to be met, a special process is needed, and the process difficulty and the manufacturing cost are also very high; on the other hand, because a mode of respectively processing high-speed data and low-speed data is adopted, the circuit is complex to realize, the power consumption is high, the design cost is increased, and certain limitations exist.
In addition, a digital signal isolator based on double-isolation gate capacitance is also proposed in the silicon valley laboratory, as shown in fig. 2a, the waveform of a key node is shown in fig. 2b, and the waveform of an input data signal is shown in fig. 2 b; the carrier signals X1 and Y1 are modulated into high frequency carrier signals through the modulation circuit 203, the waveforms are as shown in fig. 2b, and the phase difference between the waveform of Y1 and the waveform of X1 is 180 degrees, which is not described herein; the carrier signal is coupled to the receiving input terminal through the isolation gate capacitor 204, and is coupled through the isolation gate capacitor 205 at the receiving terminal to obtain signals X2 and Y2, the waveform of which is shown in fig. 2b, and the phase difference between the waveform of Y1 and the waveform of X1 is 180 degrees, which is not described herein again; the coupled carrier signals X2 and Y2 are demodulated by the demodulation circuit 206 to obtain an output waveform output, as shown in fig. 2 b.
However, the digital signal isolator based on the double isolation gate capacitor improves the voltage withstanding capability of the isolation. However, since the method of transmitting low frequency data using high frequency pulses is adopted when data is transmitted, power consumption is large, cost is high, and there is a certain limitation.
Disclosure of Invention
In view of the above, the present invention provides a digital signal isolator, which is not interfered by a common mode level even if the level is maintained for a long time when a low-speed signal is transmitted, so as to effectively avoid the problem of false triggering.
The technical scheme of the invention is realized as follows:
a digital signal isolator, comprising: a sending end and a receiving end;
the transmitting end comprises: the device comprises a first filter circuit, a refreshing circuit, a delay circuit, a refreshing pulse combination circuit, a differential signal conversion circuit, a first isolation gate capacitor and a second isolation gate capacitor;
the output end of the first filter circuit is respectively connected with the input ends of the refreshing circuit and the delay circuit; the output ends of the refreshing circuit and the delay circuit are connected with the input end of the refreshing pulse combination circuit; the output end of the refresh pulse combination circuit is connected with the input end of the differential signal conversion circuit; the output end of the differential signal conversion circuit is respectively connected with one end of the first isolation gate capacitor and one end of the second isolation gate capacitor;
the receiving end includes: the circuit comprises a third isolation gate capacitor, a fourth isolation gate capacitor, a hysteresis comparator, a watchdog circuit, a second filter circuit and an OR gate;
one end of the third isolation gate capacitor is connected with one end of the first isolation gate capacitor through a bonding wire; one end of the fourth isolation gate capacitor is connected with one end of the second isolation gate capacitor through a bonding wire; the other ends of the third isolation gate capacitor and the fourth isolation gate capacitor are connected with the input end of the hysteresis comparator; the output end of the hysteresis comparator is respectively connected with the input ends of the watchdog circuit and the filter circuit; the output ends of the watchdog circuit and the second filter circuit are connected with the input end of the OR gate;
the first filter circuit is used for filtering high-frequency noise burrs of an input signal to obtain a signal A;
the refreshing circuit is used for detecting the signal A and generating a refreshing pulse signal B with the period length of a preset first period when the duration that the level of the signal A is kept unchanged exceeds a preset first threshold value; the period length of the refresh pulse signal B is greater than the maximum transmission rate of the input signal, and the width of the refresh pulse signal B is less than the pulse width of the maximum transmission rate of the input signal;
the delay circuit is used for delaying the signal A to obtain a signal C, and the delay time from the signal C to the signal A is the same as the delay time from the refresh pulse signal B to the signal A;
the refresh pulse combination circuit is used for performing logic calculation on the refresh pulse signals B and C to obtain a single-ended signal D carrying refresh pulse information;
the differential signal conversion circuit is used for converting the single-ended signal D into differential signals E and F; wherein the phase difference between signal E and signal F is 180 degrees;
the first, second, third and fourth isolation gate capacitors respectively couple signals E and F to obtain signals G and H; the phase difference between the coupled signal G and the coupled signal F is 180 degrees;
the hysteresis comparator is used for filtering noise on the signals G and H and restoring the noise to a data signal I;
the watchdog circuit is used for detecting the data signal I and pulling the output signal J to a safe level when the duration of the detected constant level of the data signal I exceeds a preset second threshold;
the second filter circuit is used for filtering the recovered data signal I and filtering a high-frequency refresh pulse signal to obtain a complete data signal K;
and the OR gate is used for carrying out OR logic processing on the signal J and the signal K to obtain a final output signal.
Preferably, the isolation gate capacitor comprises at least three metal layers;
the negative plate of the isolation gate capacitor is made of a metal layer at the bottommost layer; the positive plate of the isolation gate capacitor is made of a metal layer with the highest layer;
and an isolation layer is arranged between the metal layer of the bottommost layer and the metal layer of the highest layer.
Preferably, the isolation gate capacitor comprises five metal layers;
the negative plate of the isolation gate capacitor is made of a first metal layer on the bottommost layer;
the positive plate of the isolation gate capacitor is made of a fifth metal layer of the highest layer;
the isolation layer is an insulation layer arranged among a second metal layer, a third metal layer and a fourth metal layer which are arranged between the first metal layer and the fifth metal layer;
and insulating materials are filled among the second metal layer, the third metal layer and the fourth metal layer to form the insulating layers, so that the insulating layers are used as isolating layers between a negative plate and a positive plate of the isolation gate capacitor.
Preferably, the transmitting end is packaged in the same chip;
the receiving end is packaged in another chip.
According to the technical scheme, in the digital signal isolator with the refreshing circuit and based on the double-isolation-gate capacitor, after the sending end filters the input signal, the refreshing circuit, the delay circuit and the refreshing pulse combination circuit are used for processing the filtered input signal; correspondingly, after noise of a signal obtained by coupling of the isolated gate capacitor is filtered, the receiving end continues processing by using the watchdog circuit and the second filter circuit, so that even if the level is kept unchanged for a long time when a low-speed signal is transmitted, the level is not interfered by a common mode level, and the problem of false triggering is effectively avoided; in addition, because the high-speed signal and the low-speed signal do not need to be processed respectively, the coding and decoding mode is simple, and the use of a complicated coding circuit is avoided.
In addition, because the digital signal isolator adopts the cascaded double-isolation-gate capacitor, the voltage resistance of the digital signal isolator is doubled compared with that of a single-isolation-gate capacitor, the digital signal isolator is simple in structure, and the process difficulty and the manufacturing cost are reduced while the high voltage resistance is realized on the basis of a standard CMOS (complementary metal oxide semiconductor) process.
Drawings
Fig. 1a is a schematic structural diagram of a digital signal isolator based on isolation gate capacitance proposed by TI corporation in the prior art.
Fig. 1b is a schematic diagram of signal waveforms of each key node when a digital signal isolator based on isolation gate capacitance proposed by TI corporation in the prior art transmits data.
Fig. 2a is a schematic structural diagram of a digital signal isolator based on double isolation gate capacitors proposed in a silicon valley laboratory in the prior art.
Fig. 2b is a schematic signal waveform diagram of each key node when a digital signal isolator based on double isolation gate capacitors is proposed in a silicon valley laboratory in the prior art to transmit data.
Fig. 3 is a schematic structural diagram of a digital signal isolator in an embodiment of the present invention.
Fig. 4 is a schematic signal waveform diagram of each key node when the digital signal isolator transmits data according to the embodiment of the present invention.
Fig. 5 is a schematic perspective view of an isolated gate capacitor according to an embodiment of the invention.
Detailed Description
In order to make the technical scheme and advantages of the invention more apparent, the invention is further described in detail with reference to the accompanying drawings and specific embodiments.
The invention provides a digital signal isolator based on double isolation gate capacitors, which is used as a dual-port device, wherein complete electrical isolation is realized between an input port and an output port of the digital signal isolator due to the existence of the internal isolation gate capacitors, and signal transmission is completed through the coupling effect of the isolation gate capacitors.
Fig. 3 is a schematic structural diagram of a digital signal isolator in an embodiment of the present invention. As shown in fig. 3, the digital signal isolator in the embodiment of the present invention includes: a transmitting end 301 and a receiving end 302;
the transmitting end 301 includes: a first filter circuit 303, a refresh circuit 304, a delay circuit 307, a refresh pulse combining circuit 305, a differential signal conversion circuit 306, a first isolation gate capacitor 308, and a second isolation gate capacitor 309;
wherein, the output end of the first filter circuit 303 is respectively connected with the input ends of the refresh circuit 304 and the delay circuit 307; the output terminals of the refresh circuit 304 and the delay circuit 307 are both connected to the input terminal of the refresh pulse combining circuit 305; the output end of the refresh pulse combining circuit 305 is connected with the input end of the differential signal conversion circuit 306; the output end of the differential signal conversion circuit 306 is connected to one end of a first isolation gate capacitor 308 and one end of a second isolation gate capacitor 309 respectively;
the receiving end 302 includes: a third isolation gate capacitor 310, a fourth isolation gate capacitor 311, a hysteresis comparator 312, a watchdog circuit 313, a second filter circuit 314, and an or gate 315;
one end of the third isolation gate capacitor 310 is connected with one end of the first isolation gate capacitor 308 through a bonding wire; one end of the fourth isolation gate capacitor 311 is connected with one end of the second isolation gate capacitor 309 through a bonding wire; the other ends of the third isolation gate capacitor 310 and the fourth isolation gate capacitor 311 are both connected with the input end of the hysteresis comparator 312; the output end of the hysteresis comparator 312 is connected to the input ends of the watchdog circuit 313 and the second filter circuit 314 respectively; the output terminals of the watchdog circuit 313 and the second filter circuit 314 are both connected to the input terminal of the or gate 315.
In order to better explain the functional structure and implementation principle of the digital signal isolator shown in fig. 3, the signal waveforms of the key nodes of the digital signal isolator shown in fig. 4 will be explained below.
For example, fig. 4 is a schematic signal waveform diagram of each key node when the digital signal isolator transmits data according to the embodiment of the present invention, as shown in fig. 4, in the digital signal isolator of the present invention:
the first filter circuit 303 is configured to filter high-frequency noise glitches from the input signal to obtain a signal a;
the refresh circuit 304 is configured to detect the signal a, and generate a refresh pulse signal B with a period length of a preset first period when it is detected that a duration of the level of the signal a remaining unchanged exceeds a preset first threshold. The period length of the refresh pulse signal B is much greater than the maximum transmission rate of the input signal, and the width of the refresh pulse signal B is much less than the pulse width of the maximum transmission rate of the input signal;
the delay circuit 307 delays the signal a to obtain a signal C, and makes the delay time from the signal C to the signal a the same as the delay time from the refresh pulse signal B to the signal a, thereby preventing the transmission data from colliding with the refresh pulse signal B;
the refresh pulse combination circuit 305 is configured to perform logic calculation on the refresh pulse signals B and C to obtain a single-ended signal D carrying refresh pulse information;
the differential signal conversion circuit 306 is configured to convert the single-ended signal D into differential signals E and F; wherein the phase difference between signal E and signal F is 180 degrees; the differential transmission mode is used for suppressing the interference of common-mode noise;
two pairs of isolation gate capacitors 308, 309 and 310, 311 couple signals E and F to obtain signals G and H, respectively; the phase difference between the coupled signal G and the coupled signal F is 180 degrees;
since the signal coupled through the isolated gate capacitor inevitably generates a certain deformation, the hysteresis comparator 312 is used to filter out the noise on the signals G and H and restore them to the data signal I;
the watchdog circuit 313 is configured to detect the data signal I, and pull the output signal J to a safe level when detecting that a duration of time during which a level of the data signal I remains unchanged exceeds a preset second threshold; preferably, in the embodiment of the present invention, the safety level can be considered as a high level;
the second filter circuit 314 is configured to filter the recovered data signal I, filter a high-frequency refresh pulse signal, and obtain a complete data signal K;
or gate 315, configured to perform or logic processing on signal J and signal K to obtain a final output signal output.
Therefore, in the digital signal isolator, when the transmission data signal input is a low-speed signal, the refresh circuit 304 generates the refresh pulse signal B, which is a high-frequency narrow pulse of GHz or more; when the transmission data signal input is a high-speed signal, the refresh pulse signal B is always kept low, as shown in fig. 4. Therefore, the signal a will get the signal C and the signal B after passing through the delay circuit 307, and the signal C and the signal B will get the signal D after passing through the refresh pulse combining circuit 305, thereby achieving the purpose of fusing the refresh pulse with the data information; the signal D passes through a differential signal conversion circuit 306 to obtain signals E and F, and the phase difference between the signals E and F is 180 degrees; coupling the signals E and F through an isolation gate capacitor to obtain signals G and H, wherein the signals G and H are pulse signals with opposite phases; the signals G and H are restored to signal I by the hysteresis comparator 312, where the signal I carries a data signal of the refresh pulse information; the signal I passes through a watchdog circuit 113 to obtain a signal J; because the signal J carries the refresh pulse information, if the watchdog circuit 113 does not detect a long-time dc level, a safety level signal is not generated, and a low level is maintained all the time; the signal I passes through the second filter circuit 314 to obtain a signal K, which filters out the high-frequency refresh pulse signal to obtain a correct data signal. The signals J and K output data signals output through the or gate 315, and the original signal waveform is recovered.
In addition, in the technical scheme of the invention, the isolation gate capacitor can be manufactured by using at least three or more metal layers to form a three-dimensional sandwich structure.
Therefore, preferably, in the embodiment of the present invention, the isolation gate capacitor includes at least three metal layers;
the negative plate of the isolation gate capacitor is made of a metal layer at the bottommost layer; the positive plate of the isolation gate capacitor is made of a metal layer with the highest layer;
and an isolation layer is arranged between the metal layer of the bottommost layer and the metal layer of the highest layer.
For example, in the preferred embodiment of the present invention, the isolation gate capacitor can be formed by a five-layer metal standard cmos process, thereby forming a three-dimensional sandwich structure as shown in fig. 5.
For example, preferably, as shown in fig. 5, in an embodiment of the present invention, the isolation gate capacitor includes five metal layers;
the negative plate of the isolation gate capacitor is made of the first metal layer 501 at the bottommost layer; the positive plate of the isolated gate capacitor is made of a fifth metal layer 505 with the highest layer;
the isolation layer is an insulation layer arranged among a second metal layer 502, a third metal layer 503 and a fourth metal layer 504 which are positioned between the first metal layer 501 and the fifth metal layer 505;
the second metal layer 502, the third metal layer 503 and the fourth metal layer 504 are not designed with metal patterns, and insulating materials (for example, silicon dioxide) are filled among all the layers of the second metal layer 502, the third metal layer 503 and the fourth metal layer 504 to form the insulating layers, so that the insulating layers are used as isolating layers between a negative plate and a positive plate of the isolation gate capacitor.
Certainly, in the technical solution of the present invention, when the five-layer metal standard cmos process is used to manufacture the isolation gate capacitor, the positions of the negative plate, the positive plate and the isolation layer in the five-layer metal may also be preset or selected according to the requirements of the practical application (for example, the negative plate is located in the second metal layer 502, the positive plate is located in the fourth metal layer 504, and the isolation layer is located in the third metal layer 503), so as to adjust the thickness of the isolation layer, and implement different isolation strengths of the isolation gate capacitor.
In addition, preferably, in an embodiment of the present invention, the transmitting end 301 may be packaged in the same chip, for example, may be packaged in the encoding chip 301 shown in fig. 3; the receiving end 302 may also be packaged in the same chip, for example, in the decoding chip 302 shown in fig. 1.
In summary, in the above digital signal isolator with a refresh circuit and based on a double-isolation-gate capacitor, after the sending end filters the input signal, the sending end also uses the refresh circuit, the delay circuit and the refresh pulse combining circuit to process the filtered input signal; correspondingly, after noise of a signal obtained by coupling of the isolated gate capacitor is filtered, the receiving end continues processing by using the watchdog circuit and the second filter circuit, so that even if the level is kept unchanged for a long time when a low-speed signal is transmitted, the level is not interfered by a common mode level, and the problem of false triggering is effectively avoided; in addition, because the high-speed signal and the low-speed signal do not need to be processed respectively, the coding and decoding mode is simple, and the use of a complicated coding circuit is avoided.
In addition, because the digital signal isolator adopts the cascaded double-isolation-gate capacitor, the voltage resistance of the digital signal isolator is doubled compared with that of a single-isolation-gate capacitor, the digital signal isolator is simple in structure, and the process difficulty and the manufacturing cost are reduced while the high voltage resistance is realized on the basis of a standard CMOS (complementary metal oxide semiconductor) process.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (4)
1. A digital signal isolator, comprising: a sending end and a receiving end;
the transmitting end comprises: the device comprises a first filter circuit, a refreshing circuit, a delay circuit, a refreshing pulse combination circuit, a differential signal conversion circuit, a first isolation gate capacitor and a second isolation gate capacitor;
the output end of the first filter circuit is respectively connected with the input ends of the refreshing circuit and the delay circuit; the output ends of the refreshing circuit and the delay circuit are connected with the input end of the refreshing pulse combination circuit; the output end of the refresh pulse combination circuit is connected with the input end of the differential signal conversion circuit; the output end of the differential signal conversion circuit is respectively connected with one end of the first isolation gate capacitor and one end of the second isolation gate capacitor;
the receiving end includes: the circuit comprises a third isolation gate capacitor, a fourth isolation gate capacitor, a hysteresis comparator, a watchdog circuit, a second filter circuit and an OR gate;
one end of the third isolation gate capacitor is connected with one end of the first isolation gate capacitor through a bonding wire; one end of the fourth isolation gate capacitor is connected with one end of the second isolation gate capacitor through a bonding wire; the other ends of the third isolation gate capacitor and the fourth isolation gate capacitor are connected with the input end of the hysteresis comparator; the output end of the hysteresis comparator is respectively connected with the input ends of the watchdog circuit and the second filter circuit; the output ends of the watchdog circuit and the second filter circuit are connected with the input end of the OR gate;
the first filter circuit is used for filtering high-frequency noise burrs of an input signal to obtain a signal A;
the refreshing circuit is used for detecting the signal A and generating a refreshing pulse signal B with the period length of a preset first period when the duration that the level of the signal A is kept unchanged exceeds a preset first threshold value; the period length of the refresh pulse signal B is greater than the maximum transmission rate of the input signal, and the width of the refresh pulse signal B is less than the pulse width of the maximum transmission rate of the input signal;
the delay circuit is used for delaying the signal A to obtain a signal C, and the delay time from the signal C to the signal A is the same as the delay time from the refresh pulse signal B to the signal A;
the refresh pulse combination circuit is used for performing logic calculation on the refresh pulse signals B and C to obtain a single-ended signal D carrying refresh pulse information;
the differential signal conversion circuit is used for converting the single-ended signal D into differential signals E and F; wherein the phase difference between signal E and signal F is 180 degrees;
the first, second, third and fourth isolation gate capacitors respectively couple signals E and F to obtain signals G and H; the phase difference between the coupled signal G and the coupled signal F is 180 degrees;
the hysteresis comparator is used for filtering noise on the signals G and H and restoring the noise to a data signal I;
the watchdog circuit is used for detecting the data signal I and pulling the output signal J to a safe level when the duration of the detected constant level of the data signal I exceeds a preset second threshold;
the second filter circuit is used for filtering the recovered data signal I and filtering a high-frequency refresh pulse signal to obtain a complete data signal K;
and the OR gate is used for carrying out OR logic processing on the signal J and the signal K to obtain a final output signal.
2. The digital signal isolator of claim 1, wherein:
the isolation gate capacitor comprises at least three metal layers;
the negative plate of the isolation gate capacitor is made of a metal layer at the bottommost layer; the positive plate of the isolation gate capacitor is made of a metal layer with the highest layer;
and an isolation layer is arranged between the metal layer of the bottommost layer and the metal layer of the highest layer.
3. The digital signal isolator of claim 2, wherein:
the isolation gate capacitor comprises five metal layers;
the negative plate of the isolation gate capacitor is made of a first metal layer on the bottommost layer;
the positive plate of the isolation gate capacitor is made of a fifth metal layer of the highest layer;
the isolation layer is an insulation layer arranged among a second metal layer, a third metal layer and a fourth metal layer which are arranged between the first metal layer and the fifth metal layer;
and insulating materials are filled among the second metal layer, the third metal layer and the fourth metal layer to form the insulating layers, so that the insulating layers are used as isolating layers between a negative plate and a positive plate of the isolation gate capacitor.
4. The digital signal isolator of claim 1, wherein:
the transmitting end is packaged in the same chip;
the receiving end is packaged in another chip.
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| CN108988831A (en) * | 2018-06-20 | 2018-12-11 | 苏州纳芯微电子股份有限公司 | Capacitance digital isolating chip and its modulation-demo-demodulation method |
| CN109831202A (en) * | 2019-03-07 | 2019-05-31 | 北京中科格励微科技有限公司 | Linear isolator |
| CN109995356A (en) * | 2019-05-20 | 2019-07-09 | 上海客益电子有限公司 | A kind of signal-isolated transmission circuit based on capacitor |
| CN110690888B (en) * | 2019-09-29 | 2022-10-14 | 北京中科格励微科技有限公司 | Isolator for digital signals |
| CN113013144B (en) * | 2019-12-19 | 2024-05-14 | 上海川土微电子有限公司 | Digital isolator chip |
| CN113659976A (en) * | 2020-05-12 | 2021-11-16 | 上海汽车集团股份有限公司 | Differential signal bidirectional isolation communication circuit and method |
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| CN111969992B (en) * | 2020-08-03 | 2021-06-22 | 苏州纳芯微电子股份有限公司 | Coding and decoding circuit for multi-channel digital signal transmission |
| CN112596428A (en) * | 2020-12-02 | 2021-04-02 | 浙江中控技术股份有限公司 | FF field bus intrinsic safety isolation gate and signal bidirectional transmission method |
| CN113162378B (en) * | 2021-03-31 | 2022-09-30 | 黄山学院 | Intelligent high-voltage insulation isolation half-bridge gate driving circuit |
| CN113422600B (en) * | 2021-08-23 | 2021-11-16 | 南京志杰通信技术有限公司 | Analysis method suitable for digital isolator |
| CN115549670B (en) * | 2022-04-25 | 2023-09-05 | 圣邦微电子（北京）股份有限公司 | digital isolator |
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Effective date of registration: 20210419 Address after: 300457 unit 1013, block 1, msd-g1, TEDA, No.57, 2nd Street, Binhai New Area Development Zone, Tianjin Patentee after: Tianjin Zhimo Technology Co.,Ltd. Address before: Room 5, room 18, room 18, district seventeen, No. 188, Fourth Ring West Road, Beijing, Beijing Patentee before: GL MICROELECTRONICS, Inc. |