CN110266303B

CN110266303B - Refreshing circuit, refreshing method, chip and data transmission system

Info

Publication number: CN110266303B
Application number: CN201910647827.4A
Authority: CN
Inventors: 伍荣翔; 李立松; 方向明
Original assignee: Chongqing Xianyi Electronic Technology Co ltd
Current assignee: Shenzhen Line Easy Microelectronics Co ltd
Priority date: 2019-07-17
Filing date: 2019-07-17
Publication date: 2023-04-28
Anticipated expiration: 2039-07-17
Also published as: CN110266303A

Abstract

The application provides a refreshing circuit, a refreshing method, a chip and a data transmission system, wherein the refreshing circuit comprises: a high resistance state control circuit, a pull-up refreshing circuit and a pull-down refreshing circuit; the input end of the high-resistance state control circuit is used for receiving a target input signal; the output end of the high-resistance state control circuit is connected with the pull-up refreshing circuit; the output end of the high-resistance state control circuit is also connected with the pull-down refreshing circuit; the output end of the high-resistance state control circuit is also connected with an external receiver through an isolation device; when the logic state of the target input signal is maintained unchanged within a preset period and the output of the high-resistance state control circuit is in a high-resistance state, the pull-up refreshing circuit pulls up the output signal of the high-resistance state control circuit according to the target input signal, or the pull-down refreshing circuit pulls down the output signal of the high-resistance state control circuit according to the target input signal, so that a refreshing signal is obtained.

Description

Refreshing circuit, refreshing method, chip and data transmission system

Technical Field

The present disclosure relates to the field of data isolation transmission, and in particular, to a refresh circuit, a refresh method, a refresh chip, and a data transmission system.

Background

The digital isolator can encode and decode the edge of the input signal to transmit the signal, the encoded signal has higher frequency component, and the signal can easily pass through the isolation barrier formed by the isolation device, so that the signal transmission between circuits with high voltage difference is realized.

However, in the conventional transmission process, it is difficult for the receiving end of the system to recover to normal in time after obtaining an error signal due to an emergency.

Disclosure of Invention

An object of the embodiments of the present application is to provide a refresh circuit, method, chip and data transmission system, so as to solve the problem in the prior art that a receiving end of the system is difficult to recover to normal in time after obtaining an error signal due to an emergency.

In a first aspect, an embodiment of the present application provides a refresh circuit, where the refresh circuit includes a high-resistance state control circuit, a pull-up refresh circuit, and a pull-down refresh circuit;

the input end of the high-resistance state control circuit is used for receiving a target input signal, the logic state of the target input signal is a first logic state or a second logic state, and the first logic state and the second logic state are opposite logic states;

the output end of the high-resistance state control circuit is connected with the pull-up refreshing circuit;

The output end of the high-resistance state control circuit is also connected with the pull-down refreshing circuit;

the output end of the high-resistance state control circuit is also connected with an external receiver through an isolation device;

when the logic state of the target input signal is maintained unchanged within a preset time period and the output of the high-resistance state control circuit is in a high-resistance state, the pull-up refreshing circuit pulls up the output signal of the high-resistance state control circuit according to the target input signal, or the pull-down refreshing circuit pulls down the output signal of the high-resistance state control circuit according to the target input signal to obtain a refreshing signal.

By the refresh circuit, the high-resistance state refresh circuit can be pulled up by the pull-up refresh circuit or pulled down by the pull-down refresh circuit under the condition of outputting a high-resistance state, so that the refresh action under the high-resistance state can be completed. The refreshing circuit can send the refreshing signal to the receiver in the high-resistance state when the logic state of the target input signal is maintained unchanged for a period of time, so that the receiving end can correct and recover data in time according to the refreshing signal of the refreshing circuit.

With reference to the first aspect, in one possible design, the high-resistance state control circuit includes a first delayer, a refresh controller, and a high-resistance state control module;

The first delayer is used for generating a first delay signal subjected to first delay according to the target input signal; the refresh controller is used for outputting a refresh enabling signal according to the target input signal; the high-resistance state control module is used for outputting a high-resistance state according to the first delay signal and the refresh enabling signal.

Through the structure, the refresh enabling signal can be obtained based on the target input signal, and the high-resistance state control module can output a high-resistance state according to the refresh enabling signal and the first delay signal, so that the refresh circuit capable of outputting the high-resistance state is obtained.

With reference to the first aspect, in one possible design, the high-impedance state control module includes a first logic circuit, a second logic circuit, and a target inverter;

the first logic circuit is used for outputting a first inversion control signal according to the first delay signal and the refresh enabling signal; the second logic circuit is used for outputting a second inversion control signal according to the first delay signal and the refresh enabling signal; the target inverter is used for outputting a high resistance state according to the first inversion control signal and the second inversion control signal.

By the structure, one possible implementation way of the high-resistance state control circuit is provided, so that the target inverter can output a high-resistance state based on the first delay signal and the refresh enable signal.

With reference to the first aspect, in one possible design, the target inverter includes a first PMOS transistor and a first NMOS transistor;

the grid electrode of the first PMOS tube is connected with the first logic circuit, the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube; the grid electrode of the first NMOS tube is connected with the second logic circuit, and the source electrode of the first NMOS tube is grounded.

With the structure, under the condition that the high-resistance state control circuit outputs a high-resistance state, the pull-up or pull-down refreshing circuit is allowed to linearly charge or discharge the output node of the target inverter, and a refreshing signal is obtained.

With reference to the first aspect, in one possible design, the pull-up refresh circuit includes a first current mirror, a pull-up control circuit;

the two input ends of the pull-up control circuit are respectively used for receiving a refresh enabling signal and the target input signal; the output end of the pull-up control circuit is connected with the first current mirror; the first current mirror is used for carrying out linear charging on the output end of the high-resistance state control circuit.

Through the structure, the first current mirror can be controlled to be turned on or off by the pull-up control circuit, and when the first current mirror is turned on, the output end of the high-resistance state control circuit is charged linearly.

With reference to the first aspect, in one possible design, the pull-up control circuit includes a third logic circuit, a pull-up switching tube; the control end of the pull-up switching tube is connected with the output end of the third logic circuit, and the output end of the pull-up switching tube is connected with the first current mirror; the third logic circuit is configured to output a pull-up refresh control signal having a logic state of the second logic when the target input signal is the second logic and the refresh enable signal is the first logic; the third logic circuit is further configured to output a pull-up refresh control signal having a logic state of the first logic when the target input signal is not the second logic and/or the refresh enable signal is not the first logic.

The structure provides a possible structure of the pull-up refreshing circuit, the pull-up refreshing control signal output by the third logic circuit controls the on or off of the pull-up switching tube, and when the pull-up switching tube is on, the first current mirror is started to linearly charge the output end of the high-resistance state control circuit, and a rapidly-changing signal edge can be formed after the charging is finished.

With reference to the first aspect, in one possible design, the pull-down refresh circuit includes a second current mirror, a pull-down control circuit; the two input ends of the pull-down control circuit are respectively used for receiving a refresh enabling signal and the target input signal; the output end of the pull-down control circuit is connected with the second current mirror; the second current mirror is used for carrying out linear discharge on the output end of the high-resistance state control circuit.

With the structure, the high-resistance state control circuit can be subjected to pull-down processing according to the pull-down refresh circuit, so that a refresh signal is obtained.

With reference to the first aspect, in one possible design, the pull-down control circuit includes a fourth logic circuit and a pull-down switching tube; the control end of the pull-down switching tube is connected with the output end of the fourth logic circuit, and the output end of the pull-down switching tube is connected with the second current mirror; the fourth logic circuit is configured to output a pull-down refresh control signal having a logic state of the first logic when the target input signal is the first logic and the refresh enable signal is the first logic; the fourth logic circuit is further configured to output a pull-down refresh control signal having a logic state of a second logic when the target input signal is not the first logic and/or the refresh enable signal is not the first logic.

One possible implementation of the pull-down refresh circuit is provided by the above structure.

In a second aspect, an embodiment of the present application provides a refresh method, applied to a refresh system, where the refresh system includes a transmitter and a receiver, the transmitter and the receiver are connected through an isolation device, the transmitter includes a refresh circuit according to the foregoing first aspect, and the refresh method includes:

the transmitter receives a target input signal, wherein the logic state of the target input signal is a first logic state or a second logic state, and the first logic state and the second logic state are opposite;

when the logic state of the target input signal is kept unchanged within a preset time period, the transmitter performs pull-up or pull-down processing according to the target input signal through the refresh circuit when the refresh circuit is in a high-resistance state, so as to obtain a refresh signal;

the receiver receives the refresh signal through the isolation device;

and the receiver analyzes according to the refresh signal to obtain a confirmation signal.

By the method, when the logic state of the target input signal is unchanged or the data rate is low in a period of time, the refreshing action under the high-resistance state can be completed, the refreshing signal is obtained, the refreshing signal is received by the receiver through the isolation device, and the confirmation signal is obtained based on the analysis of the refreshing signal. Even if the partial circuit on the transmitter side is unexpected or the system is disturbed, the receiver side can react according to the refresh signal so as to carry out subsequent data correction and recovery.

With reference to the second aspect, in one possible design, the refresh circuit includes: a high resistance state control circuit, a pull-up refreshing circuit and a pull-down refreshing circuit; the high-resistance state control circuit comprises a refresh controller for generating a refresh enabling signal; and when the refresh circuit is in a high resistance state, carrying out pull-up or pull-down processing on the target input signal by the refresh circuit to obtain a refresh signal, wherein the method comprises the following steps of:

when the refresh circuit is in a high-resistance state, the pull-up refresh circuit performs pull-up processing when the target input signal is in a second logic state and the refresh enabling signal is in a first logic state, so as to obtain a refresh signal.

Or when the refresh circuit is in a high-resistance state, the pull-down refresh circuit performs pull-down processing when the target input signal is the first logic and the refresh enabling signal is the first logic, so as to obtain a refresh signal.

The implementation manner provides a manner of performing pull-up processing or pull-down processing based on the logic state of the target input signal and the refresh enable signal to obtain the refresh signal.

With reference to the second aspect, in one possible design, the high-impedance state control circuit in the refresh circuit includes a first delay, a refresh controller, a first logic circuit, a second logic circuit, and a target inverter;

The high resistance state of the refresh circuit is obtained by:

the refresh controller sends a refresh enabling signal to the first logic circuit and the second logic circuit according to the target input signal; the first delay device sends a first delay signal to the first logic circuit and the second logic circuit according to the target input signal; the first logic circuit outputs a first inversion control signal according to the refresh enable signal and the first delay signal, and the second logic circuit outputs a second inversion control signal according to the refresh enable signal and the first delay signal; the target inverter receives the first inversion control signal and the second inversion control signal and outputs a high-resistance state according to the first inversion control signal and the second inversion control signal;

when the refresh enabling signal is a first logic, the logic state of a first inversion control signal output by the first logic circuit is a second logic, and the logic state of a first inversion control signal output by the second logic circuit is the first logic; when the refresh enable signal is a second logic, logic states of the first inversion control signal and the second inversion control signal are the same, and the logic states of the first inversion control signal and the second inversion control signal are determined according to the target input signal.

The implementation mode provides a mode for realizing high-resistance output.

With reference to the second aspect, in one possible design, the logic state of the refresh enable signal is determined by:

the refresh controller periodically converts the logic state of the refresh enable signal to a first logic and then returns to a second logic when the target input signal remains unchanged.

Thereby enabling the determination of the time at which the refresh action is performed.

In a third aspect, an embodiment of the present application provides a chip, where the chip includes the refresh circuit described in the foregoing first aspect.

In a fourth aspect, embodiments of the present application provide a data transmission system, where the data transmission system includes a transmitter and a receiver; the transmitter comprises the refresh circuit of the first aspect; the transmitter and the receiver are connected through an isolation device.

Through the data transmission system, the transmitter can transmit the refresh signal to the receiver by using the refresh circuit, and the receiver can receive the refresh signal through the isolation device and perform subsequent analysis processing. Even if the interval time between two adjacent edge signals of the input signal is long, the receiver side can also carry out data confirmation based on the refresh signal, and then correct and recover data errors caused by some unexpected situations in time.

With reference to the fourth aspect, in one possible design, the isolation device is an isolation capacitor.

In this way, the isolation capacitor can be used as a transmission medium between the transmitter and the receiver, and the receiver can recognize the refresh signal through the isolation capacitor.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a refresh circuit according to an embodiment of the present application.

Fig. 2 is a schematic diagram of another refresh circuit according to an embodiment of the present application.

Fig. 3 is a schematic diagram of a pull-up refresh circuit according to an embodiment of the present application.

Fig. 4 is a schematic diagram of a pull-down refresh circuit according to an embodiment of the present application.

Fig. 5 is a schematic diagram of a refresh circuit in one example provided by embodiments of the present application.

Fig. 6 is a schematic waveform diagram of a refresh circuit according to an embodiment of the present application.

Fig. 7 is a schematic diagram of a refresh waveform obtained after a signal corresponding to the waveform shown in fig. 6 passes through an isolation device.

Fig. 8 is a schematic diagram of an operating principle of a refresh circuit according to an embodiment of the present application.

Fig. 9 is a flowchart of a refreshing method according to an embodiment of the present application.

Fig. 10 is a schematic diagram of a refresh system according to an embodiment of the present application.

Icon: 10-a data transmission system; a 100-sender; 110-a high resistance state control circuit; 111-a first delayer; 112-a refresh controller; 113-a high resistance state control module; 1131-a first logic circuit; 1132-a second logic circuit; 1133-a target inverter; p1-a first PMOS tube; n1-a first NMOS tube; 120-pull-up refresh circuitry; 1201-charge switch; 1202-a first constant current source; 121-a first current mirror; 122-pull-up control circuitry; 1221-third logic circuitry; p2-a second PMOS tube; p3-a third PMOS tube; p4-pull-up switching tube; u1-a first current source; 130-a pull-down refresh circuit; 1301-a discharge switch; 1302-a second constant current source; 131-a second current mirror; 132-a pull-down control circuit; 1321-fourth logic circuits; n2-a second NMOS tube; n3-third NMOS tube; n4-pull-down switching tube; u2-a second current source; 200-isolating devices; 201-a first capacitance; 202-a first resistor; 300-receiver.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

The inventors have found that in existing digital isolation applications, the signal is transmitted by encoding and decoding the edges of the input signal. In the prior art, the following two problems easily occur by simply depending on the mode of coding and decoding the signal edge to perform signal transmission:

1. when the data rate of the input signal is low, two adjacent signal edges are separated by a long time, and after decoding one signal edge, the receiver may take a long time to parse the next signal edge, thereby completing the decoding of the input signal. In the practical application scenario, if the whole system is interfered by the outside and has errors, the receiver needs to receive the ' next signal edge ' of the real input signal and analyze the next signal edge ' after a long time. This makes it necessary for the receiver side to take a long time for data correction when the data rate of the input signal is low.

2. If an accident (such as power failure) occurs in a part of the circuit on the transmitter side in the system, the receiver side cannot timely learn the abnormality on the transmitter side, and timely response is difficult to ensure the safety of the whole system.

The inventors therefore propose the following embodiments to ameliorate the above drawbacks, so that the transmitter side of the system can send a refresh signal for acknowledgement to the receiver before the "next signal edge" of the input signal comes, and the receiver side can derive an acknowledgement signal from the refresh signal before the "next signal edge" of the actual input signal is received. Even if an accident happens, the receiver side can correct or recover according to the refresh signal in time.

To facilitate understanding of the schemes, some terms in this application will be explained below.

High resistance state: representing either a circuit or an output state of a node in the circuit, neither high nor low. When the circuit analysis is carried out, the influence of the high resistance state on the subsequent-stage circuit is low, and the high resistance state under the extreme condition can be regarded as open circuit or suspension.

It should be noted that the following embodiments may be combined with each other and used as a reference.

First embodiment

Referring to fig. 1, fig. 1 is a schematic diagram of a refresh circuit according to an embodiment of the present application. The refresh circuit may be provided at the transmitting end (or transmitter 100, transmitter) of the data transmission system 10.

As shown in fig. 1, the refresh circuit includes a high resistance state control circuit 110, a pull-up refresh circuit 120, and a pull-down refresh circuit 130.

The input terminal of the high-impedance state control circuit 110 is configured to receive a target input signal a, where the logic state of the target input signal a is a first logic or a second logic, and the first logic and the second logic are opposite logic states.

The output of the high impedance state control circuit 110 is connected to a pull-up refresh circuit 120. The output of the high impedance state control circuit 110 is also coupled to a pull-down refresh circuit 130.

The output of the high impedance state control circuit 110 is also connected to an external receiver 300 via an isolation device 200. The isolation device 200 may be an isolation capacitor. One end of the isolation capacitor away from the high impedance state control circuit 110 may be connected to a filter assembly, where the filter assembly includes a first capacitor 201 and a first resistor 202 connected in parallel.

When the logic state of the target input signal a remains unchanged for a preset period of time and the output of the high-resistance control circuit 110 is in a high-resistance state, the pull-up refresh circuit 120 pulls up the output signal of the high-resistance control circuit 110 according to the target input signal a, or the pull-down refresh circuit 130 pulls down the output signal of the high-resistance control circuit 110 according to the target input signal a, so as to obtain a refresh signal.

The preset duration may be related to an internal delay in the high impedance state control circuit 110, and may be set by those skilled in the art according to actual requirements.

For example, a first logic may represent a logic 0 (or low), and a second logic may represent a logic 1 (or high). Wherein those skilled in the art can implement the same functions in inverse logic through digital logic operations, and thus, specific logic state selection should not be construed as limiting the present application.

As an implementation, the high impedance control circuit 110 may be a special inverter with a delay function and an enable function. The pull-up refresh circuit 120 or the pull-down refresh circuit 130 may control the slope of the waveform of the output terminal of the high-resistance state control circuit 110 to be constant during the refresh process, for example, the output terminal of the high-resistance state control circuit 110 may be charged by the first constant current source 1202 in fig. 1 or discharged by the second constant current source 1302 in fig. 1. The constant current source may be realized by adjusting the reference current source of the integrated circuit in the form of a current mirror to a set current magnitude. The charging process of the constant current source may be controlled by the charging switch 1201, and the discharging process of the constant current source may be controlled by the discharging switch 1301.

The pull-up refresh circuit 120 and the pull-down refresh circuit 130 have similar structures, and the pull-up/pull-down refresh circuit 130 can slowly charge/discharge the output terminal of the high-resistance state control circuit 110 to realize pull-up/pull-down operation, and a signal obtained through the pull-up/pull-down operation can be regarded as an initial refresh signal c. The initial refresh signal c may be converted into a pre-refresh signal d that can be recognized by the receiver 300 after passing through the isolation device 200, and the receiver 300 may decode the signal edges of the pre-refresh signal d to obtain the acknowledge signal.

For convenience of description, the initial refresh signal c and the pre-refresh signal d are collectively referred to as refresh signals hereinafter, and differ only in whether the waveform of the initial refresh signal c and the waveform of the pre-refresh signal d exhibit positive correlation in slope through the effect of the isolation device 200.

With the above-described refresh circuit, the high-resistance refresh circuit can be pulled up by the pull-up refresh circuit 120 or pulled down by the pull-down refresh circuit 130 under the condition of outputting the high-resistance state, so that the refresh operation in the high-resistance state can be completed. This enables the refresh circuit to send a refresh signal to the receiver 300 in a high resistance state while the logic state of the target input signal a remains unchanged for a period of time. The receiver 300 is capable of receiving the refresh signal before the "next signal edge" of the actual target input signal a is not received (before the target input signal a is changed), and further obtaining a confirmation signal according to the signal edge of the refresh signal, so as to realize data confirmation or correction in advance.

On the one hand, the circuit in the high-impedance state can reduce the influence of the transmitting end on the receiving end, and even if part of the circuit on the transmitting end side is powered off due to accidents, the receiver 300 side can know that the transmitting end is abnormal according to the refresh signal in time. On the other hand, even if the data rate of the input signal is low, the interval time between two adjacent signal edges of the input signal is long, and under the condition that the system causes interference to the receiving end due to external interference, the receiving end timely corrects and recovers the data according to the refresh signal of the refresh circuit.

Alternatively, as shown in fig. 1, the high impedance state control circuit 110 may include: a first delay 111, a refresh controller 112, a high impedance state control module 113.

The first delay unit 111 is configured to generate a first delay signal a1 having undergone a first delay D1 according to the target input signal a.

The refresh controller 112 is configured to output a refresh enable signal b according to the target input signal a.

The high-resistance state control module 113 is configured to output a high-resistance state according to the first delay signal a1 and the refresh enable signal b.

Typically, the logic within the refresh controller 112 may have a second delay D2, but both the first delay D1 and the second delay D2 are small and have no significant effect on the operation of the system.

In some specific application scenarios, for example, in the case where the operation time of the system is long enough, a phenomenon may occur in which the refresh process overlaps with the active edge of the target input signal a, that is, in the case where the system is performing a refresh operation at the time when the active edge of the target input signal a occurs. For the aforementioned specific application scenario, in order to improve the refresh accuracy, it may be set that the first logic circuit 1131 may receive the refresh enable signal b earlier than the first delay signal a 1. For example, the duration of the first delay D1 may be increased by adding a delay means such that the second delay D2 of the refresh controller 112 may be less than the duration of the first delay D1.

In other examples, the refresh may be accomplished without setting the latency constraint of D1> D2.

The high-resistance state control circuit 110 can obtain the refresh enable signal b based on the target input signal a, and the high-resistance state control module 113 can output a high-resistance state according to the refresh enable signal b and the first delay signal a1, so that the refresh can be realized by means of a hardware circuit, and the high-resistance state control circuit is more suitable for complex working conditions.

The refresh enable signal b may be sent to the high-resistance state control module 113 to output a high-resistance state, and may also be sent to the pull-up refresh circuit 120 and the pull-down refresh circuit 130, so that the pull-up refresh circuit 120 may perform linear slow charging on the output node of the high-resistance state control circuit 110 according to the target input signal a and the refresh enable signal b, or the pull-down refresh circuit 130 may perform linear slow discharging on the output node of the high-resistance state control circuit 110 according to the target input signal a and the refresh enable signal b, thereby implementing refreshing and obtaining a refresh signal.

As one embodiment, the refresh enable signal b may determine the logic state by:

the refresh controller 112 periodically converts the logic state of the refresh enable signal b to a first logic and then returns to a second logic while the target input signal a remains unchanged.

The refresh controller 112 transitions the logic state of the refresh enable signal b to the second logic when the target input signal a changes.

Based on the logic state change principle of the refresh enable signal b, the refresh controller 112 may generate the refresh enable signal b regardless of whether the logic state of the target input signal a is changed, but the logic state may be different.

The time for performing the refresh operation can be determined by the refresh enable signal b and the target input signal a outputted from the refresh controller 112. In one example, the phase in which the logic state of the refresh control signal appears "second logic-first logic-second logic" may be taken as the phase in which the refresh action is performed.

As one implementation, as shown in fig. 2, the high impedance state control module 113 may include a first logic circuit 1131, a second logic circuit 1132, and a target inverter 1133.

The first logic circuit 1131 is configured to output the first inversion control signal f according to the first delay signal a1 and the refresh enable signal b.

The second logic circuit 1132 is configured to output the second inverted control signal g according to the first delay signal a1 and the refresh enable signal b.

The target inverter 1133 is configured to output a high impedance state according to the first inversion control signal f and the second inversion control signal g.

A plurality of drivers may be provided at the input terminal of the target inverter 1133 to enhance the response speed of the target inverter 1133.

Wherein, for the first logic circuit 1131, the second logic circuit 1132:

when the refresh enable signal b is a first logic, the logic state of the first inversion control signal f outputted by the first logic circuit 1131 is a second logic, and the logic state of the first inversion control signal f outputted by the second logic circuit 1132 is a first logic.

When the refresh enable signal b is the second logic, the logic states of the first inversion control signal f and the second inversion control signal g are the same, and the logic states of the first inversion control signal f and the second inversion control signal g are determined according to the target input signal a. For example, when the refresh enable signal b is the second logic, the logic states of the first and second inverted control signals f and g may be the same as the logic state of the target input signal a.

This enables the target inverter 1133 to output a high resistance state based on two signals.

To implement the above principle, in one example, the specific structure of the high-impedance state control circuit 110 may be as shown in fig. 5. As shown in fig. 5, the first logic circuit 1131 may include an nor gate and an or gate, where the refresh enable signal b is inverted by the nor gate and then is input to the or gate together with the target input signal a to obtain the first inverted control signal f. The second logic circuit 1132 may include an and gate to which the refresh enable signal b is input in combination with the target input signal a to obtain the second inverted control signal g.

Since equivalent alternatives to digital logic devices are numerous, in some examples, one skilled in the art may employ other forms of devices to build the first logic circuit 1131, the second logic circuit 1132.

As shown in fig. 2, the target inverter 1133 may include a first PMOS transistor P1 (P-channel metal-oxide-semiconductor field effect transistor, abbreviated as PMOS transistor), and a first NMOS transistor N1 (N-channel metal-oxide-semiconductor field effect transistor, abbreviated as NMOS transistor).

The gate of the first PMOS transistor P1 is connected to the first logic circuit 1131, the source of the first PMOS transistor P1 is connected to the power supply, and the drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1.

The gate of the first NMOS transistor N1 is connected to the second logic circuit 1132, and the source of the first NMOS transistor N1 is grounded.

The target inverter 1133 can output a high-resistance state according to the signals output by the first logic circuit 1131 and the second logic circuit 1132, that is, the first NMOS transistor N1 and the first PMOS transistor P1 are in the off state at the same time. And in the case that the target inverter 1133 outputs a high resistance state, the pull-up/pull-down refresh circuit 130 is allowed to perform linear slow charge/discharge on the output node (the drain of the first PMOS transistor P1 and the drain of the first NMOS transistor N1) of the target inverter 1133, so as to obtain a refresh signal. Because the output node is in a high resistance state, the node cannot obtain effective charge replenishment from ground or a power supply, and the voltage of the node can be effectively regulated by only needing small charge and discharge current, so that the energy consumption in the refreshing process is very low.

As shown in fig. 3, the pull-up refresh circuit 120 may include a first current mirror 121, a pull-up control circuit 122.

The two input terminals of the pull-up control circuit 122 are respectively used for receiving the refresh enable signal b and the target input signal a.

An output terminal of the pull-up control circuit 122 is connected to the first current mirror 121.

The first current mirror 121 is configured to linearly charge the output terminal of the high impedance state control circuit 110.

The pull-up control circuit 122 may serve as a control switch of the first current mirror 121, and the pull-up control circuit 122 may control the first current mirror 121 to be turned on or off according to the refresh enable signal b and the target input signal a. When the first current mirror 121 is turned on, the output terminal of the high impedance state control circuit 110 is charged.

The first current mirror 121 may include a second PMOS transistor P2 and a third PMOS transistor P3.

The source electrode of the second PMOS tube P2 is connected with a power supply, the drain electrode of the second PMOS tube P2 is connected with the output end of the high-resistance state control circuit 110, the grid electrode of the second PMOS tube P2 is connected with the grid electrode of the third PMOS tube P3, and the second PMOS tube P2 is also connected with the first current source U1. The source electrode of the third PMOS tube P3 is connected with a power supply, and the drain electrode and the grid electrode of the third PMOS tube P3 are connected with the first current source U1.

When the first current mirror 121 is turned on, the second PMOS transistor P2 charges the output terminal of the high-resistance control circuit 110 with a constant current, so that the output voltage of the high-resistance control circuit 110 increases slowly.

Optionally, the pull-up control circuit 122 may include a third logic circuit 1221, a pull-up switch tube P4.

The control end of the pull-up switching tube P4 is connected to the output end of the third logic circuit 1221, and the output end of the pull-up switching tube P4 is connected to the first current mirror 121.

A third logic circuit 1221 for outputting a pull-up refresh control signal e1 having a logic state of the second logic when the target input signal a is the second logic and the refresh enable signal b is the first logic;

the third logic circuit 1221 is further configured to output a pull-up refresh control signal e1 having a logic state of the first logic when the target input signal a is not the second logic and/or the refresh enable signal b is not the first logic.

There are a variety of specific implementations of the third logic circuit 1221. In one implementation, the third logic 1221 may include an NOT gate, an AND gate. After passing through the NOT gate, the refresh enabling signal b is input into the AND gate together with the target input signal a, and the pull-up refresh control signal e1 is obtained. In other implementations, the NOT gate, AND gate may be combined from other underlying digital logic devices.

The pull-up switching tube P4 may be a fourth PMOS tube, which serves as a switch of the first current mirror 121. The source electrode of the fourth PMOS transistor is connected to the power supply, the drain electrode is connected to the first current source U1, and the gate electrode is connected to the output terminal of the third logic circuit 1221.

When the logic state of the pull-up refresh control signal e1 is the second logic, the first current mirror 121 is turned on to perform linear slow charging on the output terminal of the high-resistance control circuit 110. When the logic state of the pull-up refresh control signal e1 is the first logic, the first current mirror 121 is turned off, and the voltage of the output terminal of the high-resistance control circuit 110 is no longer controlled. Through the above implementation process, the pull-up refresh control signal e1 output by the third logic circuit 1221 controls the on or off of the pull-up switch transistor P4, and when the pull-up switch transistor P4 is turned on, the first current mirror 121 is turned on to perform linear charging for the output terminal of the high-resistance state control circuit 110, and a rapidly changing signal edge can be formed after the charging is completed.

In one example, to enable refresh, the pull-up refresh control signal e1 is a logic 1 if and only if the target input signal a is a logic 1 and the refresh enable signal b is a logic 0, i.e., satisfies: pull-up refresh control signal e1= (NOT b) AND a.

Alternatively, as shown in FIG. 4, the pull-down refresh circuit 130 may be similar in structure to the pull-up refresh circuit 120. The pull-down refresh circuit 130 may include a second current mirror 131, a pull-down control circuit 132.

The two input terminals of the pull-down control circuit 132 are respectively used for receiving the refresh enable signal b and the target input signal a. An output terminal of the pull-down control circuit 132 is connected to the second current mirror 131.

The second current mirror 131 is used for linearly discharging the output terminal of the high-impedance state control circuit 110.

The pull-down control circuit 132 may serve as a control switch of the second current mirror 131, and the pull-down control circuit 132 may control the second current mirror 131 to be turned on or off according to the refresh enable signal b and the target input signal a. When the second current mirror 131 is turned on, the output terminal of the high-impedance state control circuit 110 is discharged.

The second current mirror 131 may include a second NMOS transistor N2 and a third NMOS transistor N3.

The source electrode of the second NMOS tube N2 is grounded, the drain electrode of the second NMOS tube N2 is connected with the output end of the high-resistance state control circuit 110, the grid electrode of the second NMOS tube N2 is connected with the grid electrode of the third NMOS tube N3, and the second NMOS tube N2 is also connected with the second current source U2. The source electrode of the third NMOS tube N3 is grounded, and the drain electrode and the grid electrode of the third NMOS tube N3 are connected with the second current source U2.

When the second current mirror 131 is turned on, the second NMOS N2 discharges the output terminal of the high-resistance control circuit 110 with a constant current, so that the output voltage of the high-resistance control circuit 110 decreases slowly.

Alternatively, the pull-down control circuit 132 may include a fourth logic circuit 1321, a pull-down switching tube N4. The control end of the pull-down switching tube N4 is connected to the output end of the fourth logic circuit 1321, and the output end of the pull-down switching tube N4 is connected to the second current mirror 131.

The fourth logic circuit 1321 is configured to output a pull-down refresh control signal e2 having a logic state of the first logic when the target input signal a is the first logic and the refresh enable signal b is the first logic.

The fourth logic circuit 1321 is further configured to output a pull-down refresh control signal e2 having a logic state of the second logic when the target input signal a is not the first logic and/or the refresh enable signal b is not the first logic.

As an implementation of the fourth logic 1321, the fourth logic 1321 may be an or gate. The refresh enable signal b and the target input signal a are input to the or gate together, resulting in the pull-down refresh control signal e2. In other implementations, the OR gate may be combined from other underlying digital logic devices, such as a NAND gate, to implement the OR gate function.

The pull-down switching tube N4 may be a fourth NMOS tube, which serves as a switch of the second current mirror 131. The source of the fourth NMOS transistor is grounded, the drain is connected to the second current source U2, and the gate is connected to the output terminal of the fourth logic circuit 1321.

When the logic state of the pull-down refresh control signal e2 is the first logic state, the second current mirror 131 is turned on to perform linear slow discharge on the output terminal of the high-resistance control circuit 110. When the logic state of the pull-down refresh control signal e2 is the second logic, the second current mirror 131 is turned off, and the voltage of the output terminal of the high-resistance control circuit 110 is no longer controlled.

In one example, to enable refresh, the pull-down refresh control signal e2 is a logic 0 if and only if the target input signal a is a logic 0 and the refresh enable signal b is a logic 0, i.e., satisfies: pull down refresh control signal e2=aor b.

The operation of the aforementioned refresh circuit will be described below with reference to fig. 5.

In the refresh circuit shown in fig. 5, the high impedance control circuit 110 may include an input port for receiving the target input signal a, an output port for transmitting the initial refresh signal c to the isolation device 200, and an enable port for receiving the refresh enable signal b.

When the refresh enable signal b received by the enable port is a first logic, the gate voltage of the first PMOS transistor P1 is a voltage corresponding to logic 1 (for example, may be a power supply voltage), and the gate voltage of the first NMOS transistor N1 is a voltage corresponding to logic 0 (for example, a voltage corresponding to a ground signal). When the refresh enable signal b received by the enable port is the second logic, the gate voltage of the first PMOS transistor P1 and the gate voltage of the first NMOS transistor N1 have the same logic state, for example, the same logic state as the target input signal a. The target inverter 1133 formed by the first PMOS transistor P1 and the first NMOS transistor N1 can output a high-resistance state through the matching connection relationship of the first logic circuit 1131, the second logic circuit 1132, the first PMOS transistor P1 and the first NMOS transistor N1.

In the case of outputting a high resistance state, taking a refresh by a pull-up operation as an example, a specific procedure of the pull-down operation may be described with reference to the pull-up procedure. The third logic circuit 1221 in the pull-up refresh circuit 120 sends a pull-up refresh control signal e1 to the second PMOS transistor P2 according to the refresh enable signal b and the target input signal a. When the pull-up refresh control signal e1 is logic 1, the first current mirror 121 is turned on to linearly and slowly charge the output node of the target inverter 1133. During the charging process, the slope of the signal waveform at the output end of the high impedance state control circuit 110 is constant, such as waveform "(1)" in fig. 6. After the refresh operation is completed, the initial refresh signal c can be obtained, and the waveforms are shown as (1) (linear) and (4) (fast falling edge) in fig. 6. After the initial refresh signal c is sent to the isolation device 200, a pre-refresh signal d can be obtained at the end of the isolation device 200 away from the high-resistance state control circuit 110, and the waveform of the pre-refresh signal d is shown in fig. 7.

In practical application scenarios, the time-varying process of the voltage at the output terminal of the high impedance control circuit 110 from logic 0 to logic 1 may correspond to three waveforms, such as (1), (2) and (3) in fig. 6. The convex waveform (2) and the concave waveform (3) in fig. 6 may be caused by poor linear charging effect or non-linear charging. For the upward convex waveform (2) and the downward concave waveform (3), the waveforms shown in fig. 7 can be obtained after passing through the isolation device 200. The dashed lines corresponding to "511" and "512" represent the signal threshold set by the comparator in the receiver 300. If the extremum of the convex waveform (2) and the concave waveform (3) reaches the signal threshold in the comparator, false triggering may occur, so that the receiver 300 analyzes to one signal edge more than once, thereby affecting the refresh accuracy. Therefore, to improve the refresh accuracy, a person skilled in the art may change the signal threshold in the comparator, or select the pull-up refresh circuit 120 with good linear charging effect as much as possible to perform the pull-up operation, so that the slope of the signal waveform at the output end of the high-impedance state control circuit 110 is as unchanged as possible during the charging process.

The receiver 300 can analyze the negative pulse codes corresponding to the fast falling edge (4) according to the waveforms (1) and (4) by the waveform (1) with the slope basically maintained unchanged and the fast falling edge waveform (4).

In the refresh process of the refresh circuit, the operation waveforms of the respective signals are as shown in fig. 8.

When the logic state of the target input signal a changes, the receiver 300 side can recognize a primary signal edge, such as "600" in fig. 8, from which corresponding data can be parsed.

During the T1 period (604, just before the signal edge of the target input signal a remains unchanged), the refresh enable signal b has a transition from logic 1 to logic 0 and then back to logic 1, corresponding to the waveform "605" in fig. 8. In a period t1 corresponding to the waveform 605, the pull-up refresh control signal e1 output by the third logic circuit 1221 in the pull-up refresh circuit 120 is firstly converted into logic 1 and then is recovered to logic 0, the pull-up switch tube P4 is turned on, the first current mirror 121 is turned on, the second PMOS tube P2 charges the output end of the high-resistance state control circuit 110 with the constant current I, so that the output end of the high-resistance state control circuit 110 can obtain the waveform 601 in fig. 8, and the receiver 300 at one end of the isolation device 200 can recognize the signal edge 603 in fig. 8, and the logic state of 603 can be determined according to the logic state 601. Thus, the process of completing the refresh operation just before the signal edge 604 of the target input signal a is reached is implemented, and the receiver 300 can obtain 603 the signal edge before the signal edge 604 is detected, so as to implement the confirmation and correction of the signal edge 600.

Similarly, in other duty cycles of the refresh enable signal b, it may be that the pull-down refresh circuit 130 operates to perform a pull-down process (discharge), so as to obtain the initial refresh signal c at the output of the high-impedance control circuit 110, and the waveform is similar to 602 in fig. 8, so that the receiver 300 side can obtain the corresponding signal edge for analysis and confirmation.

In general, in the principle shown in fig. 8, the logic state of the refresh enable signal b is restored to logic 1 before the logic state of the target input signal a is changed, so that the delay condition between D1 and D2 can be ignored. If the signal edge 605 generated when the logic state of the target input signal a is changed is exactly within the refresh operation time t1 of a refresh enable signal b, that is, 604 the signal edge is within the time period t1, the delay condition of D1> D2 needs to be satisfied, so as to avoid refresh errors or refresh failure and improve the refresh accuracy.

In other embodiments, isolation device 200 may be incorporated into a refresh circuit to improve system stability.

Second embodiment

Based on the same inventive concept, the embodiment of the application also provides a refreshing method, which can be applied to a refreshing system. The refresh system may include a transmitter 100, a receiver 300, with the transmitter 100 and the receiver 300 connected by an isolation device 200. Wherein the isolation device 200 may be an isolation capacitor.

The refresh circuit provided in the foregoing first embodiment may be included in the transmitter 100. For specific details of the refresh circuit, please refer to the related description in the foregoing first embodiment, and the description is omitted herein.

As shown in fig. 9, the refresh method in the present embodiment includes S21 to S24.

S21: the transmitter 100 receives a target input signal a, the logic state of which is either a first logic or a second logic, the first logic and the second logic being opposite logic states.

S22: when the logic state of the target input signal a is maintained unchanged for a preset period of time, the transmitter 100 performs pull-up or pull-down processing according to the target input signal a through the refresh circuit when the refresh circuit is in a high-resistance state, so as to obtain a refresh signal.

The high-impedance state output of the high-impedance state control circuit 110 may indicate that the refresh circuit is in a high-impedance state, i.e., the refresh circuit is in a high-impedance state.

The preset time period may be set by a person skilled in the art according to actual needs, for example, the preset time period may be set according to the time periods t1, D2, etc. in the foregoing embodiment.

S23: the receiver 300 receives the refresh signal through the isolation device 200.

S24: the receiver 300 parses the refresh signal to obtain an acknowledge signal.

Wherein an initial refresh signal c may be generated by the refresh circuit and sent to the isolation device 200, which is converted into a pre-refresh signal d by the isolation device 200 such that the receiver 300 can receive and recognize the pre-refresh signal d. The receiver 300 may parse the acknowledge signal according to the signal edge of the pre-refresh signal d.

By the above-mentioned refreshing method, when the logic state of the target input signal a is unchanged or the data rate is low within a period of time, the refreshing circuit completes the refreshing action in the high-resistance state according to the target input signal a, so as to obtain a refreshing signal, so that the receiver 300 receives the refreshing signal through the isolation device 200, and obtains a confirmation signal based on the analysis of the refreshing signal. Even if some circuits on the transmitter 100 side are unexpected or the system is disturbed, the receiver 300 side can react according to the refresh signal, so that subsequent data correction and recovery can be performed.

Optionally, the refresh circuit may include: a high resistance state control circuit 110, a pull-up refresh circuit 120, and a pull-down refresh circuit 130. The high resistance state control circuit 110 includes a refresh controller 112 for generating a refresh enable signal b.

The pull-up refresh circuit 120 may perform a pull-up process on a node in a high-resistance state in the refresh circuit according to the target input signal a and the refresh enable signal b under the combined action of the target input signal a and the refresh enable signal b, so as to obtain a refresh signal. The pull-down refresh circuit 130 may also perform a pull-down process on the node in the high-resistance state in the refresh circuit according to the target input signal a and the refresh enable signal b under the combined action of the target input signal a and the refresh enable signal b, so as to obtain the refresh signal.

In one embodiment, the step S22 may include:

when the refresh circuit is in a high-resistance state, the pull-up refresh circuit 120 performs a pull-up process when the target input signal a is the second logic and the refresh enable signal b is the first logic, so as to obtain a refresh signal.

Or, when the refresh circuit is in a high-resistance state, the pull-down refresh circuit 130 performs pull-down processing when the target input signal a is the first logic and the refresh enable signal b is the first logic, so as to obtain the refresh signal.

Wherein various combinations of basic digital logic devices may be utilized to implement the logic control process described above.

Therefore, whether to perform the refresh action or not can be determined by combining logic states of the target input signal a and the refresh enabling signal b, and the refresh time is determined.

Optionally, the high resistance state control circuit 110 in the refresh circuit may include a first delay 111, a refresh controller 112, a first logic circuit 1131, a second logic circuit 1132, and a target inverter 1133.

For the high resistance state of the refresh circuit, it can be obtained in the following way, including S31-S34.

S31: the refresh controller 112 transmits a refresh enable signal b to the first logic circuit 1131 and the second logic circuit 1132 according to the target input signal a.

S32: the first delay 111 transmits a first delay signal a1 to the first logic circuit 1131 and the second logic circuit 1132 according to the target input signal a.

S33: the first logic circuit 1131 outputs a first inversion control signal f according to the refresh enable signal b and the first delay signal a1, and the second logic circuit 1132 outputs a second inversion control signal g according to the refresh enable signal b and the first delay signal a1.

S34: the target inverter 1133 receives the first and second inverted control signals f and g and outputs a high resistance state according to the first and second inverted control signals f and g.

When the refresh enable signal b is a first logic, the logic state of the first inversion control signal f output by the first logic circuit 1131 is a second logic, and the logic state of the first inversion control signal f output by the second logic circuit 1132 is a first logic; when the refresh enable signal b is the second logic, the logic states of the first inversion control signal f and the second inversion control signal g are the same, and the logic states of the first inversion control signal f and the second inversion control signal g are determined according to the target input signal a.

Thus, the refresh process can be completed based on a refresh circuit capable of outputting a high resistance state.

Since the refresh enable signal b is involved in the process of obtaining the high resistance state and in the process of determining, in particular, whether to pull up or pull down, a subsequent refresh action is performed based on the logic state of the refresh enable signal b. Thus, the refresh method may further include:

the logic state of the refresh enable signal b is determined before the pull-up or pull-down process is performed.

As an embodiment, the logic state of the refresh enable signal b may be determined by:

The logic state of the refresh enable signal b can thus be determined and refreshed based on the logic states of the refresh enable signal b and the target input signal a.

Third embodiment

The present embodiment provides a chip including the refresh circuit provided in the foregoing first embodiment.

The chip may be a digital isolation chip, for example, a capacitive digital isolator.

For specific details of the refresh circuit in this embodiment, please refer to the related description in the foregoing first embodiment, and the details are not repeated here.

Through the chip, the data transmission accuracy can be improved when the chip is used for data transmission, and the system robustness is improved. Even if the system is unexpected, the receiver 300 can perform data confirmation and correction according to the refresh signal output by the chip in time.

Fourth embodiment

The present embodiment provides a data transmission system 10, and as shown in fig. 10, the data transmission system 10 includes a transmitter 100 and a receiver 300. The transmitter 100 and the receiver 300 are connected by an isolation device 200.

The transmitter 100 includes the refresh circuit provided in the foregoing first embodiment, so that the data transmission system 10 is provided with a data refresh function.

With the data transmission system 10 described above, the transmitter 100 can transmit the refresh signal to the receiver 300 by using the refresh circuit, and the receiver 300 can receive the refresh signal through the isolation device 200 and perform subsequent parsing processing to obtain the acknowledgement signal. Even if the interval time between two adjacent edge signals of the input signal is long, the receiver 300 side can perform data confirmation based on the refresh signal, so as to correct and recover data errors caused by some unexpected situations in time.

In the embodiments provided in this application, it should be understood that the embodiments described above are merely illustrative, for example, the division of modules and units in a circuit is merely a logic function division, and there may be another division manner in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. In addition, the units described as separate components may or may not be physically separate. Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A refresh circuit, the refresh circuit comprising: a high resistance state control circuit, a pull-up refreshing circuit and a pull-down refreshing circuit;

when the logic state of the target input signal is kept unchanged within a preset time period and the output of the high-resistance state control circuit is in a high-resistance state, the pull-up refreshing circuit pulls up the output signal of the high-resistance state control circuit according to the target input signal, or the pull-down refreshing circuit pulls down the output signal of the high-resistance state control circuit according to the target input signal to obtain a refreshing signal;

the high-resistance state control circuit comprises a first delayer, a refresh controller and a high-resistance state control module;

the first delayer is used for generating a first delay signal subjected to first delay according to the target input signal;

the refresh controller is used for outputting a refresh enabling signal according to the target input signal;

the high-resistance state control module is used for outputting a high-resistance state according to the first delay signal and the refresh enabling signal.

2. The refresh circuit of claim 1, wherein the high resistance state control module comprises a first logic circuit, a second logic circuit, a target inverter;

The first logic circuit is used for outputting a first inversion control signal according to the first delay signal and the refresh enabling signal;

the second logic circuit is used for outputting a second inversion control signal according to the first delay signal and the refresh enabling signal;

the target inverter is used for outputting a high-resistance state according to the first inversion control signal and the second inversion control signal.

3. The refresh circuit of claim 2, wherein the target inverter comprises a first PMOS transistor, a first NMOS transistor;

the grid electrode of the first PMOS tube is connected with the first logic circuit, the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube;

the grid electrode of the first NMOS tube is connected with the second logic circuit, and the source electrode of the first NMOS tube is grounded.

4. The refresh circuit of claim 1, wherein the pull-up refresh circuit comprises a first current mirror, a pull-up control circuit;

the two input ends of the pull-up control circuit are respectively used for receiving a refresh enabling signal and the target input signal;

the output end of the pull-up control circuit is connected with the first current mirror;

The first current mirror is used for carrying out linear charging on the output end of the high-resistance state control circuit.

5. The refresh circuit of claim 4, wherein the pull-up control circuit comprises a third logic circuit, a pull-up switching tube;

the control end of the pull-up switching tube is connected with the output end of the third logic circuit, and the output end of the pull-up switching tube is connected with the first current mirror;

the third logic circuit is configured to output a pull-up refresh control signal having a logic state of the second logic when the target input signal is the second logic and the refresh enable signal is the first logic;

the third logic circuit is further configured to output a pull-up refresh control signal having a logic state of the first logic when the target input signal is not the second logic and/or the refresh enable signal is not the first logic.

6. The refresh circuit of claim 1, wherein the refresh circuit comprises a refresh circuit,

the pull-down refreshing circuit comprises a second current mirror and a pull-down control circuit;

the two input ends of the pull-down control circuit are respectively used for receiving a refresh enabling signal and the target input signal;

the output end of the pull-down control circuit is connected with the second current mirror;

The second current mirror is used for carrying out linear discharge on the output end of the high-resistance state control circuit.

7. The refresh circuit of claim 6, wherein the refresh circuit comprises a refresh circuit,

the pull-down control circuit comprises a fourth logic circuit and a pull-down switching tube;

the control end of the pull-down switching tube is connected with the output end of the fourth logic circuit, and the output end of the pull-down switching tube is connected with the second current mirror;

the fourth logic circuit is configured to output a pull-down refresh control signal having a logic state of the first logic when the target input signal is the first logic and the refresh enable signal is the first logic;

the fourth logic circuit is further configured to output a pull-down refresh control signal having a logic state of a second logic when the target input signal is not the first logic and/or the refresh enable signal is not the first logic.

8. A refresh method applied to a refresh system, the refresh system comprising a transmitter and a receiver, the transmitter and the receiver being connected by an isolation device, the transmitter comprising the refresh circuit of any one of claims 1-7, the method comprising:

the receiver receives the refresh signal through the isolation device;

9. The refresh method of claim 8, wherein the refresh circuit comprises: a high resistance state control circuit, a pull-up refreshing circuit and a pull-down refreshing circuit; the high-resistance state control circuit comprises a refresh controller for generating a refresh enabling signal;

and when the refresh circuit is in a high resistance state, carrying out pull-up or pull-down processing on the target input signal by the refresh circuit to obtain a refresh signal, wherein the method comprises the following steps of:

when the refresh circuit is in a high-resistance state, the pull-up refresh circuit performs pull-up processing when the target input signal is in a second logic state and the refresh enabling signal is in a first logic state, so as to obtain a refresh signal;

10. The refresh method of claim 8, wherein the high-impedance control circuit in the refresh circuit comprises a first delay, a refresh controller, a first logic circuit, a second logic circuit, a target inverter;

the high resistance state of the refresh circuit is obtained by:

the refresh controller sends a refresh enabling signal to the first logic circuit and the second logic circuit according to the target input signal;

the first delay device sends a first delay signal to the first logic circuit and the second logic circuit according to the target input signal;

the first logic circuit outputs a first inversion control signal according to the refresh enable signal and the first delay signal, and the second logic circuit outputs a second inversion control signal according to the refresh enable signal and the first delay signal;

the target inverter receives the first inversion control signal and the second inversion control signal and outputs a high-resistance state according to the first inversion control signal and the second inversion control signal;

When the refresh enabling signal is a first logic, the logic state of a first inversion control signal output by the first logic circuit is a second logic, and the logic state of a first inversion control signal output by the second logic circuit is the first logic;

when the refresh enable signal is a second logic, logic states of the first inversion control signal and the second inversion control signal are the same, and the logic states of the first inversion control signal and the second inversion control signal are determined according to the target input signal.

11. The refresh method of claim 10, wherein the logic state of the refresh enable signal is determined by:

12. A chip comprising the refresh circuit of any one of claims 1-7.

13. A data transmission system, the system comprising a transmitter, a receiver;

the transmitter comprising the refresh circuit of any one of claims 1-7;

The transmitter and the receiver are connected through an isolation device.

14. The data transmission system of claim 13, wherein the isolation device is an isolation capacitor.