CN112152594B - EFUSE programming method, EFUSE programming circuit and electronic device - Google Patents
EFUSE programming method, EFUSE programming circuit and electronic device Download PDFInfo
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Abstract
The application provides an EFUSE programming method, an EFUSE programming circuit and an electronic device. The programming method comprises the following steps: generating a programming voltage, wherein the programming voltage is greater than or equal to the fusing voltage of EFUSE; and programming the EFUSE by using a programming voltage. According to the scheme, the programming voltage is generated firstly, and then the EFUSE is programmed by adopting the programming voltage, and because the EFUSE is programmed to be larger than or equal to the fusing voltage of the EFUSE, the EFUSE to be programmed can be ensured to be completely programmed successfully, the problem that the programming voltage is readjusted under the condition that the EFUSE is not programmed successfully is avoided, the programming efficiency of the EFUSE is improved, and the success rate of the EFUSE programming is ensured.
Description
Technical Field
The application relates to the field of EFUSE programming, in particular to an EFUSE programming method, an EFUSE programming circuit and an electronic device.
Background
In the existing EFUSE programming technology, instrument equipment is generally adopted to generate a pulse signal with a certain voltage amplitude as EFUSE programming voltage to realize the programming of EFUSE, and once EFUSE programming fails, the amplitude of the pulse signal needs to be readjusted, so that the EFUSE programming efficiency is low.
Disclosure of Invention
The present application mainly aims to provide an EFUSE programming method, an EFUSE programming circuit, and an electronic device, so as to solve the problem of low EFUSE programming efficiency in the prior art.
In order to achieve the above object, according to an aspect of the present application, there is provided an EFUSE programming method, including: generating a programming voltage, wherein the programming voltage is greater than or equal to a fusing voltage of EFUSE; and programming the EFUSE by adopting the programming voltage.
Further, generating a programming voltage includes: detecting whether the EFUSE is fused in real time; determining that the programming voltage is greater than or equal to the fusing voltage of the EFUSE in the case that the EFUSE is detected to be fused; in the case that it is detected that the EFUSE is not blown, increasing the magnitude of the programming voltage until the EFUSE is blown.
According to still another aspect of the present application, there is provided an EFUSE programming circuit including: the pulse shaper is provided with a first input end and an output end, the first input end of the pulse shaper is used for inputting a pulse signal, the amplitude of the pulse signal is a first voltage, the output end of the pulse shaper is used for outputting a programming voltage, the programming voltage is used for programming EFUSE, the amplitude of the programming voltage is a second voltage, and the second voltage is larger than or equal to the fusing voltage of the EFUSE.
Further, the EFUSE programming circuit further includes: and the detection unit is respectively electrically connected with the pulse shaper and the EFUSE and is used for detecting whether the EFUSE is fused in real time.
Further, the pulse shaper further has a second input terminal and a third input terminal, the second input terminal is used for inputting a control signal, the control signal is a voltage increasing signal or a voltage decreasing signal, the third input terminal is used for inputting a clock signal, and the pulse shaper shapes the pulse signal according to the control signal and the clock signal and outputs the programming voltage.
Further, the pulse shaper includes: the input end of the logic gate is used for inputting the control signal and the clock signal; the input end of the switch unit is electrically connected with the output end of the logic gate, the output end of the switch unit outputs an operation signal, the output signal of the output end of the logic gate is used for controlling the opening and closing of the switch unit, and the operation signal changes along with the state change of the switch unit; and the adder is provided with a first input end, a second input end and an output end, the first input end of the adder is the first input end of the pulse shaper, the second input end of the adder is electrically connected with the output end of the switching unit, and the output end of the adder is the output end of the pulse shaper.
Further, the switching unit includes a MOS transistor and/or a BJT.
Further, the logic gate comprises a NAND gate and an AND gate, the switch unit comprises a P-type MOS transistor and an N-type MOS transistor, the first input end of the NAND gate is used for inputting the clock signal, the second input end of the NAND gate is used for inputting the control signal, the control signal is the voltage increasing signal, the output end of the NAND gate is electrically connected with the grid electrode of the P-type MOS tube, the source electrode of the P-type MOS tube is electrically connected with a power supply end, the drain electrode of the P-type MOS tube is electrically connected with the drain electrode of the N-type MOS tube, the first input end of the AND gate is used for inputting the clock signal, the second input end of the AND gate is used for inputting the control signal, the control signal is the voltage decreasing signal, the output end of the AND gate is electrically connected with the grid electrode of the N-type MOS tube, the source electrode of the N-type MOS tube is grounded, and the drain electrode of the P-type MOS tube outputs the operation signal.
Further, the pulse shaper further comprises a first capacitor, a resistor and a second capacitor, wherein a first end of the first capacitor is electrically connected with the second input end of the adder, a second end of the first capacitor is electrically connected with the drain electrode of the P-type MOS transistor, a first end of the resistor is electrically connected with the drain electrode of the P-type MOS transistor, a second end of the resistor is electrically connected with a first end of the second capacitor, and a second end of the second capacitor is grounded.
Further, the second voltage is incremented.
According to another aspect of the present application, an electronic device is provided, which includes an EFUSE programming circuit, a pulse signal generator and a clock signal generator, wherein the EFUSE programming circuit is electrically connected to the pulse signal generator and the clock signal generator respectively, the pulse signal generator is configured to generate a pulse signal, the clock signal generator is configured to generate a clock signal, and the EFUSE programming circuit is any one of the EFUSE programming circuits.
Furthermore, the electronic device further comprises a control signal generator, the control signal generator is electrically connected with the EFUSE programming circuit, the control signal generator is used for generating a control signal, and the control signal is a voltage increasing type signal or a voltage decreasing type signal.
By applying the technical scheme of the application, the programming voltage is generated firstly, and then the EFUSE is programmed by adopting the programming voltage, and as the EFUSE is programmed to be larger than or equal to the fusing voltage of the EFUSE, the EFUSE to be programmed can be ensured to be completely programmed successfully, the problem of readjusting the programming voltage under the condition that the EFUSE is not successfully programmed is avoided, the programming efficiency of the EFUSE is improved, and the success rate of the EFUSE programming is ensured.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 shows a flow chart of an EFUSE method of programming according to an embodiment of the present application;
FIG. 2 shows an EFUSE write circuit schematic according to an embodiment of the present application;
FIG. 3 shows an EFUSE write circuit schematic according to another embodiment of the present application.
Wherein the figures include the following reference numerals:
01. a pulse shaper; 02. a detection unit; 03. EFUSE; 04. a NAND gate; 05. an AND gate; 06. an adder; 07. a driver.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, the EFUSE programming efficiency in the prior art is low, and in order to solve the problem of the low EFUSE programming efficiency, embodiments of the present application provide an EFUSE programming method, an EFUSE programming circuit, and an electronic device.
FIG. 1 shows a flow chart of an EFUSE programming method according to an embodiment of the present application. As shown in fig. 1, the programming method includes:
step S101, generating a programming voltage, wherein the programming voltage is greater than or equal to a fusing voltage of EFUSE;
and step S102, programming the EFUSE by using the programming voltage.
In the scheme, the writing voltage is generated firstly, and then the EFUSE is written by adopting the writing voltage, and as the EFUSE is written to be greater than or equal to the fusing voltage of the EFUSE, all the EFUSE to be written can be successfully written, the problem that the writing voltage is readjusted under the condition that the EFUSE is unsuccessfully written is avoided, the writing efficiency of the EFUSE is improved, and the success rate of the EFUSE is ensured.
Specifically, under the condition that a plurality of EFUSE are to be programmed, the fuse voltages of the EFUSE may be different, and in order to ensure that all the EFUSE are programmed successfully, the programming voltage may be greater than the maximum fuse voltage.
In one embodiment of the present application, generating a programming voltage includes: detecting whether the EFUSE is fused in real time; determining that the programming voltage is greater than or equal to the fusing voltage of the EFUSE when the EFUSE is detected to be fused; and under the condition that the EFUSE is not blown, increasing the amplitude of the programming voltage until the EFUSE is blown. The method comprises the steps of detecting whether the EFUSE is fused in real time, adjusting the programming voltage in real time, ensuring that all the EFUSE are successfully programmed at one time, avoiding the problem that all the EFUSE are required to be programmed again when a plurality of EFUSEs exist and one EFUSE is not successful, and improving the programming efficiency of the EFUSE.
An exemplary embodiment of the present application provides an EFUSE programming circuit, as shown in fig. 2, including: the pulse shaper 01 comprises a first input end and an output end, wherein the first input end of the pulse shaper 01 is used for inputting a pulse signal pul, the amplitude of the pulse signal pul is a first voltage, the output end of the pulse shaper 01 is used for outputting a programming voltage, the programming voltage is used for programming EFUSE03, the amplitude of the programming voltage is a second voltage, and the second voltage is larger than or equal to the fusing voltage of the EFUSE 03.
In the scheme, the input pulse signal is shaped by the pulse shaper, the programming voltage is output, and the output programming voltage is greater than or equal to the fusing voltage of the EFUSE, so that the EFUSE to be programmed can be ensured to be completely programmed successfully, the problem of readjusting the programming voltage under the condition that the EFUSE is not programmed successfully is solved, the programming efficiency of the EFUSE is improved, and the success rate of the EFUSE programming is ensured.
Specifically, under the condition that a plurality of EFUSE are to be programmed, the fuse voltages of the EFUSE may be different, and in order to ensure that all the EFUSE are programmed successfully, the programming voltage may be greater than the maximum fuse voltage.
In an embodiment of the present application, as shown in fig. 2, the EFUSE03 programming circuit further includes a detecting unit 02, and the detecting unit 02 is electrically connected to the pulse shaper 01 and the EFUSE03, respectively, for detecting whether the EFUSE03 is blown or not in real time. The pulse shaper 01 can adjust the magnitude of the programming voltage in real time according to the detection result of the detection unit 02, so as to satisfy that all EFUSE03 are successfully programmed.
In another embodiment of the present invention, as shown in fig. 2, the pulse shaper 01 further has a second input terminal and a third input terminal, the second input terminal is used for inputting a control signal ctrl, the control signal ctrl is a voltage increasing signal or a voltage decreasing signal, the third input terminal is used for inputting a clock signal clk, and the pulse shaper 01 shapes the pulse signal pul according to the control signal ctrl and the clock signal clk and outputs the programming voltage. That is, the pulse shaper 01 processes the control signal ctrl and the clock signal clk to output a programming voltage.
In yet another embodiment of the present application, as shown in fig. 2 and fig. 3, the pulse shaper 01 includes a logic gate, a switching unit, and an adder 06, wherein inputs of the logic gate are used for inputting the control signal and the clock signal clk; the input end of the switch unit is electrically connected with the output end of the logic gate, the output end of the switch unit outputs an operation signal, the output signal of the output end of the logic gate is used for controlling the opening and closing of the switch unit, and the operation signal changes along with the state change of the switch unit; the adder 06 has a first input terminal, a second input terminal, and an output terminal, the first input terminal of the adder 06 is the first input terminal of the pulse shaper 01, the second input terminal of the adder 06 is electrically connected to the output terminal of the switching unit, and the output terminal of the adder 06 is the output terminal of the pulse shaper 01. Namely, under the combined action of the logic gate, the switching unit and the adder 06, the programming voltage is output.
In another embodiment of the present application, the switch unit includes MOS transistors and/or BJTs, and the number and the connection relationship of the MOS transistors and the BJTs can be adjusted according to actual situations, so as to satisfy the EFUSE programming.
In one embodiment of the present application, as shown in fig. 3, the logic gate includes a nand 04 and an and 05, the switch unit includes a P-type MOS transistor P and an N-type MOS transistor N, a first input of the nand 04 is used for inputting the clock signal clk, a second input of the nand 04 is used for inputting the control signal, the control signal is the voltage-increasing signal up, an output of the nand 04 is electrically connected to a gate of the P-type MOS transistor P, a source of the P-type MOS transistor P is electrically connected to a power supply terminal HDVV, a drain of the P-type MOS transistor P is electrically connected to a drain of the N-type MOS transistor N, a first input of the and 05 is used for inputting the clock signal clk, a second input of the and 05 is used for inputting the control signal, the control signal is the voltage-decreasing signal down, an output of the and 05 is electrically connected to a gate of the N-type MOS transistor N, the source of the N-type MOS transistor N is grounded, and the drain of the P-type MOS transistor P outputs the operation signal.
In another embodiment of the present invention, as shown in fig. 3, the pulse shaper 01 further includes a first capacitor C1, a resistor R, and a second capacitor C2, wherein a first end of the first capacitor C1 is electrically connected to the second input terminal of the adder 06, a second end of the first capacitor C1 is electrically connected to the drain of the P-type MOS transistor P, a first end of the resistor R is electrically connected to the drain of the P-type MOS transistor P, a second end of the resistor R is electrically connected to the first end of the second capacitor C2, and a second end of the second capacitor C2 is grounded. An output signal CPOTU and a power supply terminal HDVV of the drain of the P-type MOS transistor P are represented as HVDD, schematic diagrams of CPOTU and HVDD are shown in fig. 3, an input signal of the positive input terminal of the adder 06 is represented as PSIN, and a schematic diagram of PSIN is shown in fig. 3, wherein the pulse signal pul and PSIN output an incremental programming voltage for programming EFUSE03 after being acted by the adder 06.
In an embodiment of the present application, as shown in fig. 3, the second voltage is increased, specifically, the second voltage is gradually increased, that is, the amplitude of the second voltage is continuously increased, and whether EFUSE03 is blown or not is detected in real time, in case that EFUSE03 is detected to be blown, it is determined that the second voltage has satisfied the requirement, and it is not necessary to continuously increase the amplitude of the second voltage, in case that there are a plurality of EFUSEs 03, the state of each EFUSE03 is detected in real time, and the amplitude of the second voltage is adjusted in real time according to whether EFUSE03 is blown or not.
In one embodiment of the present application, as shown in fig. 3, the EFUSE03 programming circuit further includes a driver 07, an input terminal of the driver 07 inputs the pulse signal pul, an output terminal of the driver 07 is connected to a negative input terminal of the adder 06, and an output terminal of the adder 06 outputs a programming signal, which is an incremental voltage signal.
In another exemplary embodiment of the present application, an electronic device is provided, which includes an EFUSE programming circuit, a pulse signal generator, and a clock signal generator, wherein the EFUSE programming circuit is electrically connected to the pulse signal generator and the clock signal generator, respectively, the pulse signal generator is configured to generate a pulse signal, the clock signal generator is configured to generate a clock signal, and the EFUSE programming circuit is any one of the EFUSE programming circuits. The electronic device is applied to shape the input pulse signal through the pulse shaper and output the programming voltage, and the output programming voltage is greater than or equal to the fusing voltage of the EFUSE, so that the EFUSE to be programmed can be ensured to be completely programmed successfully, the problem of readjusting the programming voltage under the condition that the EFUSE is not programmed successfully is solved, the programming efficiency of the EFUSE is improved, and the success rate of the EFUSE programming is ensured.
In another embodiment of the present application, the electronic apparatus further includes a control signal generator, the control signal generator is electrically connected to the EFUSE programming circuit, the control signal generator is configured to generate a control signal, and the control signal is a voltage increasing signal or a voltage decreasing signal. And processing the control signal, the pulse signal and the clock signal to obtain a programming signal, wherein the programming signal is used for programming the EFUSE.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) according to the EFUSE programming method, the programming voltage is generated firstly, then the programming voltage is adopted to program the EFUSE, and due to the fact that the EFUSE programming voltage is larger than or equal to the fusing voltage of the EFUSE, all EFUSE to be programmed can be guaranteed to be successfully programmed, the problem that the programming voltage is readjusted under the condition that the EFUSE is unsuccessfully programmed is avoided, the programming efficiency of the EFUSE is improved, and the success rate of the EFUSE programming is guaranteed.
2) The EFUSE programming circuit has the advantages that input pulse signals are shaped through the pulse shaper, programming voltage is output, and the output programming voltage is larger than or equal to the fusing voltage of the EFUSE, so that the EFUSE to be programmed can be completely programmed successfully, the problem that the programming voltage is readjusted under the condition that the EFUSE is not successfully programmed is solved, the programming efficiency of the EFUSE is improved, and the success rate of the EFUSE programming is ensured.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (7)
1. An EFUSE write circuit, comprising:
the pulse shaper is provided with a first input end and an output end, the first input end of the pulse shaper is used for inputting a pulse signal, the amplitude of the pulse signal is a first voltage, the output end of the pulse shaper is used for outputting a programming voltage, the programming voltage is used for programming EFUSE, the amplitude of the programming voltage is a second voltage, and the second voltage is larger than or equal to the fusing voltage of the EFUSE;
the EFUSE programming circuit further comprises:
the detection unit is electrically connected with the pulse shaper and the EFUSE respectively and is used for detecting whether the EFUSE is fused in real time;
the pulse shaper is also provided with a second input end and a third input end, the second input end is used for inputting a control signal, the control signal is a voltage increasing type signal or a voltage decreasing type signal, the third input end is used for inputting a clock signal, and the pulse shaper shapes the pulse signal according to the control signal and the clock signal and outputs the programming voltage;
the pulse shaper includes:
the input end of the logic gate is used for inputting the control signal and the clock signal;
the input end of the switch unit is electrically connected with the output end of the logic gate, the output end of the switch unit outputs an operation signal, the output signal of the output end of the logic gate is used for controlling the opening and closing of the switch unit, and the operation signal changes along with the state change of the switch unit;
and the adder is provided with a first input end, a second input end and an output end, the first input end of the adder is the first input end of the pulse shaper, the second input end of the adder is electrically connected with the output end of the switching unit, and the output end of the adder is the output end of the pulse shaper.
2. The EFUSE programming circuit of claim 1, wherein the switching unit comprises a MOS transistor and/or a BJT.
3. The EFUSE programming circuit of claim 1, wherein the logic gate comprises a NAND gate and an AND gate, the switch unit comprises a P-type MOS transistor and an N-type MOS transistor,
the first input end of the NAND gate is used for inputting the clock signal, the second input end of the NAND gate is used for inputting the control signal, the control signal is the voltage increasing type signal, the output end of the NAND gate is electrically connected with the grid electrode of the P type MOS tube, the source electrode of the P type MOS tube is electrically connected with a power supply end, the drain electrode of the P type MOS tube is electrically connected with the drain electrode of the N type MOS tube, the first input end of the AND gate is used for inputting the clock signal, the second input end of the AND gate is used for inputting the control signal, the control signal is the voltage decreasing type signal, the output end of the AND gate is electrically connected with the grid electrode of the N type MOS tube, the source electrode of the N type MOS tube is grounded, and the drain electrode of the P type MOS tube outputs the operation signal.
4. The EFUSE programming circuit of claim 3, wherein the pulse shaper further comprises a first capacitor, a resistor and a second capacitor, wherein a first terminal of the first capacitor is electrically connected to the second input terminal of the adder, a second terminal of the first capacitor is electrically connected to the drain of the P-type MOS transistor, a first terminal of the resistor is electrically connected to the drain of the P-type MOS transistor, a second terminal of the resistor is electrically connected to a first terminal of the second capacitor, and a second terminal of the second capacitor is grounded.
5. The EFUSE programming circuit of claim 1 wherein the second voltage is incremental.
6. An electronic device, comprising an EFUSE programming circuit, a pulse signal generator and a clock signal generator, wherein the EFUSE programming circuit is electrically connected to the pulse signal generator and the clock signal generator respectively, the pulse signal generator is used for generating a pulse signal, the clock signal generator is used for generating a clock signal, and the EFUSE programming circuit is the EFUSE programming circuit as claimed in any one of claims 1 to 5.
7. The electronic device of claim 6, further comprising a control signal generator electrically connected to the EFUSE programming circuit, the control signal generator configured to generate a control signal, wherein the control signal is a voltage increasing signal or a voltage decreasing signal.
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