CN103700404A - Erasing-writing operation method for EEPROM, erasing-writing control circuit and RFID tag chip - Google Patents
Erasing-writing operation method for EEPROM, erasing-writing control circuit and RFID tag chip Download PDFInfo
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- CN103700404A CN103700404A CN201210389986.7A CN201210389986A CN103700404A CN 103700404 A CN103700404 A CN 103700404A CN 201210389986 A CN201210389986 A CN 201210389986A CN 103700404 A CN103700404 A CN 103700404A
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Abstract
Belonging to the technical field of integrated circuit (IC) design, the invention provides an erasing-writing operation method for EEPROM (electrically erasable programmable read-only memory), an erasing-writing control circuit and an RFID tag chip. The erasing-writing control circuit is used for performing erasing-writing operation on the EEPROM, and includes a charge pump system and a verification circuit. The charge pump system is used for providing an erasing-writing operation high-voltage signal with stagewise increasable voltage. The verification circuit is used for verifying whether the EEPROM can achieve successful erasing-writing operation under the action of the erasing-writing operation high-voltage signal, and outputs a control signal to the charge pump system. If the verification circuit judges that the erasing-writing operation is unsuccessful, the control signal is output to make the voltage of the erasing-writing operation high-voltage signal increase stagewisely, and if the verification circuit judges that the erasing-writing operation is successful, the control signal is output to make the voltage of the charge pump system's erasing-writing operation high-voltage signal not increase. The erasing-writing operation method consists of the steps of stagewise voltage increase and verification.
Description
Technical field
The invention belongs to integrated circuit (IC) design field, relate to EEPROM (ElectricallyErasable Programmable Read-Only Memory, EEPROM (Electrically Erasable Programmable Read Only Memo)), relate in particular to that low-power consumption realizes erasable (erasing-programming) method of operating of EEPROM and for realizing the erasable control circuit of EEPROM of this erasable method of operating, and RFID (radio-frequency (RF) identification) label chip that comprises this EEPROM.
Background technology
RFID (radio-frequency (RF) identification) technology, ultrahigh frequency (UHF) RFID technology particularly, extensively be widely used in every field, for example, the fields such as sale of goods, transportation, production, waste management, postal tracking, aviation luggage management, vehicle toll management, traditional strip of paper shape code is because of shortcomings such as its storage capacity are little, can not rewrite, and in identification field, it is slowly substituted by rfid system.
At RFID label chip, particularly in the design of ultra-high frequency RFID label chip, high for the designing requirement of low-power consumption.Due to distance, with respect to high frequency (HF) RFID label chip, the energy that ultra-high frequency RFID label chip can obtain still less.To RFID label chip, writing fashionable, conventionally need to start charge pump circuit so that normally used storer-EEPROM-in RFID label chip is carried out to erasable operation, and the duration is very long, energy consumption is very big, so the design of low-power consumption EEPROM becomes one of difficult point of RFID label chip low power dissipation design, particularly becomes the technological difficulties in ultra-high frequency RFID label chip design.
As mentioned above, one of topmost form of memory that EEPROM is used as current RFID chip, its low power dissipation design becomes a main design direction and a difficult problem.A lot of enterprises have selected the new units such as MTP (Multi-Time-Programmable, multiple programmable) storer as R&D direction, avoid a difficult problem for EEPROM low power dissipation design.But EEPROM technical maturity, reliability is high, in the RFID label chip design of the large capacity of part, high reliability, still has irreplaceable demand, and its low power dissipation design becomes the difficult problem that must overcome, particularly the low power dissipation design under erasable operator scheme.
At present, the erasable method of operating of EEPROM is mainly: the higher high-voltage signal (for example 15V) of biasing from word-line/bit-line to storage unit, continue 1.5ms～2.5ms, and realize once erasable operation successfully, after erasable operation, there is no verification step.Because EEPROM comprises a plurality of storage unit, due to ubiquitous consistency problem, its erasable voltage is relatively dispersedly, in current this erasable method of operating, the size of high-voltage signal normally can make all storage unit substantially can both the successful voltage of erasable operation, thereby all substantially can once realize successfully erasable operation in the situation that not verifying.And this high-voltage signal can not be too high and cause memory device therefore to damage in erasable operation.
In the erasable operation of EEPROM, use high-voltage signal usually by charge pump circuit, to be provided.The erasable control circuit modular structure of the EEPROM schematic diagram that Figure 1 shows that prior art, it is applied in RFID label chip.As shown in Figure 1, the erasable control circuit 50 of EEPROM mainly comprises charge pump circuit 51 and voltage stabilizing diode 52, and the output termination voltage stabilizing diode 52 of charge pump circuit 51 provides erasable required high-voltage signal with the form of voltage stabilizing.The erasable control circuit 50 of EEPROM couples with the radio-frequency (RF) front-end circuit 20 in RFID label chip, radio-frequency (RF) front-end circuit 20 couples with antenna 10, the high-voltage signal of erasable control circuit 50 outputs of EEPROM can bias on storage array 60, after some storage unit of storage array 60 are selected, this storage unit is carried out erasable operation by this high-voltage signal.
Specifically, in the erasable control circuit 50 of EEPROM, utilize the high-voltage signal of charge pump circuit 51 and voltage stabilizing diode 52 generation such as 15V.Wherein, utilize voltage stabilizing diode 52 near reverse-conducting voltage, to produce the characteristic of large electric current, when high-voltage signal not yet reaches voltage stabilizing diode 52 reverse-conducting required voltage, the energy that charge pump circuit 51 produces can continue to raise voltage signal, when high-voltage signal reaches voltage stabilizing diode 52 reverse-conducting required voltage, voltage stabilizing diode 52 produces larger reverse leakage, the energy of charge pump circuit 51 outputs and the leakage current of voltage stabilizing diode 52 reach balance, thereby, high-voltage signal is stabilized near the reverse-conducting voltage of voltage stabilizing diode 52.
As mentioned above, for make all storage unit substantially once erasable operation successfully and not verify, it must have larger amount of redundancy for erasable high-voltage signal, to guarantee that the storage unit under poor process corner also can be operated successfully by erasable.Erasable method of operating and the erasable control circuit of current EEPROM mainly contain following shortcoming:
The first, adopt voltage stabilizing diode to carry out voltage stabilizing, make the output energy of charge pump can not be too low.This be due to, the breakdown reverse voltage of voltage stabilizing diode is not a point, but along with the rising of reversed bias voltage, reverse leakage increases gradually.If charge pump output energy is lower, voltage stabilizing diode can be clamped at output voltage compared with electronegative potential, causes some unit can not be successfully erasable; If charge pump output energy is enough high, the major part of its output energy is released by voltage stabilizing diode, and voltage stabilizing process can cause a large amount of wastes of energy.
The second, in the erasable method of operating of memory cell, erasable signal setting a large amount of redundancies, comprise the redundancy of voltage aspect and the redundancy of running time, be especially unfavorable for reducing power consumption.
Summary of the invention
One of the object of the invention is, reduces the power consumption of the erasable operation of EEPROM.
An also object of the present invention is, reduces the power consumption of ultra-high frequency RFID label chip.
For realizing above object or other objects, the invention provides following technical scheme.
According to an aspect of of the present present invention, the erasable control circuit of a kind of EEPROM is provided, for EEPROM is carried out to erasable operation, this erasable control circuit comprises:
Charge pump system, for providing the erasable operate high pressure signal that voltage can staged lifting; With
Proof scheme, it is for verifying described EEPROM erasable operation successfully whether under the effect of described erasable operate high pressure signal, and outputs control signals to described charge pump system;
Wherein, if proof scheme is judged as not erasable operation successfully, export the voltage steps ladder type lifting that described control signal makes the erasable operate high pressure signal of described charge pump system; If proof scheme is judged as erasable operation successfully, export the not lifting of voltage that described control signal makes the erasable operate high pressure signal of described charge pump system.
According to the erasable control circuit of one embodiment of the invention, wherein, described charge pump system comprises:
Charge pump circuit, its for its input voltage of lifting to export erasable operate high pressure signal;
Clock generation circuit, it is used to described charge pump circuit that comparatively faster the first clock signal and relatively slow second clock signal are provided;
Bleeder circuit, it is for exporting described output voltage pari passu the voltage division signal of low voltage; And
Voltage-dividing detection circuit, its comparative result according to received described voltage division signal and reference voltage is controlled output clock switching signal to described clock generation circuit;
Wherein, described proof scheme outputs control signals to described voltage-dividing detection circuit so that described reference voltage to be set, if proof scheme is judged as not erasable operation successfully, improve described reference voltage is set, if proof scheme is judged as erasable operation successfully, described reference voltage is set it is remained unchanged;
Wherein, if the voltage of described voltage division signal is more than or equal to described reference voltage, described voltage-dividing detection circuit output clock switching signal is so that described clock generation circuit output second clock signal; If the voltage of described voltage division signal is less than described reference voltage, described voltage-dividing detection circuit output clock switching signal is so that described clock generation circuit is exported the first clock signal; While exporting described the first clock signal, the voltage lifting of the erasable operate high pressure signal of described charge pump circuit output; While exporting described second clock signal, the voltage of the erasable operate high pressure signal of described charge pump circuit output remains unchanged substantially.
In the charge pump system of described embodiment before, preferably, described voltage-dividing detection circuit comprises voltage comparator, and it is for the size between more described voltage division signal and described reference voltage.
In the charge pump system of described embodiment before, preferably, by described voltage-dividing detection circuit, the control signal based on proof scheme output arranges described reference voltage.
According to another aspect of the present invention, the erasable method of operating of a kind of EEPROM is provided, it comprises:
Voltage ladder lifting step: staged lifting is for the voltage of erasable operate high pressure signal; With
Verification step: verify that whether erasable operation is successful, do not operate successfully if erasable, enter described voltage ladder lifting step with the voltage of erasable operate high pressure signal described in the lifting of continuation staged.
According to the erasable method of operating of one embodiment of the invention, wherein, in described verification step, if erasable, operate successfully, enter and repeat erasable operation steps: the erasable operate high pressure signal based on the erasable operation of this success repeats once erasable operation to corresponding EEPROM.
Particularly, in described voltage ladder lifting step, the size of the voltage of described erasable operate high pressure signal arranges by the erasable operation control circuit of EEPROM.
According to the erasable method of operating of further embodiment of this invention, wherein, described reference voltage comprises N ascending the 1st reference voltage to the N reference voltage setting gradually, and described voltage ladder lifting step comprises the following steps:
By voltage-dividing detection circuit, operationally select to arrange M reference voltage;
The first comparison step: by the more described voltage division signal of voltage-dividing detection circuit and described M reference voltage,
Wherein, if the voltage of described voltage division signal is less than M reference voltage, described voltage-dividing detection circuit output clock switching signal is so that described clock generation circuit is exported the first clock signal, the output voltage of charge pump circuit is lifted, until make the voltage of described voltage division signal be more than or equal to described M reference voltage
If the voltage of described voltage division signal is more than or equal to M reference voltage, described voltage-dividing detection circuit output clock switching signal is so that described clock generation circuit is exported second clock signal, and the output voltage home position of charge pump circuit is constant;
In described verification step, if erasable, do not operate successfully, proof scheme sends and controls signal to described voltage-dividing detection circuit so that M adds 1 certainly, realizes improving that reference voltage being set, and returns and enters described the first comparison step;
Wherein, N is more than or equal to 2 integer, and M is more than or equal to 1 and be less than the integer of N.
In the erasable method of operating of described arbitrary embodiment before, preferably, the voltage of described voltage division signal is less than or equal to the supply voltage of described radio frequency identification label chip.
In the erasable method of operating of described arbitrary embodiment before, preferably described EEPROM is the storer that radio frequency identification label chip is used.
According to of the present invention, provide a kind of radio frequency identification label chip also on the one hand, be characterised in that, comprising:
EEPROM; And
The above and the erasable control circuit of any EEPROM.
Preferably, described radio frequency identification label chip is ultrahigh frequency (UHF) radio frequency identification label chip.
Technique effect of the present invention is, reduced the power consumption of the charge pump circuit in erasable function circuit, also reduced the power consumption of erasable operating process, uses RFID label chip low in energy consumption of this erasable method of operating and erasable control circuit.And the characteristic between each storage unit in the EEPROM after erasable operation is even, be also difficult for damaging device because of the overtension of erasable operate high pressure signal.
Accompanying drawing explanation
From following detailed description by reference to the accompanying drawings, will make above and other object of the present invention and advantage more completely clear, wherein, same or analogous key element adopts identical label to represent.
Fig. 1 is the erasable control circuit modular structure of the EEPROM of prior art schematic diagram.
Fig. 2 is the erasable method of operating schematic flow sheet according to the EEPROM of one embodiment of the invention.
Fig. 3 is the modular structure schematic diagram according to the erasable control circuit of the EEPROM of one embodiment of the invention.
Fig. 4 is that charge pump system shown in Fig. 3 is at the control method schematic flow sheet of voltage lifting process.
Embodiment
What introduce below is some in a plurality of possibility embodiment of the present invention, aims to provide basic understanding of the present invention, is not intended to confirm key of the present invention or conclusive key element or limits claimed scope.Easily understand, according to technical scheme of the present invention, do not changing under connotation of the present invention other implementations that one of ordinary skill in the art can propose mutually to replace.Therefore, following embodiment and accompanying drawing are only the exemplary illustrations to technical scheme of the present invention, and should not be considered as of the present invention all or be considered as the restriction of technical solution of the present invention or restriction.
In description below, clear and simple and clear for what describe, all a plurality of parts shown in figure are not described.A plurality of parts of the disclosure that can realize completely shown in the drawings of those of ordinary skills.To those skilled in the art, it is all familiar and obvious being permitted multipart operation.
Figure 2 shows that the erasable method of operating schematic flow sheet according to the EEPROM of one embodiment of the invention.In this embodiment, identical with EEPROM in the prior art shown in Fig. 1 by the EEPROM of erasable operation, for example, 15V is the high-voltage signal with larger amount of redundancy, substantially can all storage unit successes in EEPROM are erasable in the situation that of 15V.Similarly, for erasable high-voltage signal, the charge pump circuit output by the erasable control circuit of EEPROM provides.Specifically in conjunction with 2 pairs of erasable operating process, describe.
First, step S501, arranges V
r=V
r (0), for example, V
r (0)=1.0V, by arranging V
rcan define the voltage swing of the high-voltage signal that charge pump circuit exports.
Further, step S502, charge pump circuit output 10V carries out erasable operation.The voltage signal of charge pump circuit output is indirectly to pass through V
rcontrol, in this embodiment, V
r (0)during=1.0V, the high-voltage signal of charge pump circuit output 10V.But, V
rconcrete size with and the voltage swing of the high-voltage signal exported of the charge pump circuit of institute's correspondence control be not restrictive.
Further, step S503, verifies that whether erasable operation is successful.If be judged as successfully, preferably, enter step S504, based on this high-voltage signal, repeat once erasable, effective to guarantee this erasable operation, further enter step S562, erasable operation success; If be judged as unsuccessfully, represent that the high-voltage signal of 10V is not high enough, need further to improve the output voltage of charge pump circuit, enter step S511.
Further, be similar to above step S501 to step S504, repeated execution of steps S511 is to step S514, and charge pump circuit output voltage is risen to 11V.Analogically, can further perform step S521-S524, step S531-S534, step S541-S544, step S51-S554, in step S553, if still can not erasablely operate successfully with the high-voltage signal of 15V, judge erasable operation failure this time, i.e. step S561.
In above erasable method of operating process, the voltage that is used for the high-voltage signal of erasable operation can start to carry out erasable operation from relative smaller value, if the in the situation that of smaller value, erasable operation successfully, power consumption is relatively low, and, if verify erasable unsuccessful, can be by VR be set, further raise the voltage of high-voltage signal, until the erasable operation that hits pay dirk, or for example, still do not have success not erasable until reach the ceiling voltage (15V) of setting, abandon this time erasable operation, this time erasable operation failure.Therefore, storage unit for EEPROM, under the inconsistent situation of its erasable voltage, all can under its corresponding voltage ladder size, carry out erasable operation, the voltage of erasable operation is relatively little, overall power reduces, and is also conducive to shorten the erasable running time (in the erasable running time of prior art, being also provided with redundancy to realize substantially disposable erasable operation successfully).
Figure 3 shows that the modular structure schematic diagram according to the erasable control circuit of the EEPROM of one embodiment of the invention.In this embodiment, it is for realizing above erasable method of operating process as shown in Figure 1, and, and take that it is applied to RFID label chip and schematically illustrates as example.But, it will be appreciated that, the erasable control circuit of EEPROM is not limited to be applied to RFID label chip, at EEPROM, answers in land used other system, need to realize with low power in the situation of erasable operation, all can apply the erasable control circuit of EEPROM of the present invention.
As shown in Figure 3, the erasable control circuit of EEPROM comprises charge pump system 30 and proof scheme 40, and it carries out erasable operation for the storage array 60 for EEPROM.The storage array 60 of EEPROM comprises the storage unit that a plurality of forms by row and column are arranged, its specific constructive form is not restrictive, and selected certain or a plurality of storage unit can be setovered to carry out erasable operation by the high-voltage signal of charge pump circuit 31 outputs of charge pump system 30.Proof scheme 40 can verify whether the data after erasable are required data, verify whether erasable operation is successfully carried out.
The structure of the charge pump system 30 of the erasable control circuit of EEPROM and principle of work thereof please number for CN201210060644.0, name are called in " charge pump system and control method thereof and comprise its radio frequency identification label chip " revealedly, be contained in by the mode quoting in full at this in this application in Chinese patent.Particularly, charge pump system 30 comprises charge pump circuit 32, clock generation circuit 31, bleeder circuit 33, voltage-dividing detection circuit 34.Charge pump circuit 32 can lifting input voltage (be also the supply voltage V of RFID label chip
dD), thereby the relatively high output voltage V out of output, for example, if the required erasable operating voltage of the EEPROM of RFID label chip is 10V, it is higher than supply voltage V
dD, so charge pump circuit 32 can provide target output voltage be the high-voltage signal of 10V to EEPROM, thereby successfully realize erasable operation; At charge pump circuit 32 by V
dDbe raised in the process of 10V, be voltage lifting process, will describe the voltage lifting process of charge pump system 30 in detail thereafter.
The particular circuit configurations type of charge pump circuit 32 is not restrictive, and it can, for the various conventional charge pumps that use, for example, can be the NCP charge pump based on Dickson structure, SP charge pump and the charge pump based on voltage multiplication.The target output voltage of charge pump circuit 32 etc. also can change according to concrete loading condition, for example, and the 10V of embodiment, 11V, 12V, 13V, 14V and 15V as shown in Figure 1.
The voltage division signal V of bleeder circuit 33 outputs
finput to voltage-dividing detection circuit 34, voltage-dividing detection circuit 34 can be less than or equal to the supply voltage V of RFID label chip
dDscope in reference voltage V is provided
r, reference voltage V
rconcrete size can regulate setting, for example, the V of embodiment as shown in Figure 1
r (1), V
r (2), V
r (3), V
r (4)and V
r (5), it specifically can control realization according to the reference voltage conditioning signal that inputs to voltage-dividing detection circuit 34.Voltage-dividing detection circuit 34 comprises and is provided with voltage comparator, and this voltage comparator can be by voltage division signal V
fwith reference voltage V
rrelatively; If V
f>=V
r, fast/slow clock switching signal of voltage-dividing detection circuit 34 outputs, controls the slow clock f of clock generation circuit 31 output
2; If V
f< V
r, fast/slow clock switching signal of voltage-dividing detection circuit 34 outputs, controls the fast clock f of clock generation circuit 31 output
1.Therefore the clock switching signal that, the clock signal of clock generation circuit 31 outputs is exported by voltage-dividing detection circuit 34 is controlled.
And for voltage-dividing detection circuit 34, it is controlled by the output signal of proof scheme 40.If proof scheme 40 checking erasable operation successfully, reference voltage V
rdo not change, V
fcontinue to be more than or equal to V
r, control clock generation circuit 31 and continue the fast clock f of output
2, the output voltage of charge pump circuit 31 remains unchanged; If the erasable operation of proof scheme 40 checking is unsuccessful, proof scheme 40 output signals make the reference voltage V in voltage-dividing detection circuit 34
rbe conditioned setting, for example, due to V
r (1)become V
r (2)thereby, control clock generation circuit 31 and continue the slow clock f1 of output, the output voltage staged lifting of charge pump circuit 31.
Figure 4 shows that charge pump system shown in Fig. 3 is at the control method schematic flow sheet of voltage lifting process.In this embodiment, the high-voltage signal that the initial output voltage of charge pump circuit 32 of take is 10V, can lifting maximum output voltage as 15V, dividing potential drop ratio describe as example as 0.1, wherein reference voltage V can be set
r=1V, 1.1V, 1.2V, 1.3V, 1.4V or 1.5V, it can in turn be raised its reference voltage is set, and it is raised to arrange and controlled by proof scheme 40.
As shown in Figure 4, first start, i=0, n=1, also arrange initial baseline voltage, initial baseline voltage V
r (1)=1V, now, the output voltage of charge pump circuit 32 will be raised to Vout (1)=10V.In following process, along with increasing progressively of n, represent reference voltage V
r (n)by lifting setting, V
r (1 ..., 5), equal respectively 1V, 1.1V, 1.2V, 1.3V, 1.4V, 1.5V; Along with increasing progressively of i, output voltage V out (i) lifting, Vout (0,1 ..., 5) and equal respectively 10V, 11V, 12V, 13V, 14V, 15V, voltage division signal V
f (i)also follow lifting, V
f (0,1 ..., 5)equal respectively 1V, 1.1V, 1.2V, 1.3V, 1.4V, 1.5V.
Further, step S110, voltage-dividing detection circuit 34 arranges reference voltage V
r (n).
Further, step S120, charge pump circuit 32 output voltage V out (i).
Further, step S130, bleeder circuit 33 is from charge pump circuit 32 output terminal dividing potential drop output voltage division signal V
f (i)=0.1Vout (i).The concrete setting of dividing potential drop ratio is not limited by the embodiment of the present invention.
Further, step S140, voltage-dividing detection circuit 34 is V relatively
f (i)with reference voltage V
r (n).This step can complete by the voltage comparator in voltage-dividing detection circuit 34.
Further, step S150, judgement V
f (i)whether be more than or equal to V
r (n).
If be judged as "No", represent that output voltage V out (i) can continue lifting, enter step S161, the fast clock signal of clock generation circuit 31 output; And further, step S171, arranges i=i+1, output voltage lifting; Be back to step S120, Vout (i)=Vout (i+1), represents output voltage lifting.Until be judged as "Yes".In the situation that charge pump circuit works in fast clock signal, its power consumption can be greater than outside input energy, and the part of its deficiency can be in RIFD label chip maintains the energy that electric capacity stores and supplement.
If be judged as "Yes", explain output voltage V out (i) and temporarily do not continue lifting, enter step S162, clock generation circuit 31 output slow clock signals.Now, the power consumption of charge pump circuit 32 is extremely low, and output voltage is also basicly stable.In the situation that charge pump circuit works in slow clock signal, its power consumption is generally less than outside input energy.
Further, step S172, the output voltage V out of charge pump circuit 32 (i) remains constant substantially, with this output voltage signal, selected EEPROM unit is carried out to erasable operation.
Further, step S180, proof scheme 40 judges that whether erasable operation is successful.If be judged as, operate successfully, finish lifting process; If be judged as, do not operate successfully, enter step S190, n=n+1 is set.
In step S190, can be specifically by proof scheme 40, to send control signal to make n from adding one, thereby make its reference voltage V
r (n)increase, for further improving the output voltage of charge pump circuit 31, prepare.
It will be appreciated that, step S501 to S503 embodiment illustrated in fig. 1, S511 to S513, S521 to S523, S531 to S533, S541 to S543, S551 to S553 all can realize by procedure shown in above Fig. 4.And above step S110 to S190 can constantly loop, along with reference voltage is raised to 1.5V from 1.0V, the output voltage of charge pump circuit 32 also can be raised to 15 volts of target output voltages from 10V successively.
In the voltage lifting process of above step S110 to S190, explanation in conjunction with Fig. 3 and Fig. 4 is known, average working current in lifting process and average power-dissipation-reduced, and, the outside energy providing has been provided as much as possible, and outside input average current required in output voltage lifting process can be reduced, (for example, can drop to 20uA, even drop to 10uA following).Therefore, the power consumption of charge pump system 30 can reduce greatly.
Further, as shown in Figure 3, charge pump system 50 couples by RF front-end module 30 and the antenna 10 of RFID label.
Because the erasable operation of EEPROM has increased verification step, thereby the accuracy of the high-voltage signal for erasable operation (being the output voltage of charge pump circuit 31) is required to reduce, high-voltage signal has some fluctuations also can not produce much problems; Meanwhile, avoid using voltage stabilizing diode.Adopting slow clock to maintain the High voltage output of charge pump, avoided the waste of energy.Because high-voltage signal is to start progressively lifting from relatively low 10V, the erasable operation in EEPROM unit is completed, so there will not be high pressure too high, damage the situation of device, do not have too much redundancy voltage yet and be biased on EEPROM.
Adopt above erasable operation scheme to mainly contain following advantage:
(1) low-power consumption
From memory cell level, change erasable operator scheme, different storage unit can be carried out erasable operation under erasable voltage in the difference of its correspondence, not only reduce the power consumption of charge pump, and reduced the overall power of erasable operation overall process, shortened the erasable running time of most unit.
(2) memory cell characteristics of erasable EEPROM after operating is successfully even
Owing to adopting equal amount of redundancy to verify, so after being verified, the element characteristics of EEPROM is uniformity relatively, more favourable to the erasable operation of next time, more favourable to the long-term use of EEPROM.
The another aspect of the present embodiment discloses a kind of RFID label chip, it uses charge pump system 50 as shown in Figure 3, its memory module can adopt EEPROM (comprising storage array 60), to RFID label chip, writing fashionable, the erasable method of operating of its EEPROM is applied the erasable method of operating of embodiment as shown in Figure 1, therefore, the power consumption of RFID label chip can reduce.Preferably, RFID label chip is ultra-high frequency RFID label chip, thereby a low-power consumption difficult problem for ultra-high frequency RFID label chip is overcome.
In this article, in " connection " and " coupling " of described use term, when not using word " directly " to limit term " connection " and " coupling ", between its two parts that also can represent to be connected or couple, be also provided with miscellaneous part.
The erasable method of operating of EEPROM of the present invention has mainly been described above example, the erasable control circuit of EEPROM and the RFID label chip of applying this erasable method of operating and circuit.Although only some of them embodiments of the present invention are described, those of ordinary skills should understand, and the present invention can be within not departing from its purport and scope implements with many other forms.Therefore, the example of showing and embodiment are regarded as illustrative and not restrictive, and in the situation that not departing from spirit of the present invention as defined in appended each claim and scope, the present invention may be contained various modifications and replacement.
Claims (12)
1. an erasable control circuit of EEPROM, for EEPROM is carried out to erasable operation, is characterized in that, it comprises:
Charge pump system, for providing the erasable operate high pressure signal that voltage can staged lifting; With
Proof scheme, it is for verifying described EEPROM erasable operation successfully whether under the effect of described erasable operate high pressure signal, and outputs control signals to described charge pump system;
Wherein, if proof scheme is judged as not erasable operation successfully, export the voltage steps ladder type lifting that described control signal makes the erasable operate high pressure signal of described charge pump system; If proof scheme is judged as erasable operation successfully, export the not lifting of voltage that described control signal makes the erasable operate high pressure signal of described charge pump system.
2. erasable control circuit as claimed in claim 1, is characterized in that, described charge pump system comprises:
Charge pump circuit, its for its input voltage of lifting to export erasable operate high pressure signal;
Clock generation circuit, it is used to described charge pump circuit that comparatively faster the first clock signal and relatively slow second clock signal are provided;
Bleeder circuit, it is for exporting described output voltage pari passu the voltage division signal of low voltage; And
Voltage-dividing detection circuit, its comparative result according to received described voltage division signal and reference voltage is controlled output clock switching signal to described clock generation circuit;
Wherein, described proof scheme outputs control signals to described voltage-dividing detection circuit so that described reference voltage to be set, if proof scheme is judged as not erasable operation successfully, improve described reference voltage is set, if proof scheme is judged as erasable operation successfully, described reference voltage is set it is remained unchanged;
Wherein, if the voltage of described voltage division signal is more than or equal to described reference voltage, described voltage-dividing detection circuit output clock switching signal is so that described clock generation circuit output second clock signal; If the voltage of described voltage division signal is less than described reference voltage, described voltage-dividing detection circuit output clock switching signal is so that described clock generation circuit is exported the first clock signal; While exporting described the first clock signal, the voltage lifting of the erasable operate high pressure signal of described charge pump circuit output; While exporting described second clock signal, the voltage of the erasable operate high pressure signal of described charge pump circuit output remains unchanged substantially.
3. charge pump system as claimed in claim 2, is characterized in that, described voltage-dividing detection circuit comprises voltage comparator, and it is for the size between more described voltage division signal and described reference voltage.
4. charge pump system as claimed in claim 2, is characterized in that, by described voltage-dividing detection circuit, the control signal based on proof scheme output arranges described reference voltage.
5. an erasable method of operating of EEPROM, is characterized in that, comprising:
Voltage ladder lifting step: staged lifting is for the voltage of erasable operate high pressure signal; With
Verification step: verify that whether erasable operation is successful, do not operate successfully if erasable, enter described voltage ladder lifting step with the voltage of erasable operate high pressure signal described in the lifting of continuation staged.
6. erasable method of operating as claimed in claim 5, it is characterized in that, in described verification step, if erasable, operate successfully, enter and repeat erasable operation steps: the erasable operate high pressure signal based on the erasable operation of this success repeats once erasable operation to corresponding EEPROM.
7. erasable method of operating as claimed in claim 5, is characterized in that, in described voltage ladder lifting step, the size of the voltage of described erasable operate high pressure signal arranges by the erasable operation control circuit of EEPROM.
8. erasable method of operating as claimed in claim 5, is characterized in that, described reference voltage comprises N ascending the 1st reference voltage to the N reference voltage setting gradually, and voltage ladder lifting step comprises the following steps:
By voltage-dividing detection circuit, operationally select to arrange M reference voltage;
The first comparison step: by the more described voltage division signal of voltage-dividing detection circuit and described M reference voltage,
Wherein, if the voltage of described voltage division signal is less than M reference voltage, described voltage-dividing detection circuit output clock switching signal is so that described clock generation circuit is exported the first clock signal, the output voltage of charge pump circuit is lifted, until make the voltage of described voltage division signal be more than or equal to described M reference voltage
If the voltage of described voltage division signal is more than or equal to M reference voltage, described voltage-dividing detection circuit output clock switching signal is so that described clock generation circuit is exported second clock signal, and the output voltage home position of charge pump circuit is constant;
In described verification step, if erasable, do not operate successfully, proof scheme sends and controls signal to described voltage-dividing detection circuit so that M adds 1 certainly, realizes improving that reference voltage being set, and returns and enters described the first comparison step;
Wherein, N is more than or equal to 2 integer, and M is more than or equal to 1 and be less than the integer of N.
9. erasable method of operating as claimed in claim 8, is characterized in that, the voltage of described voltage division signal is less than or equal to the supply voltage of described radio frequency identification label chip.
10. erasable method of operating as claimed in claim 8, is characterized in that, described EEPROM is the storer that radio frequency identification label chip is used.
11. 1 kinds of radio frequency identification label chips, are characterised in that, comprising:
EEPROM: and
The erasable control circuit of EEPROM as described in any one in claim 1 to 4.
12. control methods as claimed in claim 10, is characterized in that, described radio frequency identification label chip is super high frequency radio frequency identification label chip.
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| CN201210389986.7A CN103700404A (en) | 2012-09-27 | 2012-09-27 | Erasing-writing operation method for EEPROM, erasing-writing control circuit and RFID tag chip |
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| CN201210389986.7A CN103700404A (en) | 2012-09-27 | 2012-09-27 | Erasing-writing operation method for EEPROM, erasing-writing control circuit and RFID tag chip |
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