CN206060529U - A kind of charge pump - Google Patents
A kind of charge pump Download PDFInfo
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- CN206060529U CN206060529U CN201620562240.5U CN201620562240U CN206060529U CN 206060529 U CN206060529 U CN 206060529U CN 201620562240 U CN201620562240 U CN 201620562240U CN 206060529 U CN206060529 U CN 206060529U
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Abstract
This utility model embodiment discloses a kind of charge pump, and the charge pump includes：Charge pump unit, under the control of clock signal and enable signal works or stops for each cycle, with output voltage；Voltage detection unit, exports the enable signal in next cycle to charge pump control unit for the output end voltage according to the charge pump unit and the fiducial value of target voltage values；At least two charge pump control units, correspond with least two charge pump circuits, it is high level for the enable signal in next cycle, when the input clock signal in current period and next cycle is same level, produce high level and enable signal, otherwise produce low level signal is enabled to the Enable Pin of corresponding charge pump circuit, and then the work of control charge pump circuit and stopping, control is realized while starting the quantity of the charge pump circuit started working, so as to reach the purpose for reducing output voltage fluctuation and input power noise.
Description
Technical field
This utility model embodiment is related to circuit engineering, more particularly to a kind of charge pump.
Background technology
Nonvolatile flash memory medium (nor Flash/nand Flash) is a kind of very common storage chip, has concurrently and deposits at random
The advantage of reservoir (Random Access Memory, RAM) and read only memory (Read-Only Memory, ROM), data are fallen
Electricity will not be lost, be it is a kind of can carry out the erasable memorizer of electricity in system, while its high integration and low cost make it
The market mainstream.
Flash chip is made up of internal thousands of memory element, and each storage element stores a data, is led to
Cross the storage for applying corresponding voltage in the wordline of memory element to complete data to operate, the voltage is typically by charge pump
Circuit is produced, and the voltage of charge pump circuit output would generally carry certain voltage pulsation, and the voltage pulsation can affect data
Storage, and, with the diminution of Flash chip technology feature size, the capacitive load of output voltage also with becoming big, in order to
The readout time for meeting Flash chip requires, needs many charge pump circuit parallel operations, and then cause charge pump circuit to export
Voltage pulsation it is bigger and be difficult to control to, while input power noise can also increase, affect the storage performance of Flash chip.
A kind of charge pump construction schematic diagram of the prior art is may refer to shown in Fig. 1, and the charge pump includes n parallel connection
Charge pump circuit and the charge pump circuit one-to-one signal processing circuit in parallel with the n, output voltage VO UT are passed through
Resistance R3 and R4 carry out partial pressure, are compared with reference voltage VREF, when output voltage is more than reference voltage, export high level
Enable signal PMPEN, otherwise export low level enable signal PMPEN.Enabling signal PMPEN is used to control next cycle
Whether charge pump circuit works, thus regulating and controlling output voltage.For each charge pump circuit, whether current period works, takes
Certainly in the enable signal PMPEN of current period, when the enable signal PMPEN of current period is high level, in input clock signal
CLKIN<n>Driving under charge pump circuit start working；In order to avoid all charge pump circuits are worked or are not worked simultaneously, respectively
Individual input clock signal CLKIN<n>There is certain phase contrast, be illustrated in figure 2 four phase place input clock signal schematic diagrams, often
Individual input clock signal CLKIN<n>About 1/8 clock cycle is differed in front and back.
If with many charge pump circuits of above-mentioned four phase clock control, although input clock signal CLKIN<n>Between
Delay can to a certain degree reduce the fluctuation of output voltage, but the purpose for reducing completely can not be reached.Such as, current week
After phase more several charge pump circuits quit work, signal PMPEN is enabled for low level, the input of more several charge pump circuits
Clock signal clk IN<n>It is low level, drive clock signal CLKD<n>Low level is parked in, then in next cycle charge pump electricity
When road works, during t0 to t1, the input clock signal CLKIN of more several charge pump circuits<n>For high level, if this
The enable signal PMPEN of the more several charge pump circuits of Shi Suoshu is changed into high level, then more several out-of-work charge pumps
The drive clock signal CLKD of circuit<n>It is changed into high level simultaneously, more several out-of-work charge pump circuits will simultaneously
Start working, so as to produce larger voltage pulsation, as shown in figure 3, for one with multiple charge pump circuits while the generation that works
Voltage pulsation difference schematic diagram, wherein, the first curve 310 represents the voltage pulsation exported during a charge pump circuit functions,
Second curve 320 represents multiple charge pump circuits while the voltage pulsation exported when working.Similar, if current period is most
After charge pump circuit quits work, it is low, the input clock signal of more several charge pump circuits to enable signal PMPEN
CLKIN<n>It is high level, drive clock signal CLKD<n>High level is parked in, then in next cycle charge pump circuit functions
When, during t2 to t3, the input clock signal CLKIN of more several charge pump circuits<n>For low level, if now described
The enable signal PMPEN of more several charge pump circuits is changed into high level, then more several out-of-work charge pump circuits
Drive clock signal CLKD<n>It is changed into low level simultaneously, more several out-of-work charge pump circuits will start simultaneously at work
Make, equally produce larger voltage pulsation.Generally each phase place input clock signal CLKIN<n>Between delay by CMOS doors or
Resistance is constituted, and may be changed with supply voltage, technique, temperature etc. and be changed so that the when anaplasia between t0 to t1 or t2 to t3
Greatly, so as to the probability for producing larger voltage pulsation increases.
In sum, need to design a kind of fluctuation range of circuit to reduce charge pump circuit output voltage, improve output
The accuracy of voltage.
Utility model content
This utility model provides a kind of charge pump, to reduce the fluctuation range and input power noise of output voltage.
This utility model embodiment provides a kind of charge pump, and the circuit includes：
Charge pump unit, the charge pump unit include at least two charge pump circuits, and the charge pump circuit is mutually simultaneously
Connection connection, under the control of clock signal and enable signal works or stops for each cycle, with output voltage；
Voltage detection unit, the input of the voltage detection unit are connected with the outfan of the charge pump unit, are used
The enable signal that next cycle is exported with the fiducial value of target voltage values in the output end voltage according to the charge pump unit is arrived
Charge pump control unit；
At least two charge pump control units, are corresponded with least two charge pump circuits, and each charge pump control is single
The first input end of unit is connected with the outfan of the voltage detection unit respectively, for obtaining the enable signal in next cycle,
Second input is used for the drive clock signal for receiving current period, and the 3rd input is connected with input clock source respectively, is used for
The input clock signal in next cycle is obtained, the charge pump control unit is high electricity for the enable signal in next cycle
It is flat, when the input clock signal in current period and next cycle is same level, produces high level and enable signal, otherwise produce
Low level enables signal, and the outfan of charge pump control unit is connected with the Enable Pin of charge pump circuit, makes for output
Energy signal gives the charge pump circuit, wherein, there is Phase delay between the input clock signal of each charge pump circuit.
Exemplarily, the voltage detection unit includes division module and enable signal output module, wherein, the partial pressure
Module carries out partial pressure for the output end voltage to the charge pump unit；The enable signal output module is for according to described
The output end voltage of charge pump unit enables signal with the fiducial value output of target voltage values.
Preferably, the division module includes first resistor and second resistance, and the enable signal output module includes
One comparator, wherein：
The first end of the first resistor is connected with the outfan of the charge pump unit, the second end and the second resistance
First end be connected, the second end of second resistance ground connection；The inverting input of the first comparator is electric with described first
Second end of resistance is connected, and normal phase input end is connected with reference voltage, and outfan output enables signal.
Further, the charge pump also includes：
At least two signal processing units, with least two charge pump circuit and at least two charge pump control units
Correspond, the first input end of each signal processing unit is connected with the outfan of charge pump control unit, under acquisition
The enable signal in one cycle, the second input are connected with input clock source, for obtaining the input clock signal in next cycle, institute
Signal processing unit is stated for the driving for driving next cycle charge pump circuit functions being produced under the control for enabling signal
Clock signal and opposite phased driving clock signal, to drive charge pump circuit functions.
Preferably, the signal processing unit includes：4th phase inverter, the second nor gate, the 3rd nor gate, the 4th or non-
Door and the 3rd and door,
Wherein, the input of the 4th phase inverter and the 3rd with the second input of door respectively with charge pump control unit
Outfan be connected, the outfan of the 4th phase inverter is connected with the second input of the second nor gate；The first of second nor gate
Input and the 3rd is connected with input clock signal respectively with the second input of door, the outfan of the second nor gate and the 3rd or
The first input end of not gate is connected；Second input of the 3rd nor gate is connected with the outfan of four nor gate, outfan with
The first input end of four nor gate is connected；Second input of four nor gate is connected with the 3rd with the outfan of door.
Preferably, the charge pump control unit includes：First phase inverter, the second phase inverter, first with door, second with
Door, the first nor gate, the first NAND gate, the second NAND gate and the 3rd phase inverter,
Wherein, the input of first phase inverter and first with the second input of door respectively with input clock signal phase
Even, the outfan of the first phase inverter is connected with second with the first input end of door；The input and first of second phase inverter
It is connected with the drive clock signal of current period with the first input end of door respectively, the outfan of the second phase inverter and second and door
The second input be connected；First is connected with the first input end of the first nor gate with the outfan of door；Second with the output of door
End is connected with the second input of the first nor gate；Second input phase of the outfan of the first nor gate and the second NAND gate
Even；The first input end of the second NAND gate is connected with the outfan of the first NAND gate, and outfan is defeated with the second of the first NAND gate
Enter end to be connected；The first input end of the first NAND gate is connected with the outfan of voltage detection unit, outfan and the 3rd phase inverter
Input be connected.
Further, the charge pump also includes input clock source, and the input clock source is single with charge pump control respectively
Unit, signal processing unit are connected, for producing the input clock signal of setpoint frequency.
A kind of charge pump that this utility model embodiment is provided, by drive clock signal and next cycle of current period
Input clock signal and enable signal, determine jointly the enable signal in next cycle, it is to avoid multiple charge pump circuits occur
The situation of work, realizes when multiple charge pump circuit parallel operations simultaneously, and control starts the charge pump started working simultaneously
The quantity of circuit, so as to reach the purpose for reducing output voltage fluctuation and input power noise.
Description of the drawings
Fig. 1 is a kind of charge pump construction schematic diagram of the prior art；
Fig. 2 is four phase place input clock signal schematic diagrams；
Fig. 3 is a charge pump circuit functions and multiple charge pump circuits while when working, the contrast of output voltage fluctuation
Schematic diagram；
Fig. 4 is a kind of structural representation of charge pump that this utility model embodiment one is provided；
Fig. 5 is the structural representation of the voltage detection unit that this utility model embodiment two is provided
Fig. 6 is a kind of circuit diagram of voltage detection unit that this utility model embodiment two is provided；
Fig. 7 is a kind of circuit diagram of charge pump control unit that this utility model embodiment three is provided；
Fig. 8 is each signal waveform schematic diagram that this utility model embodiment three is provided；
Fig. 9 is that the charge pump of the present utility model that this utility model embodiment three is provided and existing charge pump are equally being born
Input power noise and current simulations comparison of wave shape schematic diagram under the conditions of load；
Figure 10 is a kind of structural representation of charge pump that this utility model example IV is provided；
Figure 11 is a kind of circuit diagram of signal processing unit that this utility model example IV is provided.
Specific embodiment
The utility model is described in further detail with reference to the accompanying drawings and examples.It is understood that herein
Described specific embodiment is used only for explanation this utility model, rather than to restriction of the present utility model.Further need exist for
It is bright, for the ease of description, in accompanying drawing, illustrate only the part related to this utility model rather than entire infrastructure.
Embodiment one
Fig. 4 is a kind of charge pump construction schematic diagram that this utility model embodiment one is provided, and the present embodiment is applied to multiple
The situation of charge pump circuit parallel operation.Referring specifically to as shown in figure 4, a kind of charge pump that the present embodiment is provided is specifically included：
Charge pump unit 410, voltage detection unit 420 and at least two charge pump control units 430.
Charge pump unit 410, including at least two charge pump circuits 411, charge pump circuit 411 is connected in parallel with each other, and uses
In each cycle in clock signal clk IN<n>Work or stop under control with enable signal PMPEN-NEW, with output voltage；
The input of voltage detection unit 420 is connected with the outfan of charge pump unit 410, for according to charge pump unit
410 output end voltage VOUT exports the enable signal PMPEN in next cycle to charge pump control with the fiducial value of target voltage values
Unit processed 430；
At least two charge pump control units 430, are corresponded with least two charge pump circuits 411, each charge pump
The first input end of control unit 430 is connected with the outfan of voltage detection unit 420 respectively, for obtaining making for next cycle
Energy signal PMPEN, i.e. the enable signal for controlling next cycle charge pump circuit of current period output, the second input are used
In the drive clock signal CLKD for receiving current period<n>, the 3rd input is connected with input clock source respectively, under acquisition
The input clock signal CLKIN in one cycle<n>, charge pump control unit 430 for the enable signal PMPEN in next cycle is
High level, the drive clock signal CLKD of current period<n>With the input clock signal CLKIN in next cycle<n>For identical electricity
At ordinary times, produce high level and enable signal PMPEN-NEW, otherwise produce low level and enable signal PMPEN-NEW, the enable signal
PMPEN-NEW is to actually enter the enable signal that charge pump circuit is controlled next cycle.Charge pump control unit 430 it is defeated
Go out end to be connected with the Enable Pin of charge pump circuit 411, signal PMPEN-NEW is enabled to charge pump circuit 411 for exporting, its
In, the input clock signal CLKIN of each charge pump circuit<n>Between have Phase delay.
Whether the first input end signal PMPEN of each charge pump control unit 430 is that high level depends on charge pump list
Whether the output end voltage VOUT of unit 410 reaches target voltage values, if it is, first input end signal PMPEN is high level,
Otherwise first input end signal PMPEN is low level；Second input end signal CLKD<n>It is that high level or low level depend on to be
In the working condition of this 430 corresponding charge pump circuit of charge pump control unit, 411 current period, if corresponding charge pump is electric
The working condition of 411 current period of road is off work, then the second input end signal CLKD<n>For low level, it is otherwise high electricity
It is flat；And the input clock signal CLKIN of the 3rd input<n>For the pulse signal of setting cycle.When first input end signal, i.e.,
When the enable signal PMPEN in next cycle is low level, the corresponding output of charge pump control unit 430 low level enables signal
PMPEN-NEW gives corresponding charge pump circuit 411, then this charge pump circuit 411 of next cycle does not work；When first input end is believed
Number, i.e., when the enable signal PMPEN in next cycle is high level, and the second input (drive clock signal of current period
CLKD<n>) and the 3rd input (the input clock signal CLKIN in next cycle<n>) for same level when, corresponding charge pump
Control unit 430 exports high level and enables signal PMPEN-NEW to corresponding charge pump circuit 411, then this electric charge of next cycle
Pump circuit 411 is started working.
Thus, it is supposed that current period several charge pump circuits 411 more quit work, corresponding enable signal PMPEN is low
Level, the input clock signal CLKIN of the several charge pump circuits more 411<n>Low level, then current period drive clock
Signal CLKD<n>Be parked in low level, then when next cycle charge pump circuit 411 works, during t0 to t1, the majority
The input clock signal CLKIN of individual charge pump circuit 411<n>For high level, if now described several charge pump circuits more 411
Enable signal PMPEN and be changed into high level, but due to the drive clock signal of more several 411 current periods of charge pump circuit
CLKD<n>Low level is parked in, the input clock signal CLKIN with next cycle<n>It is not same level, so charge pump control
Unit processed 430 produces low level and enables signal to more several charge pump circuits 411, more several quits work so described
Charge pump circuit 411 will no longer start simultaneously at work, due to the input clock signal CLKIN of each charge pump circuit 411<n>It
Between have certain Phase delay, so with each input clock signal CLKIN<n>It is changed into low level successively, corresponding each stopping
The charge pump circuit 411 of work will start start-up operation successively, so as to reduce voltage pulsation.
Same principle, it is assumed that current period majority charge pump circuit 411 quits work, corresponding enable signal PMPEN
For low, the input clock signal CLKIN of the several charge pump circuits more 411<n>High level, then drive clock signal CLKD
<n>Be parked in high level, then when next cycle charge pump circuit 411 works, during t2 to t3, more several charge pumps
The input clock signal CLKIN of circuit 411<n>For low level, if the enable signal of now described several charge pump circuits more 411
PMPEN is changed into high level, but due to the drive clock signal CLKD of more several 411 current periods of charge pump circuit<n>Stop
In high level, the input clock signal CLKIN with next cycle<n>It is not same level, so more several stopping works
The charge pump circuit 411 of work will no longer start simultaneously at work, so as to reduce voltage pulsation.
A kind of charge pump that the present embodiment is provided, by increasing charge pump between voltage detection unit and charge pump circuit
Control unit, and the first input end of the charge pump control unit is connected with the outfan of the voltage detection unit respectively,
For obtaining the enable signal in next cycle, the second input is used for the drive clock signal for receiving current period, the 3rd input
End is connected with input clock source respectively, and for obtaining the input clock signal in next cycle, the charge pump control unit is used for
It is high level in the enable signal in next cycle, the drive clock signal and the input clock signal in next cycle of current period are
During same level, produce high level and enable signal, otherwise produce low level and signal is enabled to the Enable Pin of charge pump circuit, and then
The work of control charge pump circuit and stopping, realizing when multiple charge pump circuit parallel operations, and control starts simultaneously and starts
The quantity of the charge pump circuit of work, so as to reach the purpose for reducing output voltage fluctuation and input power noise.
Embodiment two
Fig. 5 is the structural representation of the voltage detection unit that this utility model embodiment two is provided, in above-described embodiment
On the basis of, the present embodiment is optimized to voltage detection unit 420, shown in Figure 5, and voltage detection unit 420 includes：
Division module 421 and enable signal output module 422, wherein, division module 421 is for charge pump unit 410
Output end voltage carry out partial pressure；Signal output module 422 is enabled for the output end voltage and mesh according to charge pump unit 410
The fiducial value output of mark magnitude of voltage enables signal PMPEN.
Preferably, as a kind of implementation of voltage detection unit 420, shown in Figure 6, division module 421 includes：
First resistor R1 and second resistance R2, enabling signal output module 422 includes first comparator COMP1, wherein：
The first end of first resistor R1 is connected with the outfan VOUT of charge pump unit 410, the second end and second resistance R2
First end be connected, the second end of second resistance R2 ground connection；The inverting input of first comparator COMP1 and first resistor R1
Second end is connected, and normal phase input end is connected with reference voltage VREF, and outfan output enables signal PMPEN；
Wherein, the resistance of first resistor R1 and second resistance R2 is chosen according to the output target voltage of charge pump unit 410.
Voltage detection unit is optimized for division module and enables signal output module by the technical scheme of the present embodiment, its
In, division module carries out partial pressure for the output end voltage to charge pump unit, enables signal output module for according to electric charge
The output end voltage of pump unit exports the enable signal in next cycle with the fiducial value of target voltage values, so that charge pump control
Unit processed can enable the enable signal that signal produces the next cycle charge pump circuit functions of control according to described.
Embodiment three
Fig. 7 is a kind of circuit diagram of charge pump control unit that this utility model embodiment three is provided, in above-described embodiment
On the basis of, the present embodiment is optimized to charge pump control unit 430, and each charge pump circuit 411 is corresponding one
Charge pump control unit 430.Referring specifically to shown in Fig. 7,
Charge pump control unit 430 is specifically included：First phase inverter T1, the second phase inverter T2, first and door Y1, second with
Door Y2, the first nor gate HF1, the first NAND gate YF1, the second NAND gate YF2 and the 3rd phase inverter T3.
Wherein, the input of the first phase inverter T1 and first with second input of door Y1 respectively with input clock signal
CLKIN is connected, and the outfan of the first phase inverter T1 is connected with second with the first input end of door Y2；The second phase inverter T2's
Input and first is connected with the drive clock signal CLKD of current period respectively with the first input end of door Y1, the second phase inverter
The outfan of T2 is connected with second with second input of door Y2；First and the of the outfan of door Y1 and the first nor gate HF1
One input is connected；Second is connected with second input of the first nor gate HF1 with the outfan of door Y2；First nor gate HF1
Outfan be connected with the second input of the second NAND gate YF2；The first input end of the second NAND gate YF2 and the first NAND gate
The outfan of YF1 is connected, and outfan is connected with the second input of the first NAND gate YF1；First input of the first NAND gate YF1
End is connected with the outfan PMPEN of voltage detection unit 420, and outfan is connected with the input of the 3rd phase inverter T3.
In order to illustrate the operation principle of the charge pump control unit 430 of this utility model embodiment offer, each electricity is set
411 corresponding input clock signal CLKIN of lotus pump circuit differs 1/8 clock cycle successively, specifically may refer to shown in Fig. 2
Four phase place input clock signal schematic diagrams.Circuit diagram shown in Figure 7, if the first input end of the first NAND gate YF1
PMPEN is low level, then the outfan PMPEN-NEW of the 3rd phase inverter T3 is also low level；If the of the first NAND gate YF1
One input PMPEN is high level, then in the first input end and second of input clock signal CLKIN and first and door Y1
When same level occurs in the input CLKD of phase inverter T2, the outfan PMPEN-NEW of the 3rd phase inverter T3 is just high level.Often
The enable signal PMPEN-NEW in next cycle of individual charge pump circuit 411 is subject to the input clock signal in the next cycle of oneself
The impact of the drive clock signal CLKD states of CLKIN and current period and it is different.It is next that charge pump control unit 430 is exported
It is shown in Figure 8 that the charge pump in cycle enables signal PMPEN-NEW waveform diagrams, it is seen that next week of charge pump circuit 411
The enable signal PMPEN-NEW of phase is changed into high level, the enable signal in next cycle of first charge pump circuit 411 successively
PMPEN-NEW<1>To the enable signal PMPEN-NEW in next cycle of n-th charge pump circuit 411<n>It is changed into high level
Moment determined by the delay between 411 corresponding input clock signal CLKIN of each charge pump circuit, therefore, it is to avoid multiple electricity
The problem of the work simultaneously of lotus pump circuit 411, reduces the input power noise and output voltage fluctuation of charge pump unit 410.
Charge pump of the present utility model and existing charge pump shown in Fig. 9 is may refer to specifically under same loading condition
Input power noise Simulation comparison of wave shape schematic diagram, wherein the 3rd curve 3 represents charge pump unit of the present utility model 410
Input power noise, the 4th curve 4 represent the input power noise of charge pump unit 410 in prior art, and the 5th curve 5 is represented
The source current of the input of charge pump unit of the present utility model 410, the 6th curve 6 represent charge pump unit in prior art
410 input power electric current, it can be seen that by the technical solution of the utility model, it will be apparent that reduce charge pump unit 410
Input power noise.
Above-mentioned charge pump control unit 430 realizes current period and enables signal PMPEN when being low level, charge pump control
The outfan PMPEN-NEW of unit 430 is low level, and 411 next cycle of corresponding charge pump circuit do not work；Work as current period
Enable signal PMPEN when being high level, and the drive clock of the input clock signal CLKIN in next cycle and current period is believed
When number CLKD is same level, the outfan PMPEN-NEW of charge pump control unit 430 is high level, corresponding charge pump electricity
411 next cycle of road starts work.
A kind of circuit diagram of charge pump control unit that the present embodiment is provided, it is low to realize when current period enables signal
During level, the outfan of charge pump control unit is low level, and corresponding charge pump circuit next cycle does not work；When current week
When the enable signal of phase is high level, and the input clock signal in next cycle is identical with the drive clock signal of current period
During level, the outfan of charge pump control unit is high level, and corresponding charge pump circuit next cycle starts work.
Example IV
Figure 10 is a kind of structural representation of charge pump that this utility model example IV is provided, in the base of above-described embodiment
On plinth, the present embodiment is further optimized, and between charge pump control unit 430 and charge pump circuit 411 increased letter
Number processing unit 440, specifically may refer to shown in Figure 10, and the charge pump includes：
Charge pump unit 410, voltage detection unit 420, at least two charge pump control units 430 and at least two signals
Processing unit 440.
Charge pump unit 410, including at least two charge pump circuits 411, charge pump circuit 411 is connected in parallel with each other, and uses
In each cycle in clock signal clk IN<n>Work or stop under control with enable signal PMPEN-NEW, with output voltage；
The input of voltage detection unit 420 is connected with the outfan of charge pump unit 410, for according to charge pump unit
410 output end voltage VOUT exports the enable signal PMPEN in next cycle to charge pump control with the fiducial value of target voltage values
Unit processed 430；
At least two charge pump control units 430, are corresponded with least two charge pump circuits 411, each charge pump
The first input end of control unit 430 is connected with the outfan of voltage detection unit 420 respectively, for obtaining next cycle
Signal PMPEN is enabled, the second input is used for the drive clock signal CLKD for receiving current period<n>, the 3rd input difference
It is connected with input clock source, for obtaining the input clock signal CLKIN in next cycle<n>, charge pump control unit 430 is used for
Next cycle enable signal PMPEN be high level, the drive clock signal CLKD of current period<n>It is defeated with next cycle
Enter clock signal CLKIN<n>For same level when, produce high level enable signal, otherwise produce low level enable signal, electric charge
The outfan of pump control unit 430 is connected with the Enable Pin of charge pump circuit 411, for export enable signal PMPEN-NEW to
Charge pump circuit 411, wherein, the input clock signal CLKIN of each charge pump circuit<n>Between have Phase delay.
At least two signal processing units 440 and at least two charge pump circuits 411 and at least two charge pumps control list
Unit 430 corresponds, and the first input end of each signal processing unit 440 is connected with the outfan of charge pump control unit 430,
For obtaining the enable signal PMPEN-NEW in next cycle, the second input is connected with input clock source, for obtaining next week
The input clock signal CLKIN of phase, signal processing unit 440 for enable signal PMPEN-NEW control under produce driving
The drive clock signal CLKD and opposite phased driving clock signal CLKDB of next cycle charge pump circuit functions 411, to drive electric charge
Pump circuit 411 works.
Preferably, it is as a kind of implementation of signal processing unit 440, shown in Figure 11, signal processing unit 440
Including：4th phase inverter T4, the second nor gate HF2, the 3rd nor gate HF3, four nor gate HF4 and the 3rd and door Y3,
Wherein, the input of the 4th phase inverter T4 and the 3rd with the first input end of door Y3 respectively with charge pump control unit
430 outfan PMPEN_NEW is connected, and the outfan of the 4th phase inverter T4 is connected with second input of the second nor gate HF2；
The first input end of the second nor gate HF2 and the 3rd is connected with input clock signal CLKIN respectively with second input of door Y3,
The outfan of the second nor gate HF2 is connected with the first input end of the 3rd nor gate HF3；Second input of the 3rd nor gate HF3
End is connected with the outfan of four nor gate HF4, and outfan is connected with the first input end of four nor gate HF4；4th or non-
Second input of door HF4 is connected with the 3rd with the outfan of door Y3.
When the input of the 4th phase inverter T4 and the 3rd and door Y3 first input end signal PMPEN-NEW are high level
When, the drive clock signal CLKD of the next work of cycle charge pump circuit 411 of driving of generation is same with input clock signal CLKIN
Step change；When the input of the 4th phase inverter T4 and the 3rd and door Y3 first input end signal PMPEN-NEW are low level,
The drive clock signal CLKD for driving next work of cycle charge pump circuit 411 is not produced, input clock signal CLKIN is cut
Only.
On the basis of the various embodiments described above, the charge pump also includes input clock source, the input clock source point
It is not connected with charge pump control unit 430, signal processing unit 440, for producing the input clock signal of setpoint frequency
CLKIN。
Note, above are only preferred embodiment of the present utility model and institute's application technology principle.Those skilled in the art's meeting
Understand, this utility model is not limited to specific embodiment described here, can carry out for a person skilled in the art various bright
Aobvious change, readjust and substitute without departing from protection domain of the present utility model.Therefore, although by above example
This utility model is described in further detail, but this utility model is not limited only to above example, without departing from
In the case that this utility model is conceived, more other Equivalent embodiments can also be included, and scope of the present utility model is by appended
Right determine.
Claims (7)
1. a kind of charge pump, it is characterised in that include：
Charge pump unit, the charge pump unit include at least two charge pump circuits, charge pump circuit company parallel with one another
Connect, under the control of clock signal and enable signal work or stop for each cycle, with output voltage；
Voltage detection unit, the input of the voltage detection unit are connected with the outfan of the charge pump unit, for root
The enable signal in next cycle is exported to electric charge according to the output end voltage and the fiducial value of target voltage values of the charge pump unit
Pump control unit；
At least two charge pump control units, are corresponded with least two charge pump circuits, each charge pump control unit
First input end is connected with the outfan of the voltage detection unit respectively, for obtaining the enable signal in next cycle, second
Input is used for the drive clock signal for receiving current period, and the 3rd input is connected with input clock source respectively, for obtaining
The input clock signal in next cycle, the charge pump control unit are high level for the enable signal in next cycle, when
When the drive clock signal and the input clock signal in next cycle in front cycle is same level, produces high level and enable signal,
Otherwise produce low level and enable signal, the outfan of charge pump control unit is connected with the Enable Pin of charge pump circuit, is used
Signal is enabled to the charge pump circuit in exporting, wherein, there is Phase delay between the input clock signal of each charge pump circuit.
2. charge pump according to claim 1, it is characterised in that the voltage detection unit includes division module and enable
Signal output module, wherein, the division module carries out partial pressure for the output end voltage to the charge pump unit；It is described to make
Fiducial value output of the energy signal output module for the output end voltage according to the charge pump unit with target voltage values is enabled
Signal.
3. charge pump according to claim 2, it is characterised in that the division module includes first resistor and second electric
Resistance, the enable signal output module include first comparator, wherein：
The first end of the first resistor is connected with the outfan of the charge pump unit, the second end and the of the second resistance
One end is connected, the second end ground connection of the second resistance；The inverting input of the first comparator and the first resistor
Second end is connected, and normal phase input end is connected with reference voltage, and outfan output enables signal.
4. the charge pump according to claim 1 or 3, it is characterised in that the charge pump control unit includes：First is anti-phase
Device, the second phase inverter, first and door, second and door, the first nor gate, the first NAND gate, the second NAND gate and the 3rd phase inverter,
Wherein, the input of first phase inverter and first is connected with input clock signal respectively with the second input of door,
The outfan of the first phase inverter is connected with second with the first input end of door；The input and first and door of second phase inverter
First input end be connected with the drive clock signal of current period respectively, the outfan of the second phase inverter and second and the of door
Two inputs are connected；First is connected with the first input end of the first nor gate with the outfan of door；Second with the outfan of door with
Second input of the first nor gate is connected；The outfan of the first nor gate is connected with the second input of the second NAND gate；The
The first input end of two NAND gate is connected with the outfan of the first NAND gate, the second input phase of outfan and the first NAND gate
Even；The first input end of the first NAND gate is connected with the outfan of voltage detection unit, the input of outfan and the 3rd phase inverter
End is connected.
5. charge pump according to claim 1, it is characterised in that also include：
At least two signal processing units, with least two charge pump circuit and at least two charge pump control units one by one
Correspondence, the first input end of each signal processing unit is connected with the outfan of charge pump control unit, for obtaining next week
The enable signal of phase, the second input are connected with input clock source, for obtaining the input clock signal in next cycle, the letter
Number processing unit is for producing the drive clock for driving next cycle charge pump circuit functions under the control for enabling signal
Signal and opposite phased driving clock signal, to drive charge pump circuit functions.
6. charge pump according to claim 5, it is characterised in that the signal processing unit includes：4th phase inverter,
Two nor gates, the 3rd nor gate, four nor gate and the 3rd and door,
Wherein, the input of the 4th phase inverter and the 3rd defeated with charge pump control unit respectively with the second input of door
Go out end to be connected, the outfan of the 4th phase inverter is connected with the second input of the second nor gate；First input of the second nor gate
End and the 3rd it is connected with input clock signal with the second input of door respectively, the outfan of the second nor gate and the 3rd nor gate
First input end be connected；Second input of the 3rd nor gate is connected with the outfan of four nor gate, outfan and the 4th
The first input end of nor gate is connected；Second input of four nor gate is connected with the 3rd with the outfan of door.
7. charge pump according to claim 5, it is characterised in that also including input clock source, the input clock source point
It is not connected with charge pump control unit, signal processing unit, for producing the input clock signal of setpoint frequency.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620562240.5U CN206060529U (en) | 2016-06-12 | 2016-06-12 | A kind of charge pump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620562240.5U CN206060529U (en) | 2016-06-12 | 2016-06-12 | A kind of charge pump |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206060529U true CN206060529U (en) | 2017-03-29 |
Family
ID=58372732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620562240.5U Withdrawn - After Issue CN206060529U (en) | 2016-06-12 | 2016-06-12 | A kind of charge pump |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206060529U (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105958817A (en) * | 2016-06-12 | 2016-09-21 | 北京兆易创新科技股份有限公司 | Charge pump circuit |
| CN110619900A (en) * | 2018-06-19 | 2019-12-27 | 南亚科技股份有限公司 | Pump circuit, dynamic random access memory and control method of overall pump current |
| CN111800002A (en) * | 2020-06-28 | 2020-10-20 | 上海华虹宏力半导体制造有限公司 | Peak current control circuit of charge pump |
| CN112104226A (en) * | 2020-11-18 | 2020-12-18 | 深圳市芯天下技术有限公司 | Wide-voltage low-power consumption strong-driving-capability pump circuit and nonvolatile memory |
| CN112422117A (en) * | 2020-11-17 | 2021-02-26 | 深圳市博诺技术有限公司 | Circuit and equipment for automatically switching signals |
-
2016
- 2016-06-12 CN CN201620562240.5U patent/CN206060529U/en not_active Withdrawn - After Issue
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105958817A (en) * | 2016-06-12 | 2016-09-21 | 北京兆易创新科技股份有限公司 | Charge pump circuit |
| CN105958817B (en) * | 2016-06-12 | 2018-05-04 | 北京兆易创新科技股份有限公司 | A kind of charge pump |
| CN110619900A (en) * | 2018-06-19 | 2019-12-27 | 南亚科技股份有限公司 | Pump circuit, dynamic random access memory and control method of overall pump current |
| CN110619900B (en) * | 2018-06-19 | 2021-08-27 | 南亚科技股份有限公司 | Pump circuit, dynamic random access memory and control method of overall pump current |
| CN111800002A (en) * | 2020-06-28 | 2020-10-20 | 上海华虹宏力半导体制造有限公司 | Peak current control circuit of charge pump |
| CN112422117A (en) * | 2020-11-17 | 2021-02-26 | 深圳市博诺技术有限公司 | Circuit and equipment for automatically switching signals |
| CN112104226A (en) * | 2020-11-18 | 2020-12-18 | 深圳市芯天下技术有限公司 | Wide-voltage low-power consumption strong-driving-capability pump circuit and nonvolatile memory |
| CN112104226B (en) * | 2020-11-18 | 2021-02-23 | 深圳市芯天下技术有限公司 | Wide-voltage low-power consumption strong-driving-capability pump circuit and nonvolatile memory |
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