CN112104226B

CN112104226B - Wide-voltage low-power consumption strong-driving-capability pump circuit and nonvolatile memory

Info

Publication number: CN112104226B
Application number: CN202011298169.1A
Authority: CN
Inventors: 蒋丁; 高益; 张柱定
Original assignee: XTX Technology Shenzhen Ltd
Current assignee: Xtx Technology Inc
Priority date: 2020-11-18
Filing date: 2020-11-18
Publication date: 2021-02-23
Anticipated expiration: 2040-11-18
Also published as: CN112104226A

Abstract

The invention discloses a pump circuit with wide voltage and low power consumption and strong driving capability and a nonvolatile memory.A pump circuit body only starts a normally-open charge pump module when input voltage VCC is higher than or equal to a certain set value by arranging an input voltage VCC detection module; when the input voltage VCC is lower than a certain set value, the pump circuit body simultaneously starts the normally-on charge pump module and the closable charge pump module; when only the normally-open charge pump module is started, the clock control pulse signal corresponding to the charge pump module which can be closed in the clock control pulse module is also closed, and redundant current consumption is not generated.

Description

Wide-voltage low-power consumption strong-driving-capability pump circuit and nonvolatile memory

Technical Field

The invention relates to the technical field of microelectronics, in particular to a wide-voltage low-power consumption strong-driving-capability pump circuit and a nonvolatile memory.

Background

High voltage is required to be generated when Flash products operate and progam, and in order to support normal work of the products under a wide power supply voltage and require low power consumption and strong driving capability, a wide-voltage low-power consumption strong-driving-capability pump circuit is promoted.

The conventional wide voltage strong driving capability pump of the memory chip is realized by the manner as shown in fig. 1. The working principle is explained as follows: when CLK =1, the trend of the current is shown in fig. 2; when CLK =0, the current goes as shown in fig. 3; when CLK is switched, current flows continuously from VCC to VOUT, thereby raising the VOUT voltage.

The above circuit has two problems:

1. in the Nor Flash product, the input voltage VCC is required to provide a minimum of 4.8mA of driving current from 1.65V to 3.6V, and VOUT = 4V; when the input voltage VCC is relatively high, the driving current ratio is relatively easy to meet, and when VCC is relatively low, all mos transistors and capacitors are required to be made to be particularly large in order to meet the driving capability, so that the whole circuit meets the condition that VCC is relatively low, but the driving current of the whole circuit can reach more than 10mA under the condition that VCC is relatively high, and design redundancy is caused.

2. Moreover, due to the redundancy design, the capacitance is large, and when the clock is switched continuously, the capacitance consumes large useless power consumption.

Therefore, the prior art still needs to be improved and developed.

Disclosure of Invention

The invention aims to provide a pump circuit with wide voltage, low power consumption and strong driving capability and a nonvolatile memory, and aims to solve the problems that in order to meet the driving requirement of low input voltage, an mos tube and a capacitor are specially large, and design redundancy is caused when the input voltage is high in the conventional pump circuit; and the problem that the large capacitor of the redundancy design consumes large useless power consumption when the clock is switched continuously is solved.

The technical scheme of the invention is as follows: a wide-voltage low-power consumption strong-driving-capability pump circuit includes:

the pump circuit body comprises a normally-on charge pump module and a closable charge pump module;

the clock control pulse module is used for providing clock control pulses for the normally-open charge pump module and the closable charge pump module;

the input voltage VCC detection module is used for detecting the magnitude of the input voltage VCC;

the pump circuit body is connected with the clock control pulse module, the input voltage VCC detection module is connected with the clock control pulse module, and the input voltage VCC detection module is connected with the charge pump module which can be closed; when the input voltage VCC detection module detects that the input voltage VCC is greater than or equal to a certain set value, the clock control pulse signal corresponding to the charge pump module which can be closed in the charge pump module and the clock control pulse module is controlled to be closed, and when the input voltage VCC detection module detects that the input voltage VCC is less than a certain set value, the clock control pulse signal corresponding to the charge pump module which can be closed in the clock control pulse module is not closed.

The wide-voltage low-power consumption strong-driving-capability pump circuit comprises a normally-on charge pump module and a closable charge pump module, wherein the normally-on charge pump module comprises at least one stage of charge pump, and the closable charge pump module comprises at least one stage of charge pump.

The wide-voltage low-power consumption strong-driving-capability pump circuit comprises a normally-open charge pump module, a normally-open charge pump module and a normally-open charge pump module, wherein the normally-open charge pump module comprises two stages of charge pumps, namely a first charge pump and a second charge pump; the closable charge pump module comprises a first charge pump which is a third charge pump.

The wide-voltage low-power-consumption high-driving-capability pump circuit comprises a first nmos tube N1, a second nmos tube N2, a first pmos tube P1 and a second pmos tube P2, wherein a drain electrode of the first nmos tube N1 is connected with a drain electrode of the second nmos tube N2 and then connected to an input voltage VCC, a gate electrode of the first nmos tube N1 is connected with a source electrode of the second nmos tube N2, and a gate electrode of the second nmos tube N2 is connected with a source electrode of the first nmos tube N1; the source of the first pmos transistor P1 and the source of the second pmos transistor P2 are connected together and then connected to the second charge pump, the gate of the first pmos transistor P1 and the drain of the second pmos transistor P2 are connected, the drain of the first pmos transistor P1 and the gate of the second pmos transistor P2 are connected, the source of the first nmos transistor N1 and the drain of the first pmos transistor P1 are connected together and then connected to the clock control pulse block, and the source of the second nmos transistor N2 and the drain of the second pmos transistor P2 are connected together and then connected to the clock control pulse block.

The wide-voltage low-power-consumption pump circuit with strong driving capability comprises a second charge pump, a third charge pump and a fourth charge pump, wherein the second charge pump comprises a third nmos tube N3, a fourth nmos tube N4, a third pmos tube P3 and a fourth pmos tube P4, the drain electrode of the third nmos tube N3 is connected with the drain electrode of the fourth nmos tube N4 and then connected with the first charge pump, the gate electrode of the third nmos tube N3 is connected with the source electrode of the fourth nmos tube N4, and the gate electrode of the fourth nmos tube N4 is connected with the source electrode of the third nmos tube N3; the source of the third pmos transistor P3 and the source of the fourth pmos transistor P4 are connected together and then connected to the third charge pump, the gate of the third pmos transistor P3 and the drain of the fourth pmos transistor P4 are connected, the drain of the third pmos transistor P3 and the gate of the fourth pmos transistor P4 are connected, the source of the third nmos transistor N3 and the drain of the third pmos transistor P3 are connected together and then connected to the clock control pulse block, and the source of the fourth nmos transistor N4 and the drain of the fourth pmos transistor P4 are connected together and then connected to the clock control pulse block.

The wide-voltage low-power-consumption high-driving-capability pump circuit comprises a fifth nmos tube N5, a sixth nmos tube N6, a fifth pmos tube P5 and a sixth pmos tube P6, wherein a drain electrode of the fifth nmos tube N5 is connected with a drain electrode of a sixth nmos tube N6 and then connected with a second charge pump, a drain electrode of the fifth nmos tube N5 is connected with a drain electrode of a sixth nmos tube N6 and then connected with an input voltage VCC detection module, a gate electrode of the fifth nmos tube N5 is connected with a source electrode of a sixth nmos tube N6, and a gate electrode of the sixth nmos tube N6 is connected with a source electrode of a fifth nmos tube N5; the source of a fifth pmos tube P5 and the source of a sixth pmos tube P6 are connected together and then connected with a signal output terminal VOUT, the source of the fifth pmos tube P5 and the source of the sixth pmos tube P6 are connected together and then connected with an input voltage VCC detection module, the gate of the fifth pmos tube P5 and the drain of the sixth pmos tube P6 are connected, the drain of the fifth pmos tube P5 and the gate of the sixth pmos tube P6 are connected, the source of a fifth nmos tube N5 and the drain of the fifth pmos tube P5 are connected together and then connected with a clock control pulse module, and the source of the sixth nmos tube N6 and the drain of the sixth pmos tube P6 are connected together and then connected with the clock control pulse module; the second charge pump is connected with the signal output end VOUT, and the input voltage VCC detection module is connected between the second charge pump and the signal output end VOUT.

The wide-voltage low-power-consumption strong-driving-capability pump circuit comprises a clock control pulse module, a first NOT1, an amplifier A, a second NOT2, a first AND gate AND1 AND a second AND gate AND2, wherein the input end of the first NOT1 is connected with a clock control pulse signal CLK, the output end of the first NOT1 is connected with the input end of the amplifier A, the output end of the amplifier A is connected with one input end of a first AND gate AND1, the other input end of the first AND gate AND1 is connected with an input voltage VCC detection module, the output end of the amplifier A is connected with a first charge pump, the output end of the amplifier A is connected with a second charge pump, AND the output end of the first AND gate AND1 is connected with a third charge pump; the output end of the first NOT gate NOT1 is connected with the input end of the second NOT gate NOT2, the output end of the second NOT gate NOT2 is connected with one input end of the second AND gate AND2, the other input end of the second AND gate AND2 is connected with the input voltage VCC detection module, the output end of the second NOT gate NOT2 is connected with the first charge pump, the output end of the second NOT gate NOT2 is connected with the second charge pump, AND the output end of the second AND gate NOT2 is connected with the third charge pump.

The wide-voltage low-power-consumption strong-driving-capability pump circuit comprises an input voltage VCC detection module, a voltage conversion module and a control module, wherein the input voltage VCC detection module comprises a seventh nmos tube N7, a seventh pmos tube P7, an eighth nmos tube N8, a ninth nmos tube N9, a comparator CMP, a Level converter Level _ shift, a third NOT3 and a fourth NOT4, a drain of the seventh nmos tube N7 and a drain of the seventh pmos tube P7 are connected together and then connected with an input voltage VCC, a gate of the seventh nmos tube N7 is connected with an input end of the fourth NOT4, a gate of the seventh pmos tube P7 is connected with an output end of the fourth NOT4, a source of the seventh nmos tube N7 and a source of the seventh pmos tube P7 are connected together and then connected with a drain of the eighth nmos tube N8, a source of the eighth nmos tube N8 and a source of the ninth pmos tube P3527 are connected together and then connected with a drain of the ninth nmos tube N9, and a drain of the ninth nmos tube N9; the source electrode of the eighth nmos transistor N8 and the gate electrode of the eighth nmos transistor N8 are connected together and then connected with one input end of a comparator CMP, the other input end of the comparator CMP is connected with a reference voltage Vref _1p2, the output end of the comparator CMP is connected with the input end of a Level shifter Level _ shift, and the output end of the comparator CMP is connected with the input end of a third NOT gate 3; the output end of the third NOT3 is connected with the clock control pulse module; one output end of the Level shifter Level _ shift is connected with the third charge pump, and the other output end of the Level shifter Level _ shift is connected between the second charge pump and the signal output end VOUT.

A nonvolatile memory comprising the wide-voltage low-power consumption strong-driving-capability pump circuit as described in any one of the above.

The invention has the beneficial effects that: the invention provides a pump circuit with wide voltage and low power consumption and strong driving capability and a nonvolatile memory.A pump circuit body only starts a normally-open charge pump module when input voltage VCC is higher than or equal to a certain set value by arranging an input voltage VCC detection module; when the input voltage VCC is lower than a certain set value, the pump circuit body simultaneously starts the normally-on charge pump module and the closable charge pump module; when only the normally-open charge pump module is started, the clock control pulse signal corresponding to the charge pump module which can be closed in the clock control pulse module is also closed, and redundant current consumption is not generated.

Drawings

Fig. 1 is a schematic diagram of a wide-voltage low-power consumption high-driving-capability pump circuit in the prior art.

Fig. 2 is a schematic diagram of a current trend of a wide-voltage low-power consumption strong driving capability pump circuit in the prior art when CLK = 1.

Fig. 3 is a schematic diagram of a current trend of a wide-voltage low-power consumption strong driving capability pump circuit in the prior art when CLK = 0.

Fig. 4 is a schematic diagram of a wide-voltage low-power consumption high-driving-capability pump circuit according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

As shown in fig. 1, a wide-voltage low-power consumption strong driving capability pump circuit includes:

the pump circuit body 1 comprises a normally-on charge pump module and a closable charge pump module;

the clock control pulse module 2 is used for providing clock control pulses for the normally-open charge pump module and the closable charge pump module;

an input voltage VCC detection module 3 for detecting the magnitude of the input voltage VCC;

the pump circuit body 1 is connected with the clock control pulse module 2, the input voltage VCC detection module 3 is connected with the clock control pulse module 2, and the input voltage VCC detection module 3 is connected with the closable charge pump module; when the input voltage VCC detection module 3 detects that the input voltage VCC is greater than or equal to a certain set value, the clock control pulse signal corresponding to the charge pump module that can be turned off in the charge pump module that can be turned off and the clock control pulse module 2 is controlled to be turned off, and when the input voltage VCC detection module 3 detects that the input voltage VCC is less than a certain set value, the clock control pulse signal corresponding to the charge pump module that can be turned off in the charge pump module that can be turned off and the clock control pulse module 2 is not turned off.

In some embodiments, the normally-on charge pump module comprises at least one stage of charge pump and the closable charge pump module comprises at least one stage of charge pump.

In this embodiment, the normally-open charge pump module includes two charge pumps, namely a first charge pump and a second charge pump; the closable charge pump module comprises a first charge pump which is a third charge pump.

In some embodiments, the first charge pump includes a first nmos transistor N1, a second nmos transistor N2, a first pmos transistor P1, and a second pmos transistor P2, a drain of the first nmos transistor N1 and a drain of the second nmos transistor N2 are connected together and then connected to an input voltage VCC, a gate of the first nmos transistor N1 is connected to a source of the second nmos transistor N2, and a gate of the second nmos transistor N2 is connected to a source of the first nmos transistor N1; the source of the first pmos transistor P1 and the source of the second pmos transistor P2 are connected together and then connected to the second charge pump, the gate of the first pmos transistor P1 and the drain of the second pmos transistor P2 are connected, the drain of the first pmos transistor P1 and the gate of the second pmos transistor P2 are connected, the source of the first nmos transistor N1 and the drain of the first pmos transistor P1 are connected together and then connected to the clock control pulse block 2, and the source of the second nmos transistor N2 and the drain of the second pmos transistor P2 are connected together and then connected to the clock control pulse block 2.

In some embodiments, the second charge pump includes a third nmos tube N3, a fourth nmos tube N4, a third pmos tube P3, and a fourth pmos tube P4, a drain of the third nmos tube N3 and a drain of the fourth nmos tube N4 are connected together and then connected to the first charge pump (in this embodiment, a drain of the third nmos tube N3 and a drain of the fourth nmos tube N4 are connected together and then connected to a source of the first pmos tube P1), a gate of the third nmos tube N3 is connected to a source of the fourth nmos tube N4, and a gate of the fourth nmos tube N4 is connected to a source of the third nmos tube N3; the source of the third pmos transistor P3 and the source of the fourth pmos transistor P4 are connected together and then connected to the third charge pump, the gate of the third pmos transistor P3 and the drain of the fourth pmos transistor P4 are connected, the drain of the third pmos transistor P3 and the gate of the fourth pmos transistor P4 are connected, the source of the third nmos transistor N3 and the drain of the third pmos transistor P3 are connected together and then connected to the clock control pulse block 2, and the source of the fourth nmos transistor N4 and the drain of the fourth pmos transistor P4 are connected together and then connected to the clock control pulse block 2.

In some embodiments, the third charge pump includes a fifth nmos tube N5, a sixth nmos tube N6, a fifth pmos tube P5, and a sixth pmos tube P6, a drain of the fifth nmos tube N5 is connected to a drain of the sixth nmos tube N6 and then connected to the second charge pump (in this embodiment, a drain of the fifth nmos tube N5 is connected to a drain of the sixth nmos tube N6 and then connected to a source of the third pmos tube P3), a drain of the fifth nmos tube N5 is connected to a drain of the sixth nmos tube N6 and then connected to the input voltage VCC detection module 3, a gate of the fifth nmos tube N5 is connected to a source of the sixth nmos tube N6, and a gate of the sixth nmos tube N6 is connected to a source of the fifth nmos tube N5; the source of the fifth pmos transistor P5 and the source of the sixth pmos transistor P6 are connected together and then connected to the signal output terminal VOUT, the source of the fifth pmos transistor P5 and the source of the sixth pmos transistor P6 are connected together and then connected to the input voltage VCC detection module 3, the gate of the fifth pmos transistor P5 and the drain of the sixth pmos transistor P6 are connected, the drain of the fifth pmos transistor P5 and the gate of the sixth pmos transistor P6 are connected, the source of the fifth nmos transistor N5 and the drain of the fifth pmos transistor P5 are connected together and then connected to the clock control pulse module 2, and the source of the sixth nmos transistor N6 and the drain of the sixth pmos transistor P6 are connected together and then connected to the clock control pulse module 2; the second charge pump is connected with the signal output end VOUT, and the input voltage VCC detection module 3 is connected between the second charge pump and the signal output end VOUT.

In some embodiments, the clock control pulse module 2 includes a first NOT gate NOT1, an amplifier a, a second NOT gate NOT2, a first AND gate AND1, AND a second AND gate AND2, an input terminal of the first NOT gate NOT1 is connected to the clock control pulse signal CLK, an output terminal of the first NOT gate NOT1 is connected to an input terminal of the amplifier a, an output terminal of the amplifier a is connected to one input terminal of the first AND gate 1, the other input terminal of the first AND gate 1 is connected to the input voltage VCC detecting module 3, an output terminal of the amplifier a is connected to the first charge pump (in this embodiment, a source of the second nmos transistor N2 AND a drain of the second pmos transistor P2 are connected together AND then connected to an output terminal of the amplifier a), an output terminal of the amplifier a is connected to the second charge pump (in this embodiment, a source of the third nmos transistor N3 AND a drain of the third pmos transistor P3 are connected together AND then connected to an output terminal of the amplifier a), the output terminal of the first AND gate AND1 is connected to the third charge pump (in this embodiment, the source of the sixth nmos transistor N6 AND the drain of the sixth pmos transistor P6 are connected together AND then connected to the output terminal of the first AND gate AND 1); an output terminal of the first NOT gate NOT1 is connected to an input terminal of the second NOT gate NOT2, an output terminal of the second NOT gate NOT2 is connected to one input terminal of the second AND gate AND2, the other input terminal of the second AND gate AND2 is connected to the input voltage VCC detection module 3, an output terminal of the second NOT gate NOT2 is connected to the first charge pump (in this embodiment, a source of the first nmos tube N1 is connected to a drain of the first pmos tube P1 AND then connected to an output terminal of the second NOT gate NOT 2), an output terminal of the second NOT gate NOT2 is connected to the second charge pump (in this embodiment, a source of the fourth nmos tube N4 AND a drain of the fourth pmos tube P4 are connected together AND then connected to an output terminal of the second NOT gate NOT 2), AND an output terminal of the second AND gate 2 is connected to the third charge pump (in this embodiment, a source of the fifth nmos tube N5 is connected to a drain of the fifth pmos tube P5 AND gate AND 2).

In some embodiments, the input voltage VCC detection module 3 includes a seventh nmos tube N7, a seventh pmos tube P7, an eighth nmos tube N8, a ninth nmos tube N9, a comparator CMP, a Level shifter Level _ shift, a third NOT gate NOT3, and a fourth NOT gate NOT4, a drain of the seventh nmos tube N7 and a drain of the seventh pmos tube P7 are connected together and then connected to the input voltage VCC, a gate of the seventh nmos tube N7 is connected to an input of the fourth NOT gate NOT4, a gate of the seventh pmos tube P7 is connected to an output of the fourth NOT gate NOT4, a source of the seventh nmos tube N7 and a source of the seventh pmos tube P7 are connected together and then connected to a drain of the eighth nmos tube N8, a source of the eighth nmos tube N8 and a source of the eighth nmos tube N356 are connected together and then connected to the drain of the ninth nmos tube N9, and a drain of the ninth nmos tube N9 are connected together; the source electrode of the eighth nmos transistor N8 and the gate electrode of the eighth nmos transistor N8 are connected together and then connected with one input end of a comparator CMP, the other input end of the comparator CMP is connected with a reference voltage Vref _1p2, the output end of the comparator CMP is connected with the input end of a Level shifter Level _ shift, and the output end of the comparator CMP is connected with the input end of a third NOT gate 3; the output end of the third NOT gate NOT3 is connected to the clock control pulse module 2 (in this embodiment, the output end of the third NOT gate NOT3 is connected to the other input end of the first AND gate AND1, AND the output end of the third NOT gate NOT3 is connected to the other input end of the second AND gate AND 2); one output end of the Level shifter Level _ shift is connected with the third charge pump (in this embodiment, the drain of the fifth nmos tube N5 is connected with the drain of the sixth nmos tube N6, and then connected with one output end of the Level shifter Level _ shift), and the other output end of the Level shifter Level _ shift is connected between the second charge pump and the signal output end VOUT.

According to the technical scheme, the pump circuit body 1 only starts the normally-open charge pump module when the input voltage VCC is higher than or equal to a set value (such as 2.4V) by arranging the input voltage VCC detection module 3; when the input voltage VCC is lower than a certain set value (such as 2.4V), the pump circuit body 1 starts the normally-on charge pump module and the closable charge pump module at the same time; when only the normally-open charge pump module is started, the clock control pulse signal corresponding to the charge pump module which can be closed in the clock control pulse module 2 is also closed, and redundant current consumption is not generated.

When the input voltage VCC is greater than or equal to a certain set value and the en signal is 1, the eighth nmos transistor N8 and the first nmos transistor N9 are equivalent to two equal resistors, and Vhalf is greater than or equal to the reference voltage Vref _1p2, and Sel =1 and Sel _ b =0 are known through the comparator CMP, so that f2_ s and f1_ s are pulled low, and the charge pump module can be turned off. Sel =1 obtains Sel _ HV = H (1 of high voltage) through Level shifter Level _ shift, Sel _ HV _ B =0, and turns off the charge pump module, and simultaneously eliminates the current consumed by the charge pump module.

When the input voltage VCC is less than a set value and the en signal is 1, Vhalf is less than the reference voltage Vref _1p2, and Sel =0 and Sel _ b =1 are known by the comparator CMP, so that f2_ s and f1_ s are enabled, and the charge pump module is turned on and turned off. Sel =0 obtains Sel _ HV =0 and Sel _ HV _ B =1 (1 of high voltage) through Level shifter Level _ shift, and turns on the charge pump module which can be turned off, and simultaneously satisfies the driving capability of the pump circuit body 1 under low power supply.

The technical scheme also protects a nonvolatile memory which comprises the wide-voltage low-power consumption high-driving-capacity pump circuit.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A wide-voltage low-power consumption strong-driving-capability pump circuit is characterized by comprising:

the pump circuit body comprises a normally-on charge pump module and a closable charge pump module, wherein the normally-on charge pump module comprises two stages of charge pumps which are a first charge pump and a second charge pump respectively; the closable charge pump module comprises a first-stage charge pump which is a third charge pump;

the clock control pulse module is used for providing clock control pulse signals for the normally-open charge pump module and the closable charge pump module;

the pump circuit body is connected with the clock control pulse module, the input voltage VCC detection module is connected with the clock control pulse module, and the input voltage VCC detection module is connected with the charge pump module which can be closed; when the input voltage VCC detection module detects that the input voltage VCC is more than or equal to a certain set value, controlling to close the clock control pulse signal corresponding to the charge pump module which can be closed in the charge pump module which can be closed and the clock control pulse module;

the input voltage VCC detection module comprises a seventh nmos tube N7, a seventh pmos tube P7, an eighth nmos tube N8, a ninth nmos tube N9, a comparator CMP, a Level shifter Level _ shift, a third NOT gate NOT3 and a fourth NOT gate NOT4, wherein the drain of the seventh nmos tube N7 and the drain of the seventh pmos tube P7 are connected together and then connected with an input voltage VCC, the gate of the seventh nmos tube N7 is connected with the input end of the fourth NOT gate NOT4, the gate of the seventh pmos tube P7 is connected with the output end of the fourth NOT gate NOT4, the source of the seventh nmos tube N7 and the source of the seventh pmos tube P7 are connected together and then connected with the drain of the eighth nmos tube N8, the source of the eighth nmos tube N8 and the source of the eighth pmos tube N636 are connected together and then connected with the drain of the ninth gate of the ninth nmos tube N9, and the drain of the ninth nmos tube N9 is connected together and the ninth gate 9; the source electrode of the eighth nmos transistor N8 and the gate electrode of the eighth nmos transistor N8 are connected together and then connected with one input end of a comparator CMP, the other input end of the comparator CMP is connected with a reference voltage Vref _1p2, the output end of the comparator CMP is connected with the input end of a Level shifter Level _ shift, and the output end of the comparator CMP is connected with the input end of a third NOT gate 3; the output end of the third NOT3 is connected with the clock control pulse module; one output end of the Level shifter Level _ shift is connected with the third charge pump, and the other output end of the Level shifter Level _ shift is connected between the second charge pump and the signal output end VOUT.

2. The wide-voltage low-power-consumption strong-driving-capability pump circuit as claimed in claim 1, wherein the first charge pump comprises a first nmos transistor N1, a second nmos transistor N2, a first pmos transistor P1 and a second pmos transistor P2, a drain of the first nmos transistor N1 is connected with a drain of the second nmos transistor N2 and then connected to an input voltage VCC, a gate of the first nmos transistor N1 is connected with a source of the second nmos transistor N2, and a gate of the second nmos transistor N2 is connected with a source of the first nmos transistor N1; the source of the first pmos transistor P1 and the source of the second pmos transistor P2 are connected together and then connected to the second charge pump, the gate of the first pmos transistor P1 and the drain of the second pmos transistor P2 are connected, the drain of the first pmos transistor P1 and the gate of the second pmos transistor P2 are connected, the source of the first nmos transistor N1 and the drain of the first pmos transistor P1 are connected together and then connected to the clock control pulse block, and the source of the second nmos transistor N2 and the drain of the second pmos transistor P2 are connected together and then connected to the clock control pulse block.

3. The wide-voltage low-power-consumption strong-driving-capability pump circuit as claimed in claim 1, wherein the second charge pump comprises a third nmos tube N3, a fourth nmos tube N4, a third pmos tube P3 and a fourth pmos tube P4, a drain of the third nmos tube N3 is connected with a drain of a fourth nmos tube N4 and then connected with the first charge pump, a gate of the third nmos tube N3 is connected with a source of the fourth nmos tube N4, and a gate of the fourth nmos tube N4 is connected with a source of the third nmos tube N3; the source of the third pmos transistor P3 and the source of the fourth pmos transistor P4 are connected together and then connected to the third charge pump, the gate of the third pmos transistor P3 and the drain of the fourth pmos transistor P4 are connected, the drain of the third pmos transistor P3 and the gate of the fourth pmos transistor P4 are connected, the source of the third nmos transistor N3 and the drain of the third pmos transistor P3 are connected together and then connected to the clock control pulse block, and the source of the fourth nmos transistor N4 and the drain of the fourth pmos transistor P4 are connected together and then connected to the clock control pulse block.

4. The wide-voltage low-power-consumption strong-driving-capability pump circuit as claimed in claim 1, wherein the third charge pump comprises a fifth nmos tube N5, a sixth nmos tube N6, a fifth pmos tube P5 and a sixth pmos tube P6, a drain of the fifth nmos tube N5 is connected with a drain of the sixth nmos tube N6 and then connected with the second charge pump, a drain of the fifth nmos tube N5 is connected with a drain of the sixth nmos tube N6 and then connected with the input voltage VCC detection module, a gate of the fifth nmos tube N5 is connected with a source of the sixth nmos tube N6, and a gate of the sixth nmos tube N6 is connected with a source of the fifth nmos tube N5; the source of a fifth pmos tube P5 and the source of a sixth pmos tube P6 are connected together and then connected with a signal output terminal VOUT, the source of the fifth pmos tube P5 and the source of the sixth pmos tube P6 are connected together and then connected with an input voltage VCC detection module, the gate of the fifth pmos tube P5 and the drain of the sixth pmos tube P6 are connected, the drain of the fifth pmos tube P5 and the gate of the sixth pmos tube P6 are connected, the source of the fifth nmos tube N5 and the drain of the fifth pmos tube P5 are connected together and then connected with a clock control pulse module, and the source of the sixth nmos tube N6 and the drain of the sixth pmos tube P6 are connected together and then connected with the clock control pulse module; the second charge pump is connected with the signal output end VOUT, and the input voltage VCC detection module is connected between the second charge pump and the signal output end VOUT.

5. The wide-voltage low-power-consumption strong-driving-capability pump circuit according to claim 1, wherein the clock control pulse module comprises a first NOT gate NOT1, an amplifier a, a second NOT gate NOT2, a first AND gate AND1 AND a second AND gate AND2, an input end of the first NOT gate NOT1 is connected with a clock control pulse signal CLK, an output end of the first NOT gate NOT1 is connected with an input end of the amplifier a, an output end of the amplifier a is connected with one input end of the first AND gate AND1, the other input end of the first AND gate AND1 is connected with the input voltage VCC detection module, an output end of the amplifier a is connected with the first charge pump, an output end of the amplifier a is connected with the second charge pump, AND an output end of the first AND gate 1 is connected with the third charge pump; the output end of the first NOT gate NOT1 is connected with the input end of the second NOT gate NOT2, the output end of the second NOT gate NOT2 is connected with one input end of the second AND gate AND2, the other input end of the second AND gate AND2 is connected with the input voltage VCC detection module, the output end of the second NOT gate NOT2 is connected with the first charge pump, the output end of the second NOT gate NOT2 is connected with the second charge pump, AND the output end of the second AND gate NOT2 is connected with the third charge pump.

6. A nonvolatile memory comprising the wide-voltage low-power consumption strong-driving-capability pump circuit as claimed in any one of claims 1 to 5.