JP2000105611A - Charge pump circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a charge pump circuit remarkably improved in boosting efficiency. SOLUTION: A boosting potential obtained by the charge pump circuit is outputted through an operational amplifier OP. Thus, the stabilization of the boosting potential can be attained. Besides, plural potentials VR1-VR4 dropped by dividing the resistance of output from the operational amplifier OP are generated and these potentials are supplies as the substrate potentials of respective correspondent MOSFET MN1-MN4. Thus, a back gate bias voltage to be impressed to respective MOSFET can be reduced in comparison with the conventional one, and the boosting efficiency is remarkably improved and a high output current can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a charge pump circuit, and more particularly, to a charge pump circuit having greatly improved boosting efficiency.

[0002]

2. Description of the Related Art A nonvolatile semiconductor memory device, for example, an EEPROM (Electrical) capable of electrically erasing data.
ly Erasable Programmable Memory) requires a high voltage of about 12 V when writing data. Further, a driving IC for driving various display devices such as a liquid crystal display device and an LED display device also requires a positive or negative high voltage power supply. Therefore, in general, EEP
A charge pump circuit is built in a ROM or a driving IC, and a high voltage is obtained by boosting a power supply of about 3 V to 5 V.

A conventional charge pump circuit is disclosed in, for example, JP-A-2-276467 and JP-A-8-103070. FIG. 6 is a circuit diagram showing a first conventional charge pump circuit. The configuration of this charge pump circuit is such that N-channel MOSFETs (MN1 to MN4) having a gate and a drain connected to each other are connected in series,
Capacitors (C1) are connected to nodes (N1 to N4) which are connection points between gates and drains of the MOSFETs (MN1 to MN4).
To C4), and clocks CK1 and CK2 having phases opposite to each other are alternately connected to the other ends of the capacitive elements (C1 to C4). That is, a unit block including each MOSFET and each capacitance element is connected in series. Further, an N-channel MOSFET (MN1)
The gate and the drain of the N-channel MOSFET (M
N0) to the power supply voltage Vdd, and the source of the N-channel MOSFET (MN4) is used as the output HV. Next, the operation of the charge pump circuit will be described.
When the clock CK1 is at the low level, as an initial state,
The potential of the node N1 is set to an N-channel MOSFET (MN
(Vdd-Vt0-ΔV)
It is charged at t0). Here, Vth is an N-channel type M
OSFET (MN0) threshold voltage (Threshold Volt
age), and ΔVt0 is a variation in threshold voltage due to the back gate bias effect. And clock C
When K1 becomes high level, the potential of the node N1 increases by the voltage Vup represented by the following equation due to the effect of capacitive coupling. Vup = Vdd × (C1 / C1 + CN1) (1) Here, CN1 is a parasitic capacitance of the node N1. Therefore, the potential VN1 of the node N1 after boosting is represented by the following equation. VN1 = (Vdd−Vt0−ΔVt0) + Vup (2) Since the clock CK2 is at the low level, the potential of the node N2 is pushed down. Here, when the following conditional expression is satisfied, the charge moves from the node N1 to the node N2, and the current I
2 flows.

VN2−VN1> Vt1 + ΔVt1 (3) The current I2 raises the potential of the node N2 to a potential represented by the following equation. VN2 = VN1−Vt1−ΔVt1 (4) After that, when the clock CK2 changes to a high level, the potential of the node N2 rises to a high voltage by capacitive coupling according to the same operation principle as described above, and the node N2 changes to the node As a result of the charge moving to N3, the potential of the node N3 increases. In this manner, the charge is sequentially moved from the first-stage MOSFET (MN1) to the last-stage MOSFET (MN4), and the voltage is boosted so that the higher the voltage is, the closer to the node of the subsequent block. And the last stage MOSFET
A high voltage is obtained at the source of (MN4), that is, at the output HV. However, when the potential of the nodes (N1 to N4) increases, the variation ΔVt of the threshold voltage increases due to the back gate bias voltage Vbs (voltage between the source and the substrate). Is not satisfied, and the current no longer flows through the MOSFET. This state is the limit of boosting. That is, when the number of stages in the block is sufficient, the limit of the boosting is caused by the variation ΔVt of the threshold voltage. In order to improve the boosting efficiency due to such a back gate bias effect, a second charge pump circuit shown in FIG. 7 has been proposed. In the configuration of this charge pump circuit, the substrate potential of the N-channel MOSFETs (MN0 to MN2) is set to the ground potential (0 V),
The substrate potentials N3 to MN4) are set to the power supply potential Vdd. Other components are the same as those of the first charge pump circuit. According to the second charge pump circuit, by increasing the substrate potential, the MOSFET (MN3 to MN4)
, A substantial back gate bias voltage applied thereto is reduced, and boosting efficiency can be improved.

[0005]

However, according to the second charge pump circuit, the MOSFET (MN
3 to MN4) is the power supply potential Vdd, and this potential is usually about 5V. Therefore, when obtaining a voltage of, for example, 12 V as the output HV, the back gate bias voltage Vbs of the MOSFET (MN4) is (12-5) = 7V. This back gate bias voltage Vbs (7 V) is suppressed lower than that of the first charge pump circuit. However, the variation ΔVt of the threshold voltage due to the back gate bias voltage Vbs (7 V) was about 1 V, and it was difficult to achieve sufficient boosting efficiency. When the charge pump circuit is used as a power supply for a display device driving IC,
A large output current of several mA to several tens mA together with a high voltage is required. However, the fluctuation of the threshold voltage due to the back gate bias effect increases the on-resistance of the MOSFET, thereby limiting the output current. Further, the fact that the back gate bias voltage Vbs is 7 V means that a voltage of 7 V is applied to the PN junction formed between the source / drain of the MOSFET and the substrate, which is different from the MOSFET used in the 5 V system. It is necessary to use a high withstand voltage MOSFET which has been described. This high voltage MOSFET is a MOSFE used in a 5V system.
Since it has a structure in which the thickness of the gate oxide film is large and the junction depth of the source and drain is large as compared with T, high integration is difficult and the manufacturing cost is high. Furthermore,
In the charge pump circuit, since a clock is applied to the capacitors (C1 to C4) and the voltage is boosted by the capacitive coupling, a voltage fluctuation occurs in the output HV with the voltage amplitude of the clock, and the output HV is used as a power supply. Has a disadvantage that the power supply potential is not stable.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a charge pump circuit in which boost efficiency is greatly improved. It is another object of the present invention to provide a charge pump circuit that can obtain a high voltage output as well as a high voltage output. Still another object of the present invention is to provide a charge pump circuit capable of realizing a stabilized high-voltage power supply circuit. In order to achieve the above object, a charge pump circuit of the present invention outputs a boosted potential obtained by a conventional charge pump circuit through an operational amplifier (operational amplifier). Thereby, the boosted potential can be stabilized. Also, the charge pump circuit of the present invention generates a plurality of stepped-down potentials by dividing the output of the operational amplifier by resistance,
The potential is supplied as the substrate potential of each corresponding MOSFET. As a result, the back gate bias voltage applied to each MOSFET can be reduced as compared with the related art, so that the boosting efficiency can be greatly improved and a high output current can be obtained. Further, as the back gate bias voltage decreases, the source
The voltage applied to the PN junction formed between the drain and the substrate can be reduced, and there is no need to use a high breakdown voltage MOSFET.

[0007]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a charge pump circuit according to the first embodiment. In this charge pump circuit, N-channel MOSFETs (MN1 to MN4) having a gate and a drain connected to each other are connected in series,
Capacitors (C1) are connected to nodes (N1 to N4) which are connection points between gates and drains of the MOSFETs (MN1 to MN4).
To C4), and clocks CK1 and CK2 having phases opposite to each other are alternately connected to the other ends of the capacitive elements (C1 to C4). That is, a unit block including each MOSFET and each capacitance element is connected in series. Further, an N-channel MOSFET (MN1)
The gate and the drain of the N-channel MOSFET (M
N0) to the power supply voltage Vdd, and the source of the N-channel MOSFET (MN4) is used as the output HV.

The output HV is supplied to the operational amplifier OP
Power supply. The output HV has a capacitance C5 (about 50 pF) in order to alleviate voltage fluctuations to some extent.
May be added. One input of the operational amplifier OP, that is, a non-inverting input terminal (+) is supplied with the reference potential Vref. A resistor R1 is connected between the output Vop of the operational amplifier OP and the ground potential, and four potentials VR1 to VR1 which are stepped down from respective points on the resistor R1 by resistance division.
VR4 is taken out. Since Vop is a positive high voltage, it is clear that Vop ≧ VR4>VR3>VR2>VR1> 0V. Among them, VR2 is supplied to the other input of the operational amplifier OP, that is, the inverted input (-). To obtain 12V as the output Vop,
The resistance division ratio (r1 + r2) / r1 may be determined so that VR2 = reference potential Vref and Vop = 12V. Here, since (r1 + r2) / r1 = Vop / Vref holds, when Vref = 4V, this division ratio may be set to (12/4) = 3. Further, the above potentials VR1 to VR4 are set to the corresponding MOSFETs (MN
1 to MN4). That is,
The highest potential V is applied to the substrate potential of the MOSFET (MN4).
R4 is supplied, and the next highest potential VR3 is supplied to the substrate potential of the MOSFET (MN3). The following is the same. Since the boosted potential becomes higher at the node of the MOSFET in the latter stage, the back gate bias voltage can be individually minimized by gradually increasing the substrate potential. Note that a capacitance C6 (about 100 pF) may be added to the operational amplifier to further stabilize the output Vop. FIG. 2 shows a configuration example of the operational amplifier OP.
This is a well-known CMOS operational amplifier.
P-channel MOSFET (MP10 to MP11) and N
A current mirror type differential amplifier comprising channel type MOSFETs (MN10 to MN12);
OSFET (MP12) and N-channel MOSFET
(MN13). VR3 is supplied to the gate (inverting input terminal) of the N-channel MOSFET (MN10), and the gate (non-inverting input terminal) of the P-channel MOSFET (MN11).
Is supplied with a reference potential Vref. MOSFET
A constant bias voltage Vbias is supplied to the gates of (MN12 to MN13). Next, the operation of the charge pump circuit of this embodiment will be described. The operation of this charge pump circuit is based on the supply of electric charge from the power supply Vdd,
From the first stage MOSFET (MN1) to the last stage MOSFET
The charges move sequentially toward T (MN4). The point that the voltage is boosted so that the voltage becomes higher toward the node of the subsequent block is the same as in the conventional circuits shown in FIGS. 8 and 9. In this charge pump circuit, instead of using the output HV as it is, an operational amplifier O
Through P. Therefore, even if the output HV fluctuates, an extremely stable high voltage Vop can be obtained according to the setting of the reference potential Vref. Further, since the potentials VR1 to VR4 obtained by dividing the output of the operational amplifier OP by resistance are supplied as the substrate potentials of the corresponding MOSFETs (MN1 to MN4), the back gate bias voltage applied to each MOSFET is reduced. be able to. As a result, the ON resistance of each MOSFET is reduced, and a high output current Iout (10 mA) can be obtained. In the present invention, the back gate bias voltage can be individually reduced by applying a different substrate potential to each MOSFET. As an example, VR4 is supplied to the last-stage MOSFET (MN4), and the source (output HV) of the MOSFET (MN4) is 12V. in this case,
By setting the potential VR4 to, for example, 11 V, the back gate bias voltage Vbs can be reduced to 1 V. Also,
The variation ΔVt of the threshold voltage can be extremely reduced to 0.1 V or less. Thus, each MOSFET (M
By supplying the potentials VR1 to VR4 so that the substrate potentials of N1 to MN4) become substantially equal to the potential of the source thereof, the variation ΔV of the threshold voltage of each MOSFET is obtained.
t can be made very small. Actually, the source / drain potential of each MOSFET pulsates due to the operation of the charge pump, and the junction between the source substrates is forward-biased in consideration of the fluctuation of the potential, so that an excessive current does not occur. It is desirable to apply a potential in the range, that is, a potential slightly lower than the potential of the source. In this embodiment, a four-stage block (MOSFET (MN1 to MPN)
4) Although the capacitors C1 to C4) are used, the number of block stages may be appropriately increased or decreased in order to obtain a desired boosted potential. FIG. 3 is a cross-sectional view illustrating a structure when the charge pump circuit according to the first embodiment is formed on a P-type semiconductor substrate (Psub). This cross-sectional view shows an N-channel MO
SFETs (MN0 to MN4) and P-channel MOSFETs forming an inverter which is a part of the operational amplifier OP
(MP12) and N-channel MOSFET (MN13)
It is shown. The P-type semiconductor substrate (Psub) is connected to the ground potential. N-channel MOSFET (MN
0) is formed on the surface of the P-type semiconductor substrate (Psub). N-channel MOSFET (MN1-MN
4) is a first N-well region (N
W1) are formed in the first to fourth P-well regions (PW1 to PW4). First
P well region to fourth P well region (PW1 to PW
4) are electrically separated from each other, which makes it possible to supply different substrate potentials. The potentials VR1 to VR4 are supplied to the first to fourth P-well regions (PW1 to PW4), respectively. The output HV is supplied to the first N-well region (NW1). Instead of the output HV, the output V of the operational amplifier OP
op may be supplied. This is because the first N-well region (N
W1) and the first P-well region to the fourth P-well region (P
W1 to PW4) are prevented from being forward biased. On the other hand, in the operational amplifier OP, the P-channel MOSFET (MP12) is formed in the second well region (NW2). This second
The output HV is supplied to the well region (NW2). The N-channel MOSFET (MN13) is formed on the surface of a P-type semiconductor substrate (Psub). FIG.
FIG. 4 is a circuit diagram illustrating a charge pump circuit according to a second embodiment. This charge pump circuit has a ground potential (0 V)
This is a charge pump circuit that generates a lower voltage, that is, a negative voltage. The configuration of this charge pump circuit is the same as the charge pump circuit of the first embodiment except that the polarity is reversed. That is, N-channel MOSFET
Instead of P-channel MOSFETs (MP0 to MP
3) is used. These MOSFETs (MP1 to M
Although the gate and drain of P3) are connected, the direction of series connection is reversed in consideration of the direction of current flow. The source of the P-channel MOSFET (MP0) is connected to the ground potential (0V). Further, the reference potential Vref supplied to the operational amplifier OP is a negative potential. The substrate potential of each MOSFET (MP1 to MP3) includes a potential V obtained by dividing the output Vop of the operational amplifier OP by resistance.
R1 to VR3 are supplied. Here, VR3 <VR
2 <VR1 ≦ 0V. According to the operation of the charge pump circuit, the boosted potential becomes lower (negative potential) at the node of the MOSFET in the subsequent stage, so that the back gate bias voltage can be individually minimized by gradually lowering the substrate potential. I have to. According to this charge pump circuit, the high output current Iout flowing through the load resistor R2
(−6 mA) can be obtained. As the circuit configuration of the operational amplifier OP, a circuit similar to the circuit shown in FIG. 2 can be used. Note that a capacitor C6 (about 100 pF) may be added to further stabilize the output of the operational amplifier OP. In this embodiment, a three-stage block (MOS
Although the FETs (MP1 to MP3) and the capacitors C1 to C3) are used, the number of block stages may be appropriately increased or decreased in order to obtain a desired boosted potential. FIG. 5 is a cross-sectional view showing a structure when the charge pump circuit according to the second embodiment is formed on an N-type semiconductor substrate (Nsub). In this cross section,
A P-channel MOSFET (MP0 to MP3), a P-channel MOSFET (MP12) and an N-channel MOSFET which constitute an inverter which is a part of the operational amplifier OP.
ET (MN13) is shown. N-type semiconductor substrate (N
sub) is connected to the ground potential (0 V). P-channel MOSFETs (MP0 to MP3) are provided in a first P-well region (PW1) formed on the substrate surface.
0th N well region to 3rd N well region (NW0 to NW
W3). The 0th N-well region to the third N-well region are electrically separated from each other, so that different substrate potentials can be supplied. 0th N-well region to third P-well region (NW0
To NW3) are supplied with a potential of 0 V and VR1 to VR3, respectively. In the first P-well region (PW1),
The output HV (negative potential) is supplied. The output Vop of the operational amplifier OP may be supplied instead of the output HV. This prevents the PN junction formed by the first P-well region (PW1) and the 0th N-well region to the third N-well region (NW0 to NW3) from being forward biased.
On the other hand, in the operational amplifier OP, a P-channel type MOSF
The ET (MP12) is formed on the surface of an N-type semiconductor substrate (Nsub). N-channel MOSFET (MN1
3) is formed in the second P-well region (PW2). The output HV is supplied to the second P-well region (PW2).

[0009]

As described above, according to the charge pump circuit of the present invention, the boosted potential is output through the operational amplifier, so that the boosted potential can be stabilized. Further, the charge pump circuit of the present invention supplies a different substrate potential for each MOSFET performing a charge pump operation. In this method, a plurality of potentials are generated by dividing an output of an operational amplifier by resistance, and these potentials can be used as a substrate potential. As a result, the back gate bias voltage applied to each MOSFET can be reduced as compared with the related art. And the boost efficiency is greatly improved, and several mA
It is possible to obtain a high output current of up to several tens mA. Furthermore, according to the charge pump circuit of the present invention, since the back gate bias voltage applied to each MOSFET is reduced, the voltage applied to the PN junction formed between the source / drain and the substrate is also reduced. Therefore, unlike the conventional example, it is not necessary to use a MOSFET having a high withstand voltage capable of withstanding a high voltage of 7 V or more, for example.
Because it can use MOSFET that can withstand about voltage,
This can contribute to higher integration of the charge pump circuit and reduction in manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a charge pump circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an operational amplifier.

FIG. 3 is a cross-sectional view when the charge pump circuit according to the first embodiment of the present invention is formed on a semiconductor substrate.

FIG. 4 is a circuit diagram showing a charge pump circuit according to a second embodiment of the present invention.

FIG. 5 is a sectional view when a charge pump circuit according to a second embodiment of the present invention is formed on a semiconductor substrate.

FIG. 6 is a circuit diagram showing a first charge pump circuit according to a conventional example.

FIG. 7 is a circuit diagram showing a second charge pump circuit according to a conventional example.

[Explanation of symbols]

 MN0 to MN4 ... N-channel MOSFETs C1 to C4 ... Capacitance elements CK1, CK2 ... Clock OP ... Operational amplifier Vref ... Reference potential

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Shuichi Kikuchi 2-5-5 Keihanhondori, Moriguchi-shi, Osaka F-term in Sanyo Electric Co., Ltd. 5B025 AD10 5H410 BB04 CC02 DD02 EA11 EA12 EB16 EB37 FF03 FF25 HH00 KK08 5H430 BB03 BB06 BB09 BB11 EE06 FF02 FF13 GG01 HH03 HH05 5H730 AA14 AA15 BB02 BB57 DD04

Claims (5)

[Claims] A plurality of MOSFETs each having a gate and a drain connected to each other are connected in series, one end of a capacitive element is connected to a connection point between the gate and the drain of each MOSFET, and the other end of each capacitive element is connected to the opposite phase. Charge pump that alternately connects the first clock and the second clock to increase the voltage by sequentially moving charges through the respective MOSFETs to obtain a desired boosted potential from the source of the final-stage MOSFET. In the circuit, the boosted potential is supplied to the power supply potential of the operational amplifier, a reference potential is supplied to one input of the operational amplifier, the output of the operational amplifier is reduced to a predetermined potential, and the reduced potential is used as another potential of the operational amplifier. A charge pump circuit supplied to an input. 2. A MOSFET having m gates and drains connected to each other in series, one end of a capacitive element connected to a connection point between the gate and the drain of each MOSFET, and the other end connected to the other end of each capacitive element. A first clock and a second clock of a phase are connected alternately, and the voltage is boosted by sequentially moving charges through the respective MOSFETs to obtain a desired boosted potential from the source of the last-stage MOSFET. A charge pump circuit, wherein a different substrate potential is supplied to each MOSFET in the pump circuit. 3. A series connection of m MOSFETs having a gate and a drain connected to each other, one end of a capacitance element connected to a connection point between the gate and the drain of each MOSFET, and an opposite end connected to the other end of each capacitance element. A first clock and a second clock of a phase are connected alternately, and boosting is performed by sequentially moving charges from a first-stage MOSFET to a second-stage MOSFET. In a charge pump circuit for obtaining a boosted potential, this boosted potential is supplied to a power supply potential of an operational amplifier, a reference potential is supplied to one input of the operational amplifier, and m outputs obtained by dividing the output of the operational amplifier by resistance are stepped down. A potential is generated, one potential selected from the m potentials is supplied to another input of the operational amplifier, and further, the m potentials are corresponded. A charge pump circuit and supplying a substrate potential of each MOSFET. 4. The m MOSFETs are N-channel MOSFETs, and include a first stage MOSFET and a second stage MOSFET.
4. The charge pump circuit according to claim 2, wherein the m potentials are supplied such that the substrate potential supplied in the order of the OSFETs increases. 5. The m MOSFETs are P-channel MOSFETs, and include a first stage MOSFET and a second stage MOSFET.
4. The charge pump circuit according to claim 2, wherein the m potentials are supplied such that a substrate potential supplied in the order of the OSFETs becomes lower.