CN105958817B - A kind of charge pump - Google Patents
A kind of charge pump Download PDFInfo
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- CN105958817B CN105958817B CN201610409335.8A CN201610409335A CN105958817B CN 105958817 B CN105958817 B CN 105958817B CN 201610409335 A CN201610409335 A CN 201610409335A CN 105958817 B CN105958817 B CN 105958817B
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- charge pump
- input
- gate
- output terminal
- enable signal
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from dc input or output
Abstract
The embodiment of the invention discloses a kind of charge pump, the charge pump includes：Charge pump unit, works or stops under the control of clock signal and enable signal for each cycle, with output voltage；Voltage detection unit, for the enable signal in the output end voltage according to the charge pump unit and the fiducial value of target voltage values output next cycle to charge pump control unit；At least two charge pump control units, corresponded with least two charge pump circuits, for being high level in the enable signal in next cycle, when current period and the input clock signal in next cycle are same level, produce high level enable signal, otherwise low level enable signal is produced to the Enable Pin of corresponding charge pump circuit, and then control the work and stopping of charge pump circuit, realize control while start the quantity of the charge pump circuit of start-up operation, so as to achieve the purpose that to reduce output voltage fluctuation and input power noise.
Description
Technical field
The present embodiments relate to circuit engineering, more particularly to a kind of charge pump.
Background technology
Nonvolatile flash memory medium (nor Flash/nand Flash) is a kind of very common storage chip, has concurrently and deposits at random
Reservoir (Random Access Memory, RAM) and the advantages of read-only storage (Read-Only Memory, ROM), data are fallen
Electricity will not be lost, be it is a kind of can carry out the erasable memory of electricity in system, while its high integration and low cost make it
The market mainstream.
Flash chip is made of internal thousands of a storage units, and each storage element stores a data, is led to
Cross in the wordline of storage unit and apply corresponding voltage to complete the storage of data operation, the voltage is typically by charge pump
Circuit produces, and the voltage of charge pump circuit output can influence data usually with certain voltage fluctuation, the voltage fluctuation
Storage, moreover, with the diminution of Flash chip technology feature size, the capacitive load of output voltage also with becoming larger, in order to
Meet that the readout time of Flash chip is required, it is necessary to many charge pump circuit parallel operations, and then cause charge pump circuit to export
Voltage fluctuation bigger and unmanageable, while input power noise can also increase, and influence the storage performance of Flash chip.
A kind of charge pump construction schematic diagram of the prior art may refer to shown in Fig. 1, the charge pump include n parallel connection
Charge pump circuit and the charge pump circuit one-to-one signal processing circuit in parallel with the n, output voltage VO UT pass through
Resistance R3 and R4 carry out partial pressure, compared with reference voltage VREF, when output voltage is more than reference voltage, export high level
Enable signal PMPEN, otherwise export low level enable signal PMPEN.Enable signal PMPEN is used to control next cycle
Whether charge pump circuit work, and thus regulates and controls output voltage.For each charge pump circuit, whether current period works, and takes
Certainly in the enable signal PMPEN of current period, when the enable signal PMPEN of current period is high level, believe in input clock
Number CLKIN<n>Driving under charge pump circuit start to work；Work at the same time or do not work in order to avoid all charge pump circuits,
Each input clock signal CLKIN<n>There is certain phase difference, be illustrated in figure 2 four phase input clock signal schematic diagrames,
Each input clock signal CLKIN<n>About 1/8 clock cycle of front and rear difference.
If many charge pump circuits are controlled with above-mentioned four phase clock, although input clock signal CLKIN<n>Between
Delay can reduce the fluctuation of output voltage to a certain degree, but can not achieve the purpose that to reduce completely.Such as current week
After phase more several charge pump circuits are stopped, enable signal PMPEN is low level, the input of more several charge pump circuits
Clock signal clk IN<n>It is low level, driving clock signal clk D<n>Low level is parked in, then in next cycle charge pump electricity
When road works, during t0 to t1, the input clock signal CLKIN of more several charge pump circuits<n>For high level, if this
The enable signal PMPEN of the more several charge pump circuits of Shi Suoshu is changed into high level, then more several charge pumps being stopped
The driving clock signal clk D of circuit<n>It is changed into high level at the same time, more several charge pump circuits being stopped will at the same time
Start to work, so that larger voltage fluctuation is produced, as shown in figure 3, being that one and multiple charge pump circuits work at the same time generation
Voltage fluctuation difference schematic diagram, wherein, the first curve 310 represents the voltage fluctuation exported during a charge pump circuit functions,
Second curve 320 represents the voltage fluctuation exported when multiple charge pump circuits work at the same time.Similar, if current period is most
After charge pump circuit is stopped, enable signal PMPEN is low, the input clock signal of more several charge pump circuits
CLKIN<n>It is high level, driving clock signal clk D<n>High level is parked in, then in next cycle charge pump circuit functions
When, during t2 to t3, the input clock signal CLKIN of more several charge pump circuits<n>For low level, if described at this time
The enable signal PMPEN of more several charge pump circuits is changed into high level, then more several charge pump circuits being stopped
Drive clock signal clk D<n>It is changed into low level at the same time, more several charge pump circuits being stopped will start simultaneously at work
Make, equally produce larger voltage fluctuation.Usual each phase input clock signal CLKIN<n>Between delay by CMOS or
Resistance is formed, and may be changed with supply voltage, technique, temperature etc. and be changed so that the time between t0 to t1 or t2 to t3 becomes
Greatly, so that the probability for producing larger voltage fluctuation increases.
In summary, it is necessary to design a kind of circuit to reduce the fluctuation range of charge pump circuit output voltage, output is improved
The accuracy of voltage.
The content of the invention
The present invention provides a kind of charge pump, to reduce the fluctuation range of output voltage and input power noise.
The embodiment of the present invention provides a kind of charge pump, and the charge pump includes：
Charge pump unit, the charge pump unit include at least two charge pump circuits, and the charge pump circuit is mutually simultaneously
Connection connection, works or stops under the control of clock signal and enable signal for each cycle, with output voltage；
Voltage detection unit, the input terminal of the voltage detection unit are connected with the output terminal of the charge pump unit, use
The enable signal in next cycle is exported in the output end voltage according to the charge pump unit and the fiducial value of target voltage values to arrive
Charge pump control unit；
At least two charge pump control units, correspond with least two charge pump circuits, and each charge pump control is single
Output terminal of the first input end of member respectively with the voltage detection unit is connected, for obtaining the enable signal in next cycle,
Second input terminal is used for the driving clock signal for receiving current period, and the 3rd input terminal is connected with input clock source, is used for respectively
The input clock signal in next cycle is obtained, the enable signal that the charge pump control unit is used in next cycle is high electricity
It is flat, when the input clock signal in current period and next cycle is same level, high level enable signal is produced, is otherwise produced low
Level enable signal, the output terminal of the charge pump control unit is connected with the Enable Pin of charge pump circuit, enabled for exporting
Signal gives the charge pump circuit, wherein, there is phase delay between the input clock signal of each charge pump circuit.
Exemplarily, the voltage detection unit includes division module and enable signal output module, wherein, the partial pressure
Module is used to carry out partial pressure to the output end voltage of the charge pump unit；The enable signal output module is used for according to
The output end voltage of charge pump unit and the fiducial value output enable signal of target voltage values.
Preferably, the division module includes first resistor and second resistance, and the enable signal output module includes the
One comparator, wherein：
The first end of the first resistor is connected with the output terminal of the charge pump unit, second end and the second resistance
First end be connected, the second end of second resistance ground connection；The inverting input of the first comparator and the described first electricity
The second end of resistance is connected, and normal phase input end is connected with reference voltage, output terminal output enable signal.
Further, the charge pump further includes：
At least two signal processing units, with least two charge pump circuit and at least two charge pump control units
Correspond, the first input end of each signal processing unit is connected with the output terminal of charge pump control unit, under acquisition
The enable signal in one cycle, the second input terminal are connected with input clock source, for obtaining the input clock signal in next cycle, institute
Signal processing unit is stated to be used to produce the driving for driving next cycle charge pump circuit functions under the control of the enable signal
Clock signal and opposite phased driving clock signal, to drive charge pump circuit functions.
Preferably, the signal processing unit includes：4th phase inverter, the second nor gate, the 3rd nor gate, the 4th or non-
Door and the 3rd and door,
Wherein, the input terminal of the 4th phase inverter and the 3rd with the second input terminal of door respectively with charge pump control unit
Output terminal be connected, the output terminal of the 4th phase inverter is connected with the second input terminal of the second nor gate；The first of second nor gate
Input terminal and the 3rd is connected with input clock signal respectively with the second input terminal of door, the output terminal of the second nor gate and the 3rd or
The first input end of NOT gate is connected；Second input terminal of the 3rd nor gate is connected with the output terminal of four nor gate, output terminal with
The first input end of four nor gate is connected；Second input terminal of four nor gate is connected with the 3rd with the output terminal of door.
Preferably, the charge pump control unit includes：First phase inverter, the second phase inverter, first with door, second with
Door, the first nor gate, the first NAND gate, the second NAND gate and the 3rd phase inverter,
Wherein, the input terminal of first phase inverter and first with the second input terminal of door respectively with input clock signal phase
Even, the output terminal of the first phase inverter is connected with second with the first input end of door；The input terminal and first of second phase inverter
It is connected respectively with the driving clock signal of current period with the first input end of door, the output terminal of the second phase inverter and second and door
The second input terminal be connected；First is connected with the output terminal of door with the first input end of the first nor gate；Second with the output of door
End is connected with the second input terminal of the first nor gate；The output terminal of first nor gate and the second input terminal phase of the second NAND gate
Even；The first input end of second NAND gate is connected with the output terminal of the first NAND gate, and the second of output terminal and the first NAND gate is defeated
Enter end to be connected；The first input end of first NAND gate is connected with the output terminal of voltage detection unit, output terminal and the 3rd phase inverter
Input terminal be connected.
Further, the charge pump further includes input clock source, and the input clock source controls single with charge pump respectively
Member, signal processing unit are connected, for producing the input clock signal of setpoint frequency.
A kind of charge pump provided in an embodiment of the present invention, it is defeated by the driving clock signal of current period and next cycle
Enter clock signal and enable signal, determine the enable signal in next cycle jointly, avoid the occurrence of multiple charge pump circuits at the same time
The situation of work, realizes when multiple charge pump circuit parallel operations, and control starts the charge pump circuit of start-up operation at the same time
Quantity so that achieveed the purpose that reduce output voltage fluctuation and input power noise.
Brief description of the drawings
Fig. 1 is a kind of charge pump construction schematic diagram of the prior art；
Fig. 2 is four phase input clock signal schematic diagrames；
Fig. 3 is a charge pump circuit functions and when multiple charge pump circuits works at the same time, the contrast of output voltage fluctuation
Schematic diagram；
Fig. 4 is a kind of structure diagram for charge pump that the embodiment of the present invention one provides；
Fig. 5 is the structure diagram of voltage detection unit provided by Embodiment 2 of the present invention
Fig. 6 is a kind of circuit diagram of voltage detection unit provided by Embodiment 2 of the present invention；
Fig. 7 is a kind of circuit diagram for charge pump control unit that the embodiment of the present invention three provides；
Fig. 8 is each signal waveform schematic diagram that the embodiment of the present invention three provides；
Fig. 9 is the charge pump of the invention that the embodiment of the present invention three provides and existing charge pump under same loading condition
Input power noise and current simulations comparison of wave shape schematic diagram；
Figure 10 is a kind of structure diagram for charge pump that the embodiment of the present invention four provides；
Figure 11 is a kind of circuit diagram for signal processing unit that the embodiment of the present invention four provides.
Embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that in order to just
It illustrate only part related to the present invention rather than entire infrastructure in description, attached drawing.
Embodiment one
Fig. 4 is a kind of charge pump construction schematic diagram that the embodiment of the present invention one provides, and the present embodiment is suitable for multiple electric charges
The situation of pump circuit parallel operation.Referring specifically to as shown in figure 4, a kind of charge pump provided in this embodiment specifically includes：Electric charge
Pump unit 410,420 and at least two charge pump control unit 430 of voltage detection unit.
Charge pump unit 410, including at least two charge pump circuits 411, charge pump circuit 411 are connected in parallel with each other, and are used
In each cycle in clock signal clk IN<n>Work or stop under control with enable signal PMPEN-NEW, with output voltage；
The input terminal of voltage detection unit 420 is connected with the output terminal of charge pump unit 410, for according to charge pump unit
410 output end voltage VOUT and the fiducial value of target voltage values export the enable signal PMPEN in next cycle to charge pump control
Unit 430 processed；
At least two charge pump control units 430, correspond, each charge pump with least two charge pump circuits 411
Output terminal of the first input end of control unit 430 respectively with voltage detection unit 420 is connected, for obtaining making for next cycle
The enable signal for being used to control next cycle charge pump circuit of energy signal PMPEN, i.e. current period output, the second input terminal are used
In the driving clock signal clk D for receiving current period<n>, the 3rd input terminal is connected with input clock source respectively, under acquisition
The input clock signal CLKIN in one cycle<n>, charge pump control unit 430 is used for enable signal PMPEN in next cycle and is
High level, the driving clock signal clk D of current period<n>With the input clock signal CLKIN in next cycle<n>For identical electricity
Usually, high level enable signal PMPEN-NEW is produced, otherwise produces low level enable signal PMPEN-NEW, the enable signal
PMPEN-NEW actually enters the enable signal that charge pump circuit is controlled for next cycle.Charge pump control unit 430 it is defeated
Outlet is connected with the Enable Pin of charge pump circuit 411, for exporting enable signal PMPEN-NEW to charge pump circuit 411, its
In, the input clock signal CLKIN of each charge pump circuit<n>Between have phase delay.
Whether the first input end signal PMPEN of each charge pump control unit 430 is that high level depends on charge pump list
Whether the output end voltage VOUT of member 410 reaches target voltage values, if it is, first input end signal PMPEN is high level,
Otherwise first input end signal PMPEN is low level；Second input end signal CLKD<n>It is to depend on for high level or low level
In the working status of corresponding 411 current period of charge pump circuit of this charge pump control unit 430, if corresponding charge pump is electric
The working status of 411 current period of road is off work, then the second input end signal CLKD<n>It is otherwise high electricity for low level
It is flat；And the input clock signal CLKIN of the 3rd input terminal<n>To set the pulse signal in cycle.When first input end signal, i.e.,
When the enable signal PMPEN in next cycle is low level, corresponding charge pump control unit 430 exports low level enable signal
PMPEN-NEW gives corresponding charge pump circuit 411, then this charge pump circuit 411 of next cycle does not work；When first input end is believed
Number, i.e., when the enable signal PMPEN in next cycle is high level, and the second input terminal (driving clock signal of current period
CLKD<n>) and the 3rd input terminal (the input clock signal CLKIN in next cycle<n>) when being same level, corresponding charge pump
Control unit 430 exports high level enable signal PMPEN-NEW to corresponding charge pump circuit 411, then this electric charge of next cycle
Pump circuit 411 is started to work.
Thus, it is supposed that the more several charge pump circuits 411 of current period are stopped, corresponding enable signal PMPEN is low
Level, the input clock signal CLKIN of more several charge pump circuits 411<n>It is low level, then current period drives clock
Signal CLKD<n>Be parked in low level, then when next cycle charge pump circuit 411 works, during t0 to t1, the majority
The input clock signal CLKIN of a charge pump circuit 411<n>For high level, if more several charge pump circuits 411 described at this time
Enable signal PMPEN is changed into high level, but due to the driving clock signal of more several 411 current periods of charge pump circuit
CLKD<n>Low level is parked in, the input clock signal CLKIN with next cycle<n>It is not same level, so charge pump control
Unit 430 processed produces low level enable signal to more several charge pump circuits 411, more several is stopped so described
Charge pump circuit 411 will no longer start simultaneously at work, due to the input clock signal CLKIN of each charge pump circuit 411<n>Between
There is certain phase delay, so with each input clock signal CLKIN<n>It is changed into low level successively, corresponding each stopping work
The charge pump circuit 411 of work will start start-up operation successively, so as to reduce voltage fluctuation.
Same principle, it is assumed that current period majority charge pump circuit 411 is stopped, corresponding enable signal PMPEN
To be low, the input clock signal CLKIN of more several charge pump circuits 411<n>It is high level, then drives clock signal clk D
<n>Be parked in high level, then when next cycle charge pump circuit 411 works, during t2 to t3, more several charge pumps
The input clock signal CLKIN of circuit 411<n>For low level, if the enable signal of more several charge pump circuits 411 described at this time
PMPEN is changed into high level, but due to the driving clock signal clk D of more several 411 current periods of charge pump circuit<n>Stop
In high level, the input clock signal CLKIN with next cycle<n>It is not same level, so more several stopping works
The charge pump circuit 411 of work will no longer start simultaneously at work, so as to reduce voltage fluctuation.
A kind of charge pump provided in this embodiment, by increasing charge pump between voltage detection unit and charge pump circuit
Control unit, and output terminal of the first input end of the charge pump control unit respectively with the voltage detection unit is connected,
For obtaining the enable signal in next cycle, the second input terminal is used for the driving clock signal for receiving current period, the 3rd input
End is connected with input clock source respectively, and for obtaining the input clock signal in next cycle, the charge pump control unit is used for
It is high level in the enable signal in next cycle, the driving clock signal and the input clock signal in next cycle of current period are
During same level, high level enable signal is produced, otherwise produces low level enable signal to the Enable Pin of charge pump circuit, and then
The work and stopping of charge pump circuit are controlled, is realized when multiple charge pump circuit parallel operations, control starts start at the same time
The quantity of the charge pump circuit of work, so as to achieve the purpose that to reduce output voltage fluctuation and input power noise.
Embodiment two
Fig. 5 is the structure diagram of voltage detection unit provided by Embodiment 2 of the present invention, on the basis of above-described embodiment
On, voltage detection unit 420 is optimized in the present embodiment, shown in Figure 5, and voltage detection unit 420 includes：
Division module 421 and enable signal output module 422, wherein, division module 421 is used for charge pump unit 410
Output end voltage carry out partial pressure；Enable signal output module 422 is used for output end voltage and mesh according to charge pump unit 410
Mark the fiducial value output enable signal PMPEN of magnitude of voltage.
Preferably, a kind of implementation as voltage detection unit 420, shown in Figure 6, division module 421 includes：
First resistor R1 and second resistance R2, enable signal output module 422 include first comparator COMP1, wherein：
The first end of first resistor R1 is connected with the output terminal VOUT of charge pump unit 410, second end and second resistance R2
First end be connected, the second end of second resistance R2 ground connection；The inverting input of first comparator COMP1 is with first resistor R1's
Second end is connected, and normal phase input end is connected with reference voltage VREF, output terminal output enable signal PMPEN；
Wherein, the resistance value of first resistor R1 and second resistance R2 are chosen according to the output target voltage of charge pump unit 410.
The technical solution of the present embodiment, division module and enable signal output module are optimized for by voltage detection unit, its
In, division module is used to carry out the output end voltage of charge pump unit partial pressure, and enable signal output module is used for according to electric charge
The output end voltage of pump unit and the fiducial value of target voltage values export the enable signal in next cycle, so that charge pump control
Unit processed can produce the enable signal for controlling next cycle charge pump circuit functions according to the enable signal.
Embodiment three
Fig. 7 is a kind of circuit diagram for charge pump control unit that the embodiment of the present invention three provides, in the base of above-described embodiment
On plinth, charge pump control unit 430 is optimized in the present embodiment, each charge pump circuit 411 corresponds to an electric charge
Pump control unit 430.Referring specifically to shown in Fig. 7,
Charge pump control unit 430 specifically includes：First phase inverter T1, the second phase inverter T2, first and door Y1, second with
Door Y2, the first nor gate HF1, the first NAND gate YF1, the second NAND gate YF2 and the 3rd phase inverter T3.
Wherein, the input terminal of the first phase inverter T1 and first with the second input terminal of door Y1 respectively with input clock signal
CLKIN is connected, and the output terminal of the first phase inverter T1 is connected with second with the first input end of door Y2；The second phase inverter T2's
Input terminal and first is connected with the driving clock signal clk D of current period respectively with the first input end of door Y1, the second phase inverter
The output terminal of T2 is connected with second with the second input terminal of door Y2；First and the of the output terminal of door Y1 and the first nor gate HF1
One input terminal is connected；Second is connected with the output terminal of door Y2 with the second input terminal of the first nor gate HF1；First nor gate HF1
Output terminal be connected with the second input terminal of the second NAND gate YF2；The first input end and the first NAND gate of second NAND gate YF2
The output terminal of YF1 is connected, and output terminal is connected with the second input terminal of the first NAND gate YF1；The first input of first NAND gate YF1
End is connected with the output terminal PMPEN of voltage detection unit 420, and output terminal is connected with the input terminal of the 3rd phase inverter T3.
In order to illustrate the operation principle of charge pump control unit 430 provided in an embodiment of the present invention, each charge pump is set
The corresponding input clock signal CLKIN of circuit 411 differs 1/8 clock cycle successively, specifically may refer to four phases shown in Fig. 2
Position input clock signal schematic diagram.Circuit diagram shown in Figure 7, if the first input end PMPEN of the first NAND gate YF1 is
Low level, then the output terminal PMPEN-NEW of the 3rd phase inverter T3 is also low level；If the first input of the first NAND gate YF1
End PMPEN is high level, then in the first input end and the second phase inverter T2 of input clock signal CLKIN and first and door Y1
Input terminal CLKD when there is same level, the output terminal PMPEN-NEW of the 3rd phase inverter T3 is just high level.Each charge pump
The enable signal PMPEN-NEW in next cycle of circuit 411 is subject to the input clock signal CLKIN in the next cycle of oneself and works as
The driving influence of clock signal clk D-state in preceding cycle and it is different.The electricity in next cycle that charge pump control unit 430 exports
Lotus pump enable signal PMPEN-NEW waveform diagrams are shown in Figure 8, it is seen that next cycle of charge pump circuit 411 enables
Signal PMPEN-NEW is changed into high level, the enable signal PMPEN-NEW in next cycle of first charge pump circuit 411 successively<
1>To the enable signal PMPEN-NEW in next cycle of n-th of charge pump circuit 411<n>By each electricity at the time of being changed into high level
Delay between the corresponding input clock signal CLKIN of lotus pump circuit 411 determines, therefore, avoids multiple charge pump circuits 411
The problem of working at the same time, reduces input power noise and the output voltage fluctuation of charge pump unit 410.
The specific charge pump of the invention that may refer to shown in Fig. 9 and existing charge pump are defeated under same loading condition
Enter power supply noise simulation waveform contrast schematic diagram, wherein the 3rd curve 3 represents the input power of the charge pump unit 410 of the present invention
Noise, the 4th curve 4 represent the input power noise of charge pump unit 410 in the prior art, and the 5th curve 5 represents the present invention's
The source current of the input of charge pump unit 410, the 6th curve 6 represent the input power of charge pump unit 410 in the prior art
Electric current, it can be seen that pass through technical scheme, it will be apparent that reduce the input power noise of charge pump unit 410.
Above-mentioned charge pump control unit 430 realizes current period enable signal PMPEN when being low level, charge pump control
The output terminal PMPEN-NEW of unit 430 is low level, and corresponding 411 next cycle of charge pump circuit does not work；Work as current period
Enable signal PMPEN when being high level, and the driving clock of the input clock signal CLKIN in next cycle and current period is believed
When number CLKD is same level, the output terminal PMPEN-NEW of charge pump control unit 430 is high level, corresponding charge pump electricity
411 next cycle of road starts work.
A kind of circuit diagram of charge pump control unit provided in this embodiment, realizes when current period enable signal is low
During level, the output terminal of charge pump control unit is low level, and corresponding charge pump circuit next cycle does not work；When current week
When the enable signal of phase is high level, and the input clock signal in next cycle is identical with the driving clock signal of current period
During level, the output terminal of charge pump control unit is high level, and corresponding charge pump circuit next cycle starts work.
Example IV
Figure 10 is a kind of structure diagram for charge pump that the embodiment of the present invention four provides, on the basis of above-described embodiment
On, the present embodiment has carried out further optimization, and signal is added between charge pump control unit 430 and charge pump circuit 411
Processing unit 440, specifically may refer to shown in Figure 10, and the charge pump includes：
Charge pump unit 410, voltage detection unit 420, at least two charge pump control units 430 and at least two signals
Processing unit 440.
Charge pump unit 410, including at least two charge pump circuits 411, charge pump circuit 411 are connected in parallel with each other, and are used
In each cycle in clock signal clk IN<n>Work or stop under control with enable signal PMPEN-NEW, with output voltage；
The input terminal of voltage detection unit 420 is connected with the output terminal of charge pump unit 410, for according to charge pump unit
410 output end voltage VOUT and the fiducial value of target voltage values export the enable signal PMPEN in next cycle to charge pump control
Unit 430 processed；
At least two charge pump control units 430, correspond, each charge pump with least two charge pump circuits 411
Output terminal of the first input end of control unit 430 respectively with voltage detection unit 420 is connected, for obtaining making for next cycle
Can signal PMPEN, driving clock signal clk D of second input terminal for receiving current period<n>, the 3rd input terminal respectively with
Input clock source is connected, for obtaining the input clock signal CLKIN in next cycle<n>, charge pump control unit 430 be used for
The enable signal PMPEN in next cycle is high level, the driving clock signal clk D of current period<n>With the input in next cycle
Clock signal clk IN<n>For same level when, produce high level enable signal, otherwise produce low level enable signal, charge pump
The output terminal of control unit 430 is connected with the Enable Pin of charge pump circuit 411, for exporting enable signal PMPEN-NEW to electricity
Lotus pump circuit 411, wherein, the input clock signal CLKIN of each charge pump circuit<n>Between have phase delay.
At least two signal processing units 440 and at least two charge pump circuits 411 and the control of at least two charge pumps are single
Member 430 corresponds, and the first input end of each signal processing unit 440 is connected with the output terminal of charge pump control unit 430,
For obtaining the enable signal PMPEN-NEW in next cycle, the second input terminal is connected with input clock source, for obtaining next week
The input clock signal CLKIN of phase, signal processing unit 440 are used to produce driving under the control of enable signal PMPEN-NEW
The driving clock signal clk D and opposite phased driving clock signal CLKDB of next cycle charge pump circuit functions 411, to drive electric charge
Pump circuit 411 works.
Preferably, a kind of implementation as signal processing unit 440, shown in Figure 11, signal processing unit 440
Including：4th phase inverter T4, the second nor gate HF2, the 3rd nor gate HF3, four nor gate HF4 and the 3rd and door Y3,
Wherein, the input terminal of the 4th phase inverter T4 and the 3rd with the first input end of door Y3 respectively with charge pump control unit
430 output terminal PMPEN_NEW is connected, and the output terminal of the 4th phase inverter T4 is connected with the second input terminal of the second nor gate HF2；
The first input end of second nor gate HF2 and the 3rd is connected with input clock signal CLKIN respectively with the second input terminal of door Y3,
The output terminal of second nor gate HF2 is connected with the first input end of the 3rd nor gate HF3；The second input of 3rd nor gate HF3
End is connected with the output terminal of four nor gate HF4, and output terminal is connected with the first input end of four nor gate HF4；4th or non-
The second input terminal of door HF4 is connected with the 3rd with the output terminal of door Y3.
When the first input end signal PMPEN-NEW of the input terminal of the 4th phase inverter T4 and the 3rd and door Y3 is high level
When, the driving clock signal clk D and input clock signal CLKIN of the next work of cycle charge pump circuit 411 of driving of generation are same
Step change；When the first input end signal PMPEN-NEW of the input terminal of the 4th phase inverter T4 and the 3rd and door Y3 is low level,
The driving clock signal clk D for driving next cycle charge pump circuit 411 to work is not produced, input clock signal CLKIN is cut
Only.
On the basis of the various embodiments described above, the charge pump further includes input clock source, the input clock source point
It is not connected with charge pump control unit 430, signal processing unit 440, for producing the input clock signal of setpoint frequency
CLKIN。
Note that it above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious changes,
Readjust and substitute without departing from protection scope of the present invention.Therefore, although being carried out by above example to the present invention
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
It can include other more equivalent embodiments, and the scope of the present invention is determined by scope of the appended claims.
Claims (7)
- A kind of 1. charge pump, it is characterised in that including：Charge pump unit, the charge pump unit include at least two charge pump circuits, the charge pump circuit company parallel with one another Connect, work or stop under the control of clock signal and enable signal for each cycle, with output voltage；Voltage detection unit, the input terminal of the voltage detection unit is connected with the output terminal of the charge pump unit, for root The enable signal in next cycle is exported to electric charge according to the output end voltage of the charge pump unit and the fiducial value of target voltage values Pump control unit；At least two charge pump control units, correspond with least two charge pump circuits, each charge pump control unit Output terminal of the first input end respectively with the voltage detection unit is connected, for obtaining the enable signal in next cycle, second Input terminal is used for the driving clock signal for receiving current period, and the 3rd input terminal is connected with input clock source respectively, for obtaining The input clock signal in next cycle, the enable signal that the charge pump control unit is used in next cycle is high level, when When the driving clock signal and the input clock signal in next cycle in preceding cycle are same level, high level enable signal is produced, Otherwise low level enable signal is produced, the output terminal of the charge pump control unit is connected with the Enable Pin of charge pump circuit, uses In exporting enable signal to the charge pump circuit, wherein, there is phase delay between the input clock signal of each charge pump circuit.
- 2. charge pump according to claim 1, it is characterised in that the voltage detection unit includes division module and enables Signal output module, wherein, the division module is used to carry out partial pressure to the output end voltage of the charge pump unit；It is described to make Energy signal output module is used to be exported according to the output end voltage of the charge pump unit and the fiducial value of target voltage values enabled Signal.
- 3. charge pump according to claim 2, it is characterised in that the division module includes first resistor and the second electricity Resistance, the enable signal output module include first comparator, wherein：The first end of the first resistor is connected with the output terminal of the charge pump unit, and the of second end and the second resistance One end is connected, the second end ground connection of the second resistance；The inverting input of the first comparator and the first resistor Second end is connected, and normal phase input end is connected with reference voltage, output terminal output enable signal.
- 4. the charge pump according to claim 1 or 3, it is characterised in that the charge pump control unit includes：First is anti-phase Device, the second phase inverter, first and door, second and door, the first nor gate, the first NAND gate, the second NAND gate and the 3rd phase inverter,Wherein, the input terminal of first phase inverter and first is connected with input clock signal respectively with the second input terminal of door, The output terminal of first phase inverter is connected with second with the first input end of door；The input terminal and first and door of second phase inverter First input end be connected respectively with the driving clock signal of current period, the output terminal of the second phase inverter and second and the of door Two input terminals are connected；First is connected with the output terminal of door with the first input end of the first nor gate；Second with the output terminal of door with Second input terminal of the first nor gate is connected；The output terminal of first nor gate is connected with the second input terminal of the second NAND gate；The The first input end of two NAND gates is connected with the output terminal of the first NAND gate, the output terminal of the second NAND gate and the first NAND gate Second input terminal is connected；The first input end of first NAND gate is connected with the output terminal of voltage detection unit, the first NAND gate Output terminal is connected with the input terminal of the 3rd phase inverter.
- 5. charge pump according to claim 1, it is characterised in that further include：At least two signal processing units, with least two charge pump circuit and at least two charge pump control units one by one Corresponding, the first input end of each signal processing unit is connected with the output terminal of charge pump control unit, for obtaining next week The enable signal of phase, the second input terminal are connected with input clock source, for obtaining the input clock signal in next cycle, the letter Number processing unit is used to produce the driving clock for driving next cycle charge pump circuit functions under the control of the enable signal Signal and opposite phased driving clock signal, to drive charge pump circuit functions.
- 6. charge pump according to claim 5, it is characterised in that the signal processing unit includes：4th phase inverter, Two nor gates, the 3rd nor gate, four nor gate and the 3rd and door,Wherein, the input terminal of the 4th phase inverter and the 3rd defeated with charge pump control unit respectively with the second input terminal of door Outlet is connected, and the output terminal of the 4th phase inverter is connected with the second input terminal of the second nor gate；First input of the second nor gate End and the 3rd is connected with input clock signal respectively with the second input terminal of door, the output terminal of the second nor gate and the 3rd nor gate First input end be connected；Second input terminal of the 3rd nor gate is connected with the output terminal of four nor gate, the 3rd nor gate Output terminal is connected with the first input end of four nor gate；Second input terminal of four nor gate and the 3rd and the output terminal phase of door Even.
- 7. charge pump according to claim 5, it is characterised in that further include input clock source, the input clock source point It is not connected with charge pump control unit, signal processing unit, for producing the input clock signal of setpoint frequency.
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| CN201610409335.8A CN105958817B (en) | 2016-06-12 | 2016-06-12 | A kind of charge pump |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109756106B (en) * | 2018-12-27 | 2021-07-23 | 西安紫光国芯半导体有限公司 | Method and circuit for reducing noise of charge pump system |
| CN111404372B (en) * | 2020-05-08 | 2023-08-22 | Oppo广东移动通信有限公司 | Charge pump circuit, chip and terminal |
| CN111817553B (en) * | 2020-07-01 | 2021-12-24 | 浙江驰拓科技有限公司 | On-chip charge pump circuit |
| CN112165250B (en) * | 2020-10-12 | 2022-04-05 | 唯捷创芯(天津)电子技术股份有限公司 | Charge pump circuit, chip and communication terminal |
| CN113346739B (en) * | 2021-05-28 | 2022-09-09 | 长江存储科技有限责任公司 | Charge pump circuit system, three-dimensional memory and three-dimensional memory system |
| CN113824316B (en) * | 2021-10-26 | 2023-11-03 | 上海交通大学 | Comprehensive charge pump circuit based on digital inverter |
| CN114167936B (en) * | 2021-12-03 | 2022-11-22 | 中国科学院半导体研究所 | CMOS charge pump pumping device with wide working voltage range |
| CN114915164A (en) * | 2022-04-07 | 2022-08-16 | 北京中电华大电子设计有限责任公司 | Circuit and method for smoothly controlling starting power consumption of charge pump |
| CN115940631B (en) * | 2023-01-10 | 2023-11-17 | 中茵微电子(南京)有限公司 | Low ripple charge pump circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105634268A (en) * | 2016-01-15 | 2016-06-01 | 西安紫光国芯半导体有限公司 | Charge pump power supply with low ripple voltage |
| CN206060529U (en) * | 2016-06-12 | 2017-03-29 | 北京兆易创新科技股份有限公司 | A kind of charge pump |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105634268A (en) * | 2016-01-15 | 2016-06-01 | 西安紫光国芯半导体有限公司 | Charge pump power supply with low ripple voltage |
| CN206060529U (en) * | 2016-06-12 | 2017-03-29 | 北京兆易创新科技股份有限公司 | A kind of charge pump |
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