CN112462247A - Method and circuit for measuring EEPROM erasing voltage of smart card chip - Google Patents
Method and circuit for measuring EEPROM erasing voltage of smart card chip Download PDFInfo
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- CN112462247A CN112462247A CN202011264810.XA CN202011264810A CN112462247A CN 112462247 A CN112462247 A CN 112462247A CN 202011264810 A CN202011264810 A CN 202011264810A CN 112462247 A CN112462247 A CN 112462247A
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- 238000005070 sampling Methods 0.000 claims abstract description 24
- 101150042711 adc2 gene Proteins 0.000 claims description 21
- 101100434411 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) ADH1 gene Proteins 0.000 claims description 20
- 101150102866 adc1 gene Proteins 0.000 claims description 20
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 101710096660 Probable acetoacetate decarboxylase 2 Proteins 0.000 claims description 4
- 230000002238 attenuated effect Effects 0.000 claims description 4
- 101710096655 Probable acetoacetate decarboxylase 1 Proteins 0.000 claims 2
- 238000012360 testing method Methods 0.000 abstract description 18
- 238000012216 screening Methods 0.000 abstract description 3
- 238000005259 measurement Methods 0.000 description 4
- 108091022873 acetoacetate decarboxylase Proteins 0.000 description 2
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31907—Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31703—Comparison aspects, e.g. signature analysis, comparators
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31724—Test controller, e.g. BIST state machine
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
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- Physics & Mathematics (AREA)
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- Computer Hardware Design (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a method and a circuit for measuring EEPROM erasing voltage of a smart card chip, which are particularly suitable for accurately measuring the EEPROM erasing voltage of the smart card chip on test equipment of the smart card chip. The invention obtains the accurate EEPROM erasing voltage by sampling the output current of the EEPROM erasing voltage, calculating the corresponding internal loss voltage through the current and then compensating the internal loss voltage to the output voltage of the acquired EEPROM erasing voltage. The measuring circuit does not need to use a power supply higher than the EEPROM erasing voltage, reduces the influence of the measuring circuit on the EEPROM erasing voltage output, improves the measuring accuracy of the EEPROM erasing voltage and reduces the misjudgment caused by the measuring deviation. The test equipment for the intelligent card chip is particularly used for judging whether the EEPROM erasing voltage reaches the compliant range in the EEPROM screening test of the intelligent card chip.
Description
Technical Field
The invention relates to a method and a circuit for measuring EEPROM erasing voltage of a smart card chip, which are particularly suitable for accurately measuring the erasing voltage of the smart card chip during erasing of the EEPROM on the smart card test equipment, and relate to the field of smart card test equipment.
Background
In the production test of the intelligent card chip, after the wafer is processed, unqualified die is distinguished by testing, wherein one is the screening test of EEPROM erasing and writing voltage, namely, the erasing and writing voltage generated by boosting the inside of the intelligent card chip during erasing and writing the EEPROM is output to a VPPH end, and the EEPROM screening test is carried out by measuring the output voltage of the VPPH end to judge whether the EEPROM erasing and writing voltage is in a qualified range. Because the EEPROM erase voltage is usually higher than the operating voltage of the smart card and the operating voltage of devices such as a controller and an ADC in the smart card test equipment, the current common method is to divide the output voltage of the VPPH terminal, input the divided voltage to the ADC for conversion, and then calculate the voltage value of the VPPH terminal by the controller to be used as the EEPROM erase voltage value. The problem with this approach is that the VPPH terminal generates an internal voltage drop once the current is output, and the output current and the internal voltage drop are nonlinear. And if the resistance value of the resistor using voltage division is not large enough, the current flowing through the voltage division resistor can cause the non-contact smart card chip to generate an internal voltage drop of tens of millivolts to hundreds of millivolts, so that the output voltage value of the VPPH end is low, the measured value is lower than the actual internal boosted voltage value, erroneous judgment is caused, and the test result is influenced. If a large-resistance resistor of dozens of mega ohms to hundreds of mega ohms is used for voltage division, the large-resistance resistor can introduce strong noise, and the test result and consistency are seriously influenced.
Disclosure of Invention
The invention designs a method and a circuit for measuring the EEPROM erasing voltage of a smart card chip on a smart card chip test device, which realize accurate measurement of the EEPROM erasing voltage of the smart card chip by compensating the internal voltage drop caused by the output current of a VPPH end caused by the test circuit, improve the measurement consistency and reduce the misjudgment rate.
The invention is mainly realized by the following technical scheme:
firstly, a relation table of a voltage drop value (compensation voltage value) and a current value generated by outputting the erasing voltage of the EEPROM of the smart card core to a VPPH end is stored in an internal memory or an external memory of a controller.
Secondly, after the output voltage of the VPPH end is driven by a voltage division and following circuit, the output voltage is input to an analog-to-digital converter ADC2, the ADC2 converts the acquired voltage value into a digital signal and outputs the digital signal to a controller, and the voltage value of the VPPH end is calculated according to the voltage value.
Meanwhile, the current output by the VPPH terminal is sampled and amplified by using a current sampling and amplifying circuit, the amplified analog signal is converted into a digital signal by using an analog-to-digital converter ADC1 and is output to the controller, and the controller calculates the current value output by the VPPH terminal according to the digital signal.
And finally, the controller obtains the current value output by the VPPH end through the digital signal of the analog-to-digital converter ADC1, searches the corresponding compensation voltage value according to the relation table of the current value and the internal voltage drop value, and adds the compensation voltage value and the voltage value of the VPPH end to obtain the accurate internal boosting voltage value.
In the whole scheme, the controller detects the output current of the VPPH end, converts the output current into a compensation voltage value, and then adds the compensation voltage value with the VPPH voltage value obtained through voltage division and conversion calculation of the following circuit, so that the accuracy of EEPROM erasing and writing voltage measurement is improved, a large-resistance resistor is not needed, noise interference is reduced, the accuracy and consistency of measurement are improved, and the misjudgment rate is reduced.
In summary, the hardware part of the scheme mainly comprises a controller, a current sampling and amplifying circuit, an analog-to-digital converter ADC1, a voltage dividing and following circuit and an analog-to-digital converter ADC2, wherein the controller sends a test command to the smart card chip to enable the smart card chip to perform erasing and writing operations of the EEPROM; the current sampling and amplifying circuit and the ADC1 are used for obtaining the magnitude of the VPPH output current and then searching a corresponding compensation voltage value; the voltage division and following circuit and the ADC2 are used for calculating the voltage value of the VPPH end, and the controller adds the two voltage values to obtain the accurate erasing voltage value of the EEPROM.
The method for measuring the erasing voltage of the EEPROM of the smart card chip by the circuit structure mainly comprises the following steps:
step one, outputting the EEPROM erasing voltage of the smart card chip to a VPPH end to generate a relation table of a voltage drop value and a current value, and storing the relation table into a MEMORY of a controller;
step two, when the controller sends a command to the smart card chip to test the EEPROM erasing voltage, the smart card chip starts to erase and write the EEPROM, and simultaneously outputs the EEPROM erasing voltage to the VPPH end, and the VPPH end outputs a voltage value obtained by dividing the voltage output by the VPPH end through the voltage dividing and following circuit and then acquires the voltage value obtained by dividing the voltage output by the VPPH end through the analog-to-digital converter ADC 2;
and step three, after the output of the VPPH end passes through the current sampling and amplifying circuit, the controller collects current data through the analog-to-digital converter ADC1 to calculate and search a corresponding compensation voltage value.
And step four, the controller acquires the voltage value through the analog-to-digital converter ADC2, obtains the voltage value of the VPPH end through proportional operation, and performs addition operation on the calculated voltage value of the VPPH end and the compensation voltage value to obtain an accurate internal boosting voltage value.
Drawings
The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
fig. 1 is a schematic diagram of the connection of the controller, the current sampling and amplifying circuit, the analog-to-digital converter ADC1, the voltage dividing and following circuit, and the analog-to-digital converter ADC 2;
fig. 2 is a circuit architecture of the voltage division and follower circuit and the analog-to-digital converter ADC 2;
FIG. 3 is a circuit architecture of the current sampling and amplifying circuit and the ADC1
Detailed Description
The invention is described in detail with reference to fig. 1, 2 and 3.
As shown in fig. 1, the circuit of the present invention includes a voltage dividing and following circuit, a current sampling and amplifying circuit, an analog-to-digital converter ADC1, an analog-to-digital converter ADC2 and a controller, wherein the voltage dividing and following circuit is connected to the analog-to-digital converter ADC2, generates a digital signal of a proportional attenuation value of a VPPH output voltage, and is connected to the controller to calculate the VPPH output voltage; the current sampling and amplifying circuit is connected with the analog-to-digital converter ADC1, generates a digital signal of voltage corresponding to the current output by VPPH, and is connected to the controller for calculating the output current of VPPH.
The voltage division and following circuit shown in fig. 2 is composed of a resistor voltage division and a follower, wherein a voltage signal output by VPPH is connected with the resistor voltage division, the resistor voltage division outputs a VPPH attenuated voltage signal, the attenuated voltage signal follower is connected with an analog-to-digital converter ADC2 after being driven by the follower, and a corresponding digital signal is generated by the analog-to-digital converter ADC2 and sent to the controller.
The current sampling and amplifying circuit shown in fig. 3 is composed of a current sampling resistor and an instrumentation amplifier, wherein a current signal output by VPPH is connected to the current sampling resistor after passing through a resistor voltage-dividing circuit, the current sampling resistor converts the current signal output by VPPH into a voltage signal, the voltage signal is connected to the input end of the instrumentation amplifier, after the signal is amplified, the instrumentation amplifier outputs the voltage signal to an analog-to-digital converter ADC1, and the ADC1 generates a digital signal corresponding to the voltage signal and sends the digital signal to the controller.
One specific implementation for measuring the erase-write voltage of the smart card chip EEPROM based on the circuit structure of the invention is as follows.
The method comprises the following steps: the controller sends an EEPROM erasing voltage test instruction to the smart card chip through a 7816 channel or a 13.56MHz RF channel, the smart card chip starts to erase and write the EEPROM after receiving the instruction, at the moment, a boosting circuit inside the smart card chip works, and the boosted EEPROM erasing voltage is output to a VPPH end of the chip;
step two: because EEPROM erasing voltage is high, the internal resistance is large, drive weak, so VPPH end output voltage is changed into a suitable voltage to output to ADC2 through resistance voltage division first, then drive by following circuit that JFET amplifier forms and input to ADC2, ADC2 changes the voltage signal that the following circuit outputs into the digital signal and outputs to the controller, the voltage value that the controller samples ADC2 multiplies the proportion of voltage division to calculate and obtains the voltage value that VPPH end outputs;
step three: the current output by the VPPH end flows through the current sampling resistor after passing through the resistor voltage division part, a voltage is generated on the current sampling resistor, the voltage is amplified by the instrument amplifier and then output to the ADC1, the ADC1 converts an amplified analog voltage signal into a digital signal and outputs the digital signal to the controller, and the controller performs proportional operation on the digital signal to obtain an output current value of the VPPH end;
step four: the controller calculates a compensation voltage value by searching a relation table of a voltage drop value and a current value generated when the EEPROM erasing voltage in the memory is output to the VPPH end, then adds the compensation voltage value and the measured VPPH end output voltage value to obtain a voltage value of the EEPROM erasing voltage, compares the voltage value with a voltage range specified by a test, and judges whether the EEPROM erasing voltage value is in compliance or not.
The present invention has been described in detail with reference to the specific embodiments, which are not intended to limit the present invention, and various changes and modifications may be made without departing from the principle of the present invention, and these should be construed as falling within the scope of the present invention.
Claims (7)
1. A method for measuring the erasing voltage of an EEPROM (electrically erasable programmable read-Only memory) of a smart card chip is characterized by comprising the following steps of:
step 1) firstly, when a controller sends an erasing and writing command of an EEPROM, a high voltage for erasing the EEPROM is generated inside a smart card chip and is output to a VPPH end, the output of the VPPH end is measured by a voltage division and following circuit, and meanwhile, the output current of the VPPH end is measured by a current sampling and amplifying circuit;
step 2) dividing the voltage of the signal entering the voltage dividing and following circuit, converting the divided voltage into a proper level, driving the level by a follower, outputting the level to an analog-to-digital converter ADC2 for analog-to-digital conversion, sending the converted digital signal to a controller by the analog-to-digital converter ADC2, and calculating the voltage value output by VPPH by the controller;
step 3) simultaneously converting the current output by the VPPH end into voltage by the current sampling and amplifying circuit, amplifying the voltage into a proper voltage value, outputting the voltage value to the analog-to-digital converter ADC1 for analog-to-digital conversion, and sending the converted digital signal to the controller by the analog-to-digital converter ADC 1;
and 4) calculating the digital signal output by the analog-to-digital converter ADC1 by the controller to obtain a current value output by the VPPH end, obtaining a voltage drop value generated inside the corresponding smart card chip, and then adding the voltage drop value and the voltage value output by the VPPH to obtain an accurate voltage value of the internal high voltage.
2. The method of claim 1, wherein said step 2): the voltage output by the VPPH is divided into an input voltage signal which can be accepted by the analog-to-digital converter ADC2 by using the resistor voltage division, and the input voltage signal is driven by the follower to be input to the analog-to-digital converter ADC2 for analog-to-digital conversion, and is converted into a digital value corresponding to the voltage signal.
3. The method of claim 1, wherein said step 3): the current signal is sensed using a sampling resistor and the sampled signal is amplified using an instrumentation amplifier to an input voltage signal acceptable to the analog-to-digital converter ADC 1.
4. The method of claim 1, wherein said step 4): the controller program stores a corresponding table of the relation between the VPPH output current and the voltage drop generated in the smart card chip in a memory, when the controller acquires the current value output by the VPPH end through the analog-to-digital converter ADC1, the corresponding internal voltage drop is found through the corresponding table, and the internal voltage drop value is added with the voltage value acquired on the analog-to-digital converter ADC2 to obtain the accurate voltage value of the EEPROM erasing voltage.
5. A circuit for measuring EEPROM erasing voltage of a smart card chip is used for realizing the method of claim 1, and is characterized by comprising a voltage division and following circuit, a current sampling and amplifying circuit, an analog-to-digital converter ADC1, an analog-to-digital converter ADC2 and a controller, wherein the voltage division and following circuit is connected with the analog-to-digital converter ADC2, generates a digital signal of a proportional attenuation value of VPPH output voltage and is connected to the controller for calculating the VPPH output voltage; the current sampling and amplifying circuit is connected with the analog-to-digital converter ADC1, generates a digital signal of voltage corresponding to the current output by VPPH, and is connected to the controller for calculating the output current of VPPH.
6. The circuit of claim 5, wherein the voltage divider and follower circuit comprises a resistor divider and a follower, wherein the voltage signal output by the VPPH is connected to the resistor divider, the resistor divider outputs a VPPH attenuated voltage signal, and the attenuated voltage signal follower is connected to the ADC2, and is driven by the follower to generate a corresponding digital signal to the controller via the ADC 2.
7. The circuit of claim 5, wherein the current sampling and amplifying circuit comprises a current sampling resistor and an instrumentation amplifier, wherein a current signal output by the VPPH is connected to the current sampling resistor after passing through the resistor voltage dividing circuit, the current sampling resistor converts the current signal output by the VPPH into a voltage signal, the voltage signal is connected to an input end of the instrumentation amplifier, the instrumentation amplifier outputs the voltage signal to the analog-to-digital converter ADC1 after the signal is amplified, and the analog-to-digital converter ADC1 generates a digital signal corresponding to the voltage signal and sends the digital signal to the controller.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011264810.XA CN112462247A (en) | 2020-11-13 | 2020-11-13 | Method and circuit for measuring EEPROM erasing voltage of smart card chip |
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| CN202011264810.XA CN112462247A (en) | 2020-11-13 | 2020-11-13 | Method and circuit for measuring EEPROM erasing voltage of smart card chip |
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| CN202011264810.XA Pending CN112462247A (en) | 2020-11-13 | 2020-11-13 | Method and circuit for measuring EEPROM erasing voltage of smart card chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113514758A (en) * | 2021-09-15 | 2021-10-19 | 绅克半导体科技(苏州)有限公司 | Chip testing method, tester and storage medium |
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Application publication date: 20210309 |