CN212514879U - Operational amplifier test system - Google Patents
Operational amplifier test system Download PDFInfo
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- CN212514879U CN212514879U CN202020237334.1U CN202020237334U CN212514879U CN 212514879 U CN212514879 U CN 212514879U CN 202020237334 U CN202020237334 U CN 202020237334U CN 212514879 U CN212514879 U CN 212514879U
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Abstract
The utility model relates to a test system is put to fortune. The operational amplifier testing system comprises an operational amplifier to be tested, an auxiliary testing loop, a first capacitance sampling circuit, a second capacitance sampling circuit and a calculating circuit. The auxiliary test loop is used for sampling and recording the time coordinate of a sampling point and the output voltage of the operational amplifier to be tested in the test stage; the first capacitance sampling circuit is used for receiving the low-level voltage signal and the common-mode voltage signal and providing the low-level voltage signal and the common-mode voltage signal to the inverting input end of the operational amplifier to be tested; the first input end of a second capacitance sampling circuit of the second capacitance sampling circuit is grounded, and the second capacitance sampling circuit is used for receiving a low-level voltage signal and a common-mode voltage signal and supplying the low-level voltage signal and the common-mode voltage signal to the non-inverting input end of the operational amplifier to be tested; the computing circuit is used for receiving the output voltage of the operational amplifier to be tested and computing the bias current of the operational amplifier to be tested according to the time coordinates of the plurality of sampling points and the output voltage of the operational amplifier to be tested.
Description
Technical Field
The utility model relates to a semiconductor integrated circuit tests technical field, especially relates to a test system is put to fortune.
Background
With the continuous development of semiconductor technology, the performance of operational amplifiers is gradually improved as electronic components with wide application. Nowadays, the application of high-precision operational amplifiers with offset voltages as low as several uV levels or bias currents as low as several pA levels is becoming more and more common. There is therefore a greater demand for the accuracy and precision of operational amplifier testing.
At present, the testing of the operational amplifier bias current is generally completed based on a common resistance sampling method, and the voltage drop on the sampling resistor is calculated by measuring the change of the output voltage of the auxiliary operational amplifier, so that the current flowing through the sampling resistor is calculated. The method can obtain better test results when testing the bias current of most operational amplifier products. For the test of the pA-level bias current operational amplifier device, in order to make the voltage drop on the sampling resistor easier to be measured, a larger sampling resistor (about several mega ohms) is often required to be selected, but an overlarge sampling resistor is introduced at the input end of the tested operational amplifier, so that the whole test loop is more easily affected by noise, and the final test result is inaccurate.
SUMMERY OF THE UTILITY MODEL
Therefore, it is necessary to provide an operational amplifier test system for solving the problem that the current operational amplifier test system cannot accurately measure the pA-level bias current.
The utility model provides a test system is put to fortune, include:
an operational amplifier to be tested;
the first input end of the first capacitance sampling circuit is grounded, the second input end of the first capacitance sampling circuit is electrically connected with the inverting input end of the operational amplifier to be tested, and the output end of the first capacitance sampling circuit is electrically connected with the inverting input end of the operational amplifier to be tested, is used for receiving a low-level voltage signal and a common-mode voltage signal and provides the low-level voltage signal and the common-mode voltage signal to the inverting input end of the operational amplifier to be tested;
the first input end of the second capacitance sampling circuit is grounded, the second input end of the second capacitance sampling circuit is electrically connected with the non-inverting input end of the operational amplifier to be tested, and the output end of the second capacitance sampling circuit is electrically connected with the non-inverting input end of the operational amplifier to be tested, is used for receiving the low-level voltage signal and the common-mode voltage signal and provides the low-level voltage signal and the common-mode voltage signal to the non-inverting input end of the operational amplifier to be tested;
the auxiliary test loop is electrically connected with the operational amplifier to be tested and used for sampling and recording the time coordinate of a sampling point and the output voltage of the operational amplifier to be tested after a preset delay time in a test stage when a sampling capacitor in the first capacitor sampling unit is connected to the non-inverting input end of the operational amplifier to be tested or when a sampling capacitor in the second capacitor sampling unit is connected to the inverting input end of the operational amplifier to be tested; and
and the computing circuit is electrically connected with the auxiliary test loop and used for receiving the output voltage of the operational amplifier to be tested and computing the bias current of the operational amplifier to be tested according to the time coordinates of the plurality of sampling points and the output voltage of the operational amplifier to be tested.
In one embodiment, the auxiliary test loop is further configured to, before the test, periodically detect an output voltage of the operational amplifier to be tested after a sampling capacitor in the first capacitor sampling unit is connected to a non-inverting input terminal of the operational amplifier to be tested, or after a sampling capacitor in the second capacitor sampling unit is connected to an inverting input terminal of the operational amplifier to be tested, and continue for a preset time;
the calculation circuit is further configured to determine the preset delay time according to the output voltages of the operational amplifiers to be tested detected within the preset time.
In one embodiment, the calculation circuit configured to determine the preset delay time according to the output voltages of the operational amplifiers to be tested detected within the preset time is specifically configured to:
calculating the termination time t from the slopeeAnd a starting time tsRespectively corresponding to the output voltages of the operational amplifiers to be tested, calculating teTime and tsSlope G of the output voltage between moments0Wherein, ts＝te- Δ t, Δ t being the period of detecting the output voltage of the operational amplifier under test;
let te＝te-Δt，ts＝tsΔ t, according to teTime at and tsCalculating t according to the output voltage of the operational amplifier to be tested corresponding to the time delta teTime at and tsSlope G of the output voltage between instants Δ tt；
Judgment GtAnd G0Whether the absolute value of the difference value of (a) is greater than the maximum allowable error E of the slope;
if yes, calculating the termination time t according to the slopeeDetermining the preset delay time tdelay＝te+2Δt+toffsetWherein t isoffsetAn additional delay for setting;
otherwise, let E be G0-Gt，G0＝Gt，te＝te-Δt，ts＝tsΔ t, according to teTime at and tsCalculating t according to the output voltage of the operational amplifier to be tested corresponding to the time delta teTime at and tsSlope G of the output voltage between instants Δ ttAnd returning to judgment GtAnd G0Is greater than the maximum allowable slope error E.
In one embodiment, the first capacitance sampling circuit includes:
the first end of the first resistor is grounded, and the second end of the first resistor is electrically connected with the output end of the auxiliary test loop;
a first end of the first sampling capacitor is electrically connected with a second end of the first resistor and the output end of the auxiliary test loop, and a second end of the first sampling capacitor is electrically connected with the inverting input end of the operational amplifier to be tested; and
and the first switch is connected in parallel with two ends of the first sampling capacitor.
In one embodiment, the first capacitance sampling circuit includes:
the first end of the second resistor is electrically connected with the first end of the first resistor, and the second end of the second resistor is grounded through a feedback resistor;
a first end of the second sampling capacitor is electrically connected with a second end of the second resistor, and a second end of the second sampling capacitor is electrically connected with a non-inverting input end of the operational amplifier to be tested; and
and the second switch is connected in parallel with two ends of the second sampling capacitor.
In one embodiment, the auxiliary test loop comprises:
the auxiliary operational amplifier is characterized in that a third resistor and a third switch are sequentially connected in series between the non-inverting input end of the auxiliary operational amplifier and the output end of the operational amplifier to be tested, the inverting input end of the auxiliary operational amplifier is grounded, and the output end of the auxiliary operational amplifier is electrically connected with the second end of the first resistor and the first end of the first sampling capacitor through another feedback resistor;
and the input end of the VI source is electrically connected with the output end of the auxiliary operational amplifier, and the output end of the VI source is electrically connected with the input end of the computing circuit, and is used for periodically sampling and recording sampling time and output voltage of a sampling point and supplying the output voltage to the computing circuit.
In one embodiment, the output voltage of the sampling point is equal to the average value of the output voltages in four power frequency periods on two sides of the sampling point.
In one embodiment, the switches are all electronic relays.
In one embodiment, the set additional delay toffsetIs 10-2～10-3s。
In one embodiment, a feedback resistor is connected between the output terminal of the auxiliary test loop and the first capacitance sampling circuit.
To sum up, the embodiment of the utility model provides a test system is put to fortune. The operational amplifier testing system comprises an operational amplifier to be tested, an auxiliary testing loop, a first capacitance sampling circuit, a second capacitance sampling circuit and a calculating circuit. The auxiliary test loop is electrically connected with the operational amplifier to be tested and used for accessing the sampling capacitor in the first capacitor sampling unit to the non-inverting input end of the operational amplifier to be tested or sampling in the second capacitor sampling unit in the test stageThe method comprises the steps that a capacitor is connected to the inverting input end of an operational amplifier to be tested, and after a preset delay time, the time coordinate of a sampling point and the output voltage of the operational amplifier to be tested are sampled and recorded; the first capacitor sampling circuit is grounded at a first input end of the first capacitor sampling circuit, a second input end of the first capacitor sampling circuit is electrically connected with an inverting input end of the operational amplifier to be tested, and an output end of the first capacitor sampling circuit is electrically connected with the inverting input end of the operational amplifier to be tested, is used for receiving a low-level voltage signal and a common-mode voltage signal and provides the low-level voltage signal and the common-mode voltage signal to the inverting input end of the operational amplifier to be tested; the first input end of the second capacitance sampling circuit is grounded, the second input end of the second capacitance sampling circuit is electrically connected with the non-inverting input end of the operational amplifier to be tested, and the output end of the second capacitance sampling circuit is electrically connected with the non-inverting input end of the operational amplifier to be tested, is used for receiving the low-level voltage signal and the common-mode voltage signal and provides the low-level voltage signal and the common-mode voltage signal to the non-inverting input end of the operational amplifier to be tested; and the computing circuit is electrically connected with the auxiliary test loop and used for receiving the output voltage of the operational amplifier to be tested and computing the bias current of the operational amplifier to be tested according to the time coordinates of the plurality of sampling points and the output voltage of the operational amplifier to be tested. It can be understood that after the sampling capacitor is connected to the input terminal of the operational amplifier to be tested, the bias current of the operational amplifier to be tested will continuously charge the sampling capacitor according to the formula
And calculating the slope of the voltage change of the sampling capacitor to obtain the magnitude of the bias current. The voltage change at the two ends of the capacitor can be measured through the voltage Vm at the output end of the auxiliary test loop, and the voltage change at the two ends of the sampling capacitor is obtained by dividing the Vm change by the gain of the auxiliary operational amplifier loop, so that the problem that the operational amplifier circuit is influenced by noise due to the introduction of an overlarge sampling resistor is solved, and the test accuracy of the bias current is improved.
Drawings
Fig. 1 is a schematic structural diagram of an operational amplifier testing system according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an exemplary operational amplifier test circuit using a sampling resistor to test bias current;
fig. 3 is a schematic diagram of a programming interface provided by the present invention;
fig. 4 is a waveform of the measured output voltage of the amplifier to be measured after adding a certain delay according to the present invention;
fig. 5 is a test waveform of the LMC6001 bias current provided by the present invention;
fig. 6 is a test waveform of the bias current of OP37G provided by the present invention;
fig. 7 is a schematic diagram of an output voltage sampling method according to an embodiment of the present invention;
fig. 8 is a schematic flow chart of an operational amplifier testing method according to an embodiment of the present invention;
fig. 9 is a schematic flow chart of another operational amplifier testing method according to an embodiment of the present invention.
Detailed Description
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention can be embodied in many different forms other than those specifically described herein, and it will be apparent to those skilled in the art that similar modifications can be made without departing from the spirit and scope of the invention, and it is therefore not to be limited to the specific embodiments disclosed below.
Referring to fig. 1, an embodiment of the present invention provides an operational amplifier test system, which includes an operational amplifier DUT to be tested, an auxiliary test loop 100, a first capacitance sampling circuit 200, a second capacitance sampling circuit 300, and a computing circuit 400.
The auxiliary test loop 100 is electrically connected to the operational amplifier to be tested DUT, and is configured to, in a test phase, sample and record a time coordinate of a sampling point and an output voltage of the operational amplifier to be tested DUT after a preset delay time when a sampling capacitor in the first capacitor sampling unit 200 is connected to a non-inverting input terminal of the operational amplifier to be tested DUT, or when a sampling capacitor in the second capacitor sampling unit 300 is connected to an inverting input terminal of the operational amplifier to be tested DUT.
The first input end of the first capacitance sampling circuit 200 is grounded, the second input end of the first capacitance sampling circuit 200 is electrically connected with the inverting input end of the operational amplifier under test DUT, and the output end of the first capacitance sampling circuit 200 is electrically connected with the inverting input end of the operational amplifier under test DUT, and is configured to receive the low-level voltage signal and the common-mode voltage signal and provide the low-level voltage signal and the common-mode voltage signal to the inverting input end of the operational amplifier under test DUT.
The first input terminal of the second capacitance sampling circuit 300 is grounded, the second input terminal of the second capacitance sampling circuit 300 is electrically connected to the non-inverting input terminal of the operational amplifier under test DUT, and the output terminal of the second capacitance sampling circuit 300 is electrically connected to the non-inverting input terminal of the operational amplifier under test DUT, and is configured to receive the low-level voltage signal and the common-mode voltage signal and provide the low-level voltage signal and the common-mode voltage signal to the non-inverting input terminal of the operational amplifier under test DUT.
The computing circuit 400 is electrically connected to the auxiliary test loop 100, and is configured to receive the output voltage of the operational amplifier DUT to be tested, and compute the bias current of the operational amplifier DUT to be tested according to the time coordinates of the plurality of sampling points and the output voltage of the operational amplifier DUT to be tested.
It will be appreciated that the bias current of the operational amplifier comprises a positive input bias current (Ib +) and a negative input bias current (Ib-). The positive input bias current (Ib +) is the current flowing into (or out of) the non-inverting terminal of the device when the output voltage of the device under test is zero (or a predetermined value) under a predetermined power supply voltage. The negative input bias current (Ib-) is the current that flows into (or out of) the inverting terminal of the device when the device under test output voltage is zero (or a predetermined value) at a predetermined power supply voltage. Bias current (Ib): when the output voltage of the device to be tested is zero (or a specified value) under a specified power supply voltage, the average current flowing into (or flowing out of) two input ends of the device. Input offset current (Ios): when the output voltage of the device to be tested is zero (or a predetermined value) under a predetermined power supply voltage, the difference between the currents flowing into (or out of) the two input ends of the device.
Testing the bias current parameters of the op-amp amplifier requires the assistance of an auxiliary op-amp loop. Currently, the testing of the offset current of the operational amplifier is generally completed based on a common resistance sampling method, please refer to fig. 2. The testing steps comprise: (1) the device power supply terminals apply a predetermined power supply voltage V +, V-via FPVI1 and FPVI 0. (2) The device under test output voltage VO is set to a predetermined value by setting the reference voltage VREF. (3) And closing switches K1 and K2, and testing the output voltage Vm0 at the output end of the auxiliary operational amplifier. (4) The switch K1 is turned off and the output voltage Vm1 is tested at the output of the auxiliary operational amplifier. (5) The in-phase terminal input bias current Ib + (Vm1-Vm0) × RI/(RF × R). (6) And closing the switch K1, opening the switch K2 and testing the output voltage Vm2 at the output end of the auxiliary operational amplifier. (7) The reverse-phase terminal receives a bias current Ib — (Vm2-Vm0) × RI/(RF × R). (8) The input bias current Ib is (Ib + + Ib-)/2. (9) The offset current is input, and is Ib + -Ib-. Therefore, the voltage drop on the IB sampling resistor is calculated by measuring the change of the output voltage of the auxiliary operational amplifier, and the IB current flowing through the IB sampling resistor is further calculated. The method can obtain better test results when testing the bias current of most operational amplifier devices. However, for the test of the pA-level bias current operational amplifier device, in order to make the voltage drop across the IB sampling resistor easier to be measured, a larger IB sampling resistor (several M ohms) is often required to be selected, and an excessively large IB sampling resistor is introduced at the input end of the operational amplifier to be measured, so that the whole test loop is more easily affected by noise, and the final test result is unstable.
In this embodiment, the sampling resistor is replaced by a sampling capacitor, so that the problem of noise interference can be solved. And when the sampling capacitor is connected to the input end of the operational amplifier DUT to be tested, the bias current of the operational amplifier to be tested continuously charges the sampling capacitor according to the formula
And calculating the slope of the voltage change of the sampling capacitor to obtain the magnitude of the bias current. The voltage of the two ends of the capacitor can be changed by an auxiliary circuitAnd when the output end Vm of the auxiliary operational amplifier is measured, the change of Vm is divided by the gain of the auxiliary operational amplifier loop, namely the change of the voltage at two ends of the IB sampling capacitor.
After the sampling resistor is replaced by the sampling capacitor, a good clock is needed so that the relay can be opened at the sampling point and the output voltage of the operational amplifier DUT to be measured can be measured according to the requirement. Therefore, the utility model provides a test system is put to fortune supports menu programming and the open C language programming two kinds of modes of fill-in table formula, and hardware system adopts the modularized design, can match and expand according to the demand. The system has the advantages of high test precision, rich parameters, stable performance, good adaptability, self-contained software oscilloscope function and convenient device programming development and use operation. The testing process can be accomplished through menu programming, and the programming interface is shown in fig. 3. FIG. 4 is a voltage waveform at Vm measured after a certain delay is added, which is displayed by a software oscilloscope of the STS8200 system, and the magnitude of the bias current of the operational amplifier to be measured can be calculated through the slope of the voltage waveform.
In one embodiment, the auxiliary test loop 100 is further configured to, before the test, periodically detect an output voltage of the operational amplifier under test DUT for a preset time period after the sampling capacitor in the first capacitor sampling unit 200 is connected to the non-inverting input terminal of the operational amplifier under test, or after the sampling capacitor in the second capacitor sampling unit 300 is connected to the inverting input terminal of the operational amplifier under test;
the calculating circuit 400 is further configured to determine the preset delay time according to the detection of the output voltages of the plurality of operational amplifiers under test DUT within the preset time.
It can be understood that, when the loop is powered on and the loop state is switched, the test of the pA-level bias current may be affected by the fact that the loop state is not stable or the leakage of the charge caused by the switching moment of some relays. If the voltage slope is calculated without a measurement delay, the tested pA-class bias current will produce a very large error. It is therefore necessary to add sufficient measurement delay during the test. Therefore, the utility model discloses confirm to predetermine delay time before the test, be favorable to improving pA level bias current's measuring accuracy.
Referring to fig. 5, fig. 5 shows waveforms of the entire process of testing the LMC6001 (with a bias current less than 25fA) by using the operational amplifier testing system of the present invention. Two waveforms are shown in fig. 5, the upper waveform being the positive supply voltage of the device under test and the lower waveform being the output voltage (Vm) of the auxiliary op-amp. It can be seen that the following waveform is clearly divided into two parts, which represent the test procedure for positive and negative input bias currents, respectively. It can be seen that the slope of the Vm waveform is large both on power-up of the test and when the test positive input switches to a negative input. However, after a certain time, the slope of the waveform becomes very slow, and the slope of the waveform reflects the magnitude of the bias current of the device under test. When the loop is electrified and the loop state is switched, the testing of the pA-level bias current can be influenced by the fact that the loop state is not stable or the leakage of charges brought by the switching moments of some relays. If the voltage slope is calculated without a measurement delay, the tested pA-class bias current will produce a very large error. It is therefore necessary to add sufficient measurement delay during the test.
Referring to fig. 6, fig. 6 shows a test waveform of the bias current of OP37G (typical bias current value is 12 nA). The bias current of the OP37G is in the order of tens of nA, and is very large compared with the pA-level operational amplifier, and better test results can be obtained by applying a common sampling resistor mode. Here a waveform measured by means of a sampled capacitance. It can be seen that the slope of the waveform is very good, and there is a large difference in slope at the moment of power-up and switching, because the bias current of OP37G is large, and the influence of the charge change caused by power-up and switching is much smaller than the bias current of OP37G, and is almost negligible. While LMC6001 has a bias current of only within 25fA, these effects are not negligible. This is also the reason why the IB test of the high-precision op-amp requires longer test delay.
In one embodiment, the calculation circuit 400 configured to determine the preset delay time according to the detection of the output voltages of the plurality of operational amplifiers under test DUT within the preset time is specifically configured to:
calculating the termination time t from the slopeeAnd a starting time tsRespectively corresponding to the output voltages of the operational amplifiers to be tested DUT, calculating teTime and tsSlope G of the output voltage between moments0Wherein, ts＝te- Δ t, Δ t being the period of detecting the output voltage of said operational amplifier under test DUT;
let te＝te-Δt，ts＝tsΔ t, according to teTime at and ts-the output voltages of the operational amplifiers DUT to be tested respectively corresponding to the moments of- Δ t, calculating teTime at and tsSlope G of the output voltage between instants Δ tt；
Judgment GtAnd G0Whether the absolute value of the difference value of (a) is greater than the maximum allowable error E of the slope;
if yes, calculating the termination time t according to the slopeeDetermining the preset delay time tdelay＝te+2Δt+toffsetWherein t isoffsetAn additional delay for setting;
otherwise, let E be G0-Gt，G0＝GT，te＝te-Δt，ts＝tsΔ t, according to teTime at and ts-the output voltages of the operational amplifiers DUT to be tested respectively corresponding to the moments of- Δ t, calculating teTime at and tsSlope G of the output voltage between instants Δ ttAnd returning to judgment GtAnd G0Is greater than the maximum allowable slope error E.
Because the testing of the pA-level bias current needs to add longer measurement delay, the measurement delay needed by different models of tested operational amplifiers is different. If the delay time is determined by observing the waveform of the oscilloscope each time, the method is not beneficial to being applied to the automatic test of the bias current parameters of the operational amplifier. The method for automatically determining the measurement delay comprises the following steps of applying a measurement delay with enough length in the first test, and recording all voltage values and corresponding time coordinates measured by the output end of the auxiliary operational amplifier in the delay process. In the measured data, the slope of the measured waveform is calculated every short time (Δ t) by gradually decreasing from the last measured data. Then comparing with the slope of the adjacent waveform segment, if the difference value exceeds the maximum allowable error E of the set slope, the moment is considered as the delay time.
In addition, in order to increase a certain test margin and ensure that the loop is in a stable state when entering the test process, a small amount of extra delay t can be added according to the requirement on the basis of the delay timeoffset. In general, the additional delay toffsetValues on the order of 10 ms. In one embodiment, the set additional delay toffsetIs 10-2～10-3s
When the batch test of the operational amplifier products is carried out, the test delay is a preset larger measurement delay when the first tested device is tested. And then determining the stable time of the tested device by scanning a mode of comparing the slope section by section according to the test result. The settling time is then used as the delay time for the next device under test in the same batch. Thus, the automatic determination of the delay time can be completed only by increasing the test time of the first device under test. For the test of the devices of a whole batch, the trouble of manually judging the measurement delay can be saved by only increasing the almost negligible test time, so that the method is better applied to the automatic test.
In one embodiment, the first capacitance sampling circuit 200 includes a first resistor R1, a first sampling capacitor C1, and a first switch K1.
A first terminal of the first resistor R1 is connected to ground, and a second terminal of the first resistor R1 is electrically connected to an output terminal of the auxiliary test loop 100.
A first terminal of the first sampling capacitor C1 is electrically connected to a second terminal of the first resistor R1 and an output terminal of the auxiliary test loop 100, and a second terminal of the first sampling capacitor C1 is electrically connected to an inverting input terminal of the operational amplifier under test DUT.
The first switch K1 is connected in parallel across the first sampling capacitor C1.
In one embodiment, the first capacitance sampling circuit 200 includes a second resistor R2, a second sampling capacitor C2, and a second switch K2:
the first end of the second resistor R2 is electrically connected with the first end of the first resistor R1, and the second end of the second resistor R2 passes through a feedback resistor RFAnd (4) grounding.
The first end of the second sampling capacitor C2 is electrically connected with the second end of the second resistor R2, and the second end of the second sampling capacitor C2 is electrically connected with the non-inverting input end of the operational amplifier under test DUT.
The second switch K2 is connected in parallel across the second sampling capacitor C2.
In one embodiment, the auxiliary test loop 100 includes auxiliary operational amplifier AMP and VI sources.
A third resistor R3 and a third switch K3 are sequentially connected in series between the non-inverting input end of the auxiliary operational amplifier AMP and the output end of the operational amplifier DUT to be tested, the inverting input end of the auxiliary operational amplifier AMP is grounded, and the output end of the auxiliary operational amplifier AMP passes through the other feedback resistor RFIs electrically connected with the second end of the first resistor R1 and the first end of the first sampling capacitor C1.
The input end of the VI source is electrically connected to the output end of the auxiliary operational amplifier AMP, and the output end of the VI source is electrically connected to the input end of the computing circuit 400, and is used for periodically sampling and recording sampling time and output voltage of a sampling point, and providing the output voltage to the computing circuit 400.
In this embodiment, the testing step includes: (1) and a power supply end of the device applies specified power supply voltage V +, V-through the FPVI1 and the FPVI0 to provide a common-mode voltage signal for the operational amplifier to be tested. (2) And closing the first switch K1, opening the second switch K2, periodically sampling and recording the sampling time and the output voltage of the sampling point at the output end of the auxiliary operational amplifier, supplying the sampling time and the output voltage to the calculation circuit 400, and calculating the positive input bias current. (3) And opening the first switch K1, closing the second switch K2, periodically sampling and recording the sampling time and the output voltage of the sampling point at the output end of the auxiliary operational amplifier, supplying the sampling time and the output voltage to the calculating circuit 400, and calculating the negative input bias current.
It can also be seen from fig. 4 that a sine wave with a small amplitude is superimposed on the voltage ramp wave, which is a power frequency disturbance of 50 Hz. Because the final test result is only related to the slope, the interference of the power frequency does not have great influence on the test result. In order to further improve the test accuracy, in one embodiment, the VI source for periodically sampling and recording the time coordinate of the sampling point and the output voltage of the operational amplifier under test DUT is specifically configured to:
determining the sampling point according to the sampling frequency;
sampling voltages of four power frequency periods positioned at two sides of the sampling point, and taking the average value of the voltages as the output voltage of the operational amplifier to be tested DUT corresponding to the sampling point;
and recording the time coordinate of the sampling point and the output voltage of the operational amplifier DUT to be tested.
Referring to fig. 7, the voltages in the 4 power frequency cycles are sampled near the point to be measured, and the average value is the voltage value of the midpoint in the selected 4 power frequency cycles. The voltage of 2 sampling points is obtained by the method, and then the voltage is divided by the time difference, so that the slope of the voltage waveform among the 2 sampling points can be calculated.
In one embodiment, the switches are all electronic relays.
Referring to fig. 8, based on the operational amplifier testing system in any of the above embodiments, the embodiment of the present invention further provides an operational amplifier testing method, including:
step S810, electrifying the operational amplifier test system;
step S820, in the testing stage, when the sampling capacitor in the first capacitor sampling unit 200 is connected to the non-inverting input terminal of the operational amplifier DUT to be tested, or when the sampling capacitor in the second capacitor sampling unit 300 is connected to the inverting input terminal of the operational amplifier DUT to be tested, and after a preset delay time, sampling and recording the time coordinate of the sampling point and the output voltage of the operational amplifier DUT to be tested;
and step S830, calculating the bias current of the operational amplifier DUT to be tested according to the time coordinates of the plurality of sampling points and the output voltage of the operational amplifier DUT to be tested.
In one embodiment, the operational amplifier testing method further includes:
before testing, when a sampling capacitor in a first capacitor sampling unit is connected to the non-inverting input end of an operational amplifier to be tested, or when a sampling capacitor in a second capacitor sampling unit is connected to the inverting input end of the operational amplifier to be tested, periodically detecting the output voltage of the operational amplifier to be tested DUT, and continuing for a preset time;
and determining the preset delay time according to the output voltages of the operational amplifiers to be tested DUT detected in the preset time.
In one embodiment, the determining the preset delay time according to the detection of the output voltages of the plurality of operational amplifiers under test DUT within the preset time includes:
calculating the termination time t from the slopeeAnd a starting time tsRespectively corresponding to the output voltages of the operational amplifiers to be tested DUT, calculating teTime and tsSlope G of the output voltage between moments0Wherein, ts＝te- Δ t, Δ t being the period of detecting the output voltage of said operational amplifier under test DUT;
let te＝te-Δt，ts＝tsΔ t, according to teTime at and ts-the output voltages of the operational amplifiers DUT to be tested respectively corresponding to the moments of- Δ t, calculating teTime at and tsSlope G of the output voltage between instants Δ tt；
Judgment GtAnd G0Whether the absolute value of the difference value of (a) is greater than the maximum allowable error E of the slope;
if yes, calculating the termination time t according to the slopeeDetermining the preset delay time tdelay＝te+2Δt+toffsetWherein t isoffsetAn additional delay for setting;
otherwise, let E be G0-Gt，G0＝Gt，te＝te-Δt，ts＝tsΔ t, according to teTime at and ts-the output voltages of the operational amplifiers DUT to be tested respectively corresponding to the moments of- Δ t, calculating teTime at and tsSlope G of the output voltage between instants Δ ttAnd returning to judgment GtAnd G0Is greater than the maximum allowable slope error E.
In one embodiment, the operational amplifier testing method further includes:
detecting the output voltage of a plurality of operational amplifiers (DUTs) to be tested in the preset time, and setting the initial preset delay time t before determining the preset delay timedelay＝0；
Judging the preset delay time tdelayWhether or not it is 0;
if yes, let tdelay＝TmaxAnd when the sampling capacitor in the first capacitor sampling unit is connected to the non-inverting input end of the operational amplifier to be tested, or when the sampling capacitor in the second capacitor sampling unit is connected to the inverting input end of the operational amplifier to be tested, periodically detecting the output voltage of the operational amplifier to be tested DUT, wherein TmaxPresetting a delay time for the longest allowable time;
otherwise, entering a testing stage.
Referring to fig. 9, fig. 9 shows the whole testing process, and the specific testing process includes:
powering on the operational amplifier test system, and starting the test;
setting the initial value of the preset delay time to be 0 and the allowed maximum preset delay time to be Tmax；
Judging whether the currently set preset delay time is 0 or not;
and if not, entering a test stage, and sampling and recording the time coordinate of the sampling point and the output voltage of the operational amplifier to be tested DUT (device under test) after the sampling capacitor in the first capacitor sampling unit is accessed to the non-inverting input end of the operational amplifier to be tested, or after the sampling capacitor in the second capacitor sampling unit is accessed to the inverting input end of the operational amplifier to be tested.
If the preset delay time currently set is 0, let tdelay＝TmaxAnd after the input of the operational amplifier DUT to be tested is switched from positive input to negative input or from negative input to positive input, periodically detecting the output voltage of the operational amplifier DUT to be tested;
let te＝Tmax，ts＝TmaxΔ t, calculating the termination time t from the slopeeAnd a starting time tsRespectively corresponding to the output voltages of the operational amplifiers to be tested DUT, calculating teTime and tsSlope G of the output voltage between moments0；
Let te＝te-Δt，ts＝tsΔ t, according to teTime at and ts-the output voltages of the operational amplifiers DUT to be tested respectively corresponding to the moments of- Δ t, calculating teTime at and tsSlope G of the output voltage between instants Δ tt；
Judgment GtAnd G0Whether the absolute value of the difference value of (a) is greater than the maximum allowable error E of the slope;
if yes, calculating the termination time t according to the slopeeDetermining the preset delay time tdelay＝te+2Δt+toffsetAnd returning to the step of judging whether the currently set preset delay time is 0 or not, wherein toffsetAn additional delay for setting;
otherwise, let E be G0-Gt，G0＝Gt，te＝te-Δt，ts＝tsΔ t, according to teTime at and ts-the output voltages of the operational amplifiers DUT to be tested respectively corresponding to the moments of- Δ t, calculating teTime at and tsSlope G of the output voltage between instants Δ ttAnd is combined withReturn to judgment GtAnd G0Is greater than the maximum allowable slope error E.
When the batch test of the operational amplifier is carried out, the test delay is a preset larger measurement delay when the first tested device is tested. And then determining the stable time of the tested device by scanning a mode of comparing the slope section by section according to the test result. The settling time is then used as the delay time for the next device under test in the same batch. Thus, the automatic determination of the delay time can be completed only by increasing the test time of the first device under test. For the test of the devices of a whole batch, the trouble of manually judging the measurement delay can be saved by only increasing the almost negligible test time, so that the method is better applied to the automatic test.
In order to verify the accuracy of the test, when the bias current of the tested operational amplifier is in a dozen nA level, a more accurate test result can be obtained by using a sampling resistor method, and data measured by a sampling capacitor method at the moment can be compared with test data of the sampling resistor method to roughly verify the accuracy of the test result. Further, a constant current source circuit of 1nA is fabricated and applied to an input terminal of an operational amplifier having a bias current of several tens of fA levels, which is equivalent to an operational amplifier having a bias current of 1 nA. The equivalent operational amplifier is tested by using a sampling capacitor method, and the test result is compared with 1nA to further verify the test precision. Because the pA-level constant current source circuit is difficult to manufacture, the verification of the IB sampling capacitor method for testing the accuracy of the pA-level bias current is difficult to realize through the mode. The method can be combined with the typical value in the parameter manual of the tested device to be compared with the test result, and simultaneously, whether the output voltage waveform of the auxiliary operational amplifier is an oblique line with good linearity is observed, so that the reliability of the pA-level bias current test result is deduced.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (10)
1. An operational amplifier test system, comprising:
an operational amplifier to be tested;
the first input end of the first capacitance sampling circuit is grounded, the second input end of the first capacitance sampling circuit is electrically connected with the inverting input end of the operational amplifier to be tested, and the output end of the first capacitance sampling circuit is electrically connected with the inverting input end of the operational amplifier to be tested, is used for receiving a low-level voltage signal and a common-mode voltage signal and provides the low-level voltage signal and the common-mode voltage signal to the inverting input end of the operational amplifier to be tested;
the first input end of the second capacitance sampling circuit is grounded, the second input end of the second capacitance sampling circuit is electrically connected with the non-inverting input end of the operational amplifier to be tested, and the output end of the second capacitance sampling circuit is electrically connected with the non-inverting input end of the operational amplifier to be tested, is used for receiving the low-level voltage signal and the common-mode voltage signal and provides the low-level voltage signal and the common-mode voltage signal to the non-inverting input end of the operational amplifier to be tested;
the auxiliary test loop is electrically connected with the operational amplifier to be tested and used for sampling and recording the time coordinate of a sampling point and the output voltage of the operational amplifier to be tested after a preset delay time in a test stage when a sampling capacitor in the first capacitor sampling unit is connected to the non-inverting input end of the operational amplifier to be tested or when a sampling capacitor in the second capacitor sampling unit is connected to the inverting input end of the operational amplifier to be tested; and
and the computing circuit is electrically connected with the auxiliary test loop and used for receiving the output voltage of the operational amplifier to be tested and computing the bias current of the operational amplifier to be tested according to the time coordinates of the plurality of sampling points and the output voltage of the operational amplifier to be tested.
2. The operational amplifier test system of claim 1,
the auxiliary test loop is also used for periodically detecting the output voltage of the operational amplifier to be tested before testing when the sampling capacitor in the first capacitor sampling unit is connected to the non-inverting input end of the operational amplifier to be tested, or after the sampling capacitor in the second capacitor sampling unit is connected to the inverting input end of the operational amplifier to be tested, and continuously prolonging the preset time;
the calculation circuit is further configured to determine the preset delay time according to the output voltages of the operational amplifiers to be tested detected within the preset time.
3. The operational amplifier test system as claimed in claim 2, wherein the computing circuit for determining the preset delay time according to the detection of the output voltages of the operational amplifiers to be tested within the preset time is specifically configured to:
calculating the termination time t from the slopeeAnd a starting time tsRespectively corresponding to the output voltages of the operational amplifiers to be tested, calculating teTime and tsSlope G of the output voltage between moments0Wherein, ts＝te- Δ t, Δ t being the period of detecting the output voltage of the operational amplifier under test;
let te＝te-Δt，ts＝tsΔ t, according to teTime at and tsCalculating t according to the output voltage of the operational amplifier to be tested corresponding to the time delta teTime at and tsSlope G of the output voltage between instants Δ tt；
Judgment GtAnd G0Whether the absolute value of the difference value of (a) is greater than the maximum allowable error E of the slope;
if yes, calculating the termination time t according to the slopeeDetermining the preset delay time tdelay＝te+2Δt+toffsetWherein t isoffsetAn additional delay for setting;
otherwise, let E be G0-Gt，G0＝Gt，te＝te-Δt，ts＝tsΔ t, according to teTime at and tsCalculating t according to the output voltage of the operational amplifier to be tested corresponding to the time delta teTime at and tsSlope G of the output voltage between instants Δ ttAnd returning to judgment GtAnd G0Is greater than the maximum allowable slope error E.
4. The op-amp test system of claim 1, wherein the first capacitive sampling circuit comprises:
the first end of the first resistor is grounded, and the second end of the first resistor is electrically connected with the output end of the auxiliary test loop;
a first end of the first sampling capacitor is electrically connected with a second end of the first resistor and the output end of the auxiliary test loop, and a second end of the first sampling capacitor is electrically connected with the inverting input end of the operational amplifier to be tested; and
and the first switch is connected in parallel with two ends of the first sampling capacitor.
5. The op-amp test system of claim 4, wherein the first capacitive sampling circuit comprises:
the first end of the second resistor is electrically connected with the first end of the first resistor, and the second end of the second resistor is grounded through a feedback resistor;
a first end of the second sampling capacitor is electrically connected with a second end of the second resistor, and a second end of the second sampling capacitor is electrically connected with a non-inverting input end of the operational amplifier to be tested; and
and the second switch is connected in parallel with two ends of the second sampling capacitor.
6. The operational amplifier test system of claim 5, wherein the auxiliary test loop comprises:
the auxiliary operational amplifier is characterized in that a third resistor and a third switch are sequentially connected in series between the non-inverting input end of the auxiliary operational amplifier and the output end of the operational amplifier to be tested, the inverting input end of the auxiliary operational amplifier is grounded, and the output end of the auxiliary operational amplifier is electrically connected with the second end of the first resistor and the first end of the first sampling capacitor through another feedback resistor;
and the input end of the VI source is electrically connected with the output end of the auxiliary operational amplifier, and the output end of the VI source is electrically connected with the input end of the computing circuit, and is used for periodically sampling and recording sampling time and output voltage of a sampling point and supplying the output voltage to the computing circuit.
7. The operational amplifier test system of claim 6, wherein the output voltage at the sampling point is equal to an average of the output voltages over four power frequency cycles on either side of the sampling point.
8. The operational amplifier test system of claim 5, wherein the switches are electronic relays.
9. The operational amplifier test system of claim 3 wherein the set additional delay toffsetIs 10-2～10-3s。
10. The operational amplifier test system as recited in claim 3, wherein a feedback resistor is coupled between the output of the auxiliary test loop and the first capacitive sampling circuit.
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| CN202020237334.1U CN212514879U (en) | 2020-03-02 | 2020-03-02 | Operational amplifier test system |
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| CN202020237334.1U CN212514879U (en) | 2020-03-02 | 2020-03-02 | Operational amplifier test system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114062900A (en) * | 2021-12-13 | 2022-02-18 | 中国电子科技集团公司第四十七研究所 | Operational amplifier circuit offset voltage testing method |
| CN117092484A (en) * | 2023-07-04 | 2023-11-21 | 江苏润石科技有限公司 | High-speed operational amplifier test circuit and test method thereof |
| CN117214661A (en) * | 2023-09-11 | 2023-12-12 | 无锡市晶源微电子股份有限公司 | Input offset voltage testing device for operational amplifier |
| CN117214661B (en) * | 2023-09-11 | 2024-04-19 | 无锡市晶源微电子股份有限公司 | Input offset voltage testing device for operational amplifier |
-
2020
- 2020-03-02 CN CN202020237334.1U patent/CN212514879U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114062900A (en) * | 2021-12-13 | 2022-02-18 | 中国电子科技集团公司第四十七研究所 | Operational amplifier circuit offset voltage testing method |
| CN117092484A (en) * | 2023-07-04 | 2023-11-21 | 江苏润石科技有限公司 | High-speed operational amplifier test circuit and test method thereof |
| CN117214661A (en) * | 2023-09-11 | 2023-12-12 | 无锡市晶源微电子股份有限公司 | Input offset voltage testing device for operational amplifier |
| CN117214661B (en) * | 2023-09-11 | 2024-04-19 | 无锡市晶源微电子股份有限公司 | Input offset voltage testing device for operational amplifier |
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