GB9710145D0 - Dynamic memory integrated circuit structure - Google Patents

Dynamic memory integrated circuit structure

Info

Publication number
GB9710145D0
GB9710145D0 GBGB9710145.5A GB9710145A GB9710145D0 GB 9710145 D0 GB9710145 D0 GB 9710145D0 GB 9710145 A GB9710145 A GB 9710145A GB 9710145 D0 GB9710145 D0 GB 9710145D0
Authority
GB
United Kingdom
Prior art keywords
integrated circuit
circuit structure
dynamic memory
memory integrated
dynamic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GBGB9710145.5A
Other versions
GB2310940A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
WAHLSTROM SVEN E
Original Assignee
WAHLSTROM SVEN E
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/034,451 external-priority patent/US5317212A/en
Application filed by WAHLSTROM SVEN E filed Critical WAHLSTROM SVEN E
Publication of GB9710145D0 publication Critical patent/GB9710145D0/en
Publication of GB2310940A publication Critical patent/GB2310940A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4099—Dummy cell treatment; Reference voltage generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
GB9710145A 1993-03-19 1994-03-16 Inverting refresh circuit for an amplifying DRAM cell in an FPGA Withdrawn GB2310940A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/034,451 US5317212A (en) 1993-03-19 1993-03-19 Dynamic control of configurable logic
GB9518093A GB2292029B (en) 1993-03-19 1994-03-16 Dynamic control of configurable logic

Publications (2)

Publication Number Publication Date
GB9710145D0 true GB9710145D0 (en) 1997-07-09
GB2310940A GB2310940A (en) 1997-09-10

Family

ID=26307692

Family Applications (2)

Application Number Title Priority Date Filing Date
GB9710144A Expired - Fee Related GB2310939B (en) 1993-03-19 1994-03-16 Operating a dynamic memory
GB9710145A Withdrawn GB2310940A (en) 1993-03-19 1994-03-16 Inverting refresh circuit for an amplifying DRAM cell in an FPGA

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GB9710144A Expired - Fee Related GB2310939B (en) 1993-03-19 1994-03-16 Operating a dynamic memory

Country Status (1)

Country Link
GB (2) GB2310939B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110266303A (en) * 2019-07-17 2019-09-20 重庆线易电子科技有限责任公司 Refresh circuit, method, chip and data transmission system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3778783A (en) * 1971-11-29 1973-12-11 Mostek Corp Dynamic random access memory
US3774177A (en) * 1972-10-16 1973-11-20 Ncr Co Nonvolatile random access memory cell using an alterable threshold field effect write transistor
US4694205A (en) * 1985-06-03 1987-09-15 Advanced Micro Devices, Inc. Midpoint sense amplification scheme for a CMOS DRAM
US5127739A (en) * 1987-04-27 1992-07-07 Texas Instruments Incorporated CMOS sense amplifier with bit line isolation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110266303A (en) * 2019-07-17 2019-09-20 重庆线易电子科技有限责任公司 Refresh circuit, method, chip and data transmission system
CN110266303B (en) * 2019-07-17 2023-04-28 重庆线易电子科技有限责任公司 Refreshing circuit, refreshing method, chip and data transmission system

Also Published As

Publication number Publication date
GB2310939B (en) 1997-10-29
GB2310940A (en) 1997-09-10
GB9710144D0 (en) 1997-07-09
GB2310939A (en) 1997-09-10
GB2310939A8 (en) 2007-02-15

Similar Documents

Publication Publication Date Title
GB9715240D0 (en) Configuration memory integrated circuit
EP0591009A3 (en) Semiconductor memory
GB2264578A8 (en) Nonvolatilte semiconductor memory
GB9423036D0 (en) An integrated circuit memory device
SG68634A1 (en) Dynamic memory
EP0519584A3 (en) Semiconductor memory
GB2287112B (en) Auto-precharging semiconductor memory devices
GB2250617B (en) Semiconductor memory unit
EP0717414A3 (en) Semiconductor memory
GB2280975B (en) Semiconductor memory devices
EP0474238A3 (en) Semiconductor memory circuit
SG44560A1 (en) Integrated circuit memory
KR0132636B1 (en) Memory device
TW303051U (en) Dynamic type memory
EP0458351A3 (en) Semiconductor memory circuit
KR960009033B1 (en) Semiconductor memory
GB2307997B (en) An integrated circuit memory device
EP0441388A3 (en) Semiconductor memory circuit
EP0577106A3 (en) Semiconductor memory circuit
EP0450516A3 (en) Semiconductor memory
EP0449282A3 (en) Semiconductor memory circuit
EP0441379A3 (en) Semiconductor memory
GB2283128B (en) Memory device
GB2276033B (en) Integrated circuits
GB9710145D0 (en) Dynamic memory integrated circuit structure

Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)