CN116779578A - 电子封装件及其封装基板与制法 - Google Patents
电子封装件及其封装基板与制法 Download PDFInfo
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Abstract
一种电子封装件及其封装基板与制法,其封装基板包括于绝缘部中嵌埋线路层及表面处理层,且该表面处理层结合于该线路层的顶面上,而未形成于该线路层的侧面上,故该线路层能维持原本预定的线距,以有利于该封装基板朝细间距/细线路的设计发展。
Description
技术领域
本发明有关一种半导体封装,尤指一种具嵌埋型线路(Embedded Trace)的封装基板及其后续所制作成的电子封装件。
背景技术
随着电子产业的蓬勃发展,电子产品在型态上趋于轻薄短小,在功能上则朝高性能、高功能、高速化的研发方向。因此,为满足半导体装置的高集成度(Integration)及微型化(Miniaturization)需求,故于封装制程中,常常采用具有高密度及细间距的线路的封装基板。
如图1所示,现有封装基板1于其最外侧的介电层10上配置有多个设于该介电层10上的导电迹线11,并于该导电迹线11的外表面上形成一如镍/金材的金属层12,以令该导电迹线11与该金属层12形成线路结构1a。
然而,现有封装基板1中,各该导电迹线11的侧面11c形成有该金属层12,致使该金属层12占据各该导电迹线11之间的空间,导致各该线路结构1a之间的空间宽度(或该导电迹线11的线距)由原本预定的各该导电迹线11的侧面11c之间的距离d1变成各该金属层12的侧面12c之间的距离d2,约缩减10~20微米(即d1-d2=10~20微米),故若以原本预定的距离d1进行布线,则该封装基板1于后续制程中进行打线制程时,相邻的导电迹线11上的焊线容易因各该金属层12之间的距离d2过密而相接触,导致短路。
再者,由于该金属层12占据各该导电迹线11之间的空间(使表面形状呈现圆弧形),使得相邻的导电迹线11上的打线接点容易偏移而造成打线焊接不黏固,因而于设计该线路结构1a时,需增宽各该导电迹线11的侧面11c之间的距离d1,以避免短路的问题,但却也导致该封装基板1无法朝细间距/细线路的需求发展,故现有封装基板1难以满足半导体芯片的高密度接点数的需求。
因此,如何克服上述现有技术的种种问题,实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失,本发明提供一种电子封装件及其封装基板与制法,有利于该封装基板朝细间距/细线路的设计发展。
本发明的封装基板,包括:一绝缘部;线路层,其嵌埋于该绝缘部中;以及表面处理层,其嵌埋于该绝缘部中并结合于该线路层的顶面上,且该表面处理层未形成于该线路层的侧面上。
本发明亦提供一种封装基板的制法,包括:提供一绝缘部;将线路层嵌埋于该绝缘部中;以及形成表面处理层于该线路层的顶面上,且该表面处理层未形成于该线路层的侧面上。
前述的封装基板及其制法中,该表面处理层的表面齐平该绝缘部的表面,以令该表面处理层外露于该绝缘部。
前述的封装基板及其制法中,形成该表面处理层的材质为导电材。
本发明还提供一种电子封装件,包括:一前述的封装基板;以及电子元件,其设于该绝缘部上且电性连接该线路层。
前述的电子封装件中,该电子元件以打线方式电性连接该线路层。
由上可知,本发明的电子封装件及其封装基板,主要借由该表面处理层未形成于该线路层的侧面上,使该表面处理层不会占据该线路层的侧面空间,因而该线路层的侧面空间能维持原本预定的线距,故相较于现有技术,本发明的封装基板若以原本预定的线距进行布线,则该封装基板于后续制程中进行打线制程时,相邻的焊线不会相接触,因而能避免短路的问题发生。
再者,由于该表面处理层不会占据该线路层的侧面空间,使得该线路层的线距可依需求设计,而无需增加线距,即可避免打线接点容易偏移而造成打线焊接不黏固的问题,故相较于现有技术,本发明的封装基板的线路层有利于朝细间距/细线路的设计发展,以满足半导体芯片的高密度接点数的需求。
附图说明
图1为现有封装基板的剖面示意图。
图2为本发明的封装基板的剖视示意图。
图3为本发明的电子封装件的剖视示意图。
图4A至图4D为本发明的封装基板的制法的剖视示意图。
其中,附图标记说明如下:
1,2封装基板
1a线路结构
10介电层
11,21导电迹线
11c,12c,21c侧面
12金属层
2a,2b线路层
20,40绝缘部
20a,22a表面
21a顶面
22表面处理层
23电性连接垫
24导电层
25阻层
26绝缘保护层
3电子封装件
30电子元件
30a作用面
30b非作用面
300电极垫
31焊线
35封装材
40a第一侧
40b第二侧
400导电盲孔
d,d1,d2距离。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式,熟悉此技艺的人士可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供熟悉此技艺的人士的了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上”、及“一”等的用语,亦仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当亦视为本发明可实施的范畴。
图2为本发明的封装基板2的剖面示意图。如图2所示,该封装基板2包括:一绝缘部20、至少一线路层2a及一表面处理层22。
所述的绝缘部20为单一绝缘层结构或多层堆叠绝缘层结构,且形成该绝缘部20的材质为介电材,如味之素增层膜(Ajinomoto Build-up Film,简称ABF)、预浸材(Prepreg,简称PP)或其它等,并无特别限制。
所述的线路层2a以嵌埋方式配置于该绝缘部20中,且包含多个导电迹线21。
于本实施例中,该导电迹线21的顶面21a低于该绝缘部20的表面20a。
所述的表面处理层22以嵌埋方式配置于该绝缘部20中并结合于该线路层2a的顶面21a上,而未形成于该线路层2a的侧面21c上。
于本实施例中,该表面处理层22的表面22a齐平该绝缘部20的表面20a,以令该表面处理层22外露于该绝缘部20。
再者,形成该表面处理层22的材质为镍/金(Ni/Au)、镍/钯/金(Ni/Pd/Au)、有机保焊剂(Organic Solderability Preservatives,简称OSP)或其它等。
因此,本发明的封装基板2借由各该导电迹线21的侧面21c未形成有该表面处理层22,使该表面处理层22不会占据各该导电迹线21之间的空间,因而各该导电迹线21的侧面21c的间的空间宽度(或该线路层2a的线距)维持原本预定的距离d,故相较于现有技术,本发明的封装基板2若以原本预定的距离d进行布线,则该封装基板2于后续制程中进行打线制程时,相邻的导电迹线21上的焊线31(如图3所示)不会相接触,因而能避免短路的问题发生。
再者,由于该表面处理层22不会占据各该导电迹线21之间的空间,使得各该导电迹线21的侧面21c之间的空间宽度(或该线路层2a的线距)可依需求设计其两者之间的距离d,而无需增宽各该导电迹线21的侧面21c之间的距离d,即可避免相邻的导电迹线21上的打线接点容易偏移而造成打线焊接不黏固的问题,故该封装基板2的线路层2a有利于朝细间距/细线路的设计发展,以满足半导体芯片的高密度接点数的需求。
另外,由于该表面处理层22未形成于该线路层2a的侧面21c上,故于相同布线数量下,该封装基板2所用的金属材用量少于现有封装基板1所用的金属材用量,因而能减少该封装基板2的制作成本。
另外,于后续应用中,如图3所示,该封装基板2可于该绝缘部20的表面20a上接合至少一电子元件30,以形成电子封装件3。
所述的电子元件30为主动元件、被动元件或其组合,其中,该主动元件为例如半导体芯片,且该被动元件为例如电阻、电容及电感。
于本实施例中,该电子元件30为半导体芯片,其具有相对的作用面30a与非作用面30b,该作用面30a上具有多个电极垫300,且该电子元件30以其非作用面30b结合于该绝缘部20的表面20a上,并以其电极垫300借由多个如金线的焊线31以打线方式结合该表面处理层22以电性连接该线路层2a,再以封装材35形成于该封装基板2上以包覆该电子元件30与焊线31。
图4A至图4D为本发明的封装基板2的制法的剖面示意图。
如图4A所示,于一绝缘部40上以图案化方式进行布线制程,以形成多个线路层2a,2b。
于本实施例中,该绝缘部40具有相对的第一侧40a与第二侧40b,且于该第一侧40a的布线以蚀刻金属的方式将该线路层2a嵌埋于该绝缘部40中,而于该第二侧40b的布线以电镀金属的方式将该线路层2b形成于该绝缘部40的表面上,并于该绝缘部40中形成多个导电盲孔400以电性连接该第一侧40a与第二侧40b的线路层2a,2b。
再者,该第一侧40a的线路层2a包含多个导电迹线21,且该第二侧40b的线路层2b具有多个电性连接垫23。
如图4B所示,先于该第二侧40b的绝缘表面上形成一导电层24,再于该绝缘部40的第一侧40a与第二侧40b上覆盖一如光阻的图案化阻层25,以令该第一侧40a的线路层2a的局部表面外露于该阻层25。之后,借由该导电层24电镀一表面处理层22于该线路层2a的导电迹线21的外露表面上,使该表面处理层22的表面齐平该绝缘部40的表面。
如图4C所示,移除该阻层25及该导电层24,以令该表面处理层22外露于该绝缘部40。
如图4D所示,于该绝缘部40的第一侧40a与第二侧40b上形成一如防焊层的绝缘保护层26,且令该表面处理层22及该些电性连接垫23外露于该绝缘保护层26。
综上所述,本发明的封装基板借由将该线路层嵌埋于该绝缘部中,且该表面处理层未形成于该线路层的侧面上,使各该导电迹线的侧面之间的空间宽度(或该线路层的线距)维持原本预定的距离,故本发明的封装基板不仅能避免短路的问题,且有利于朝细间距/细线路的设计发展。
上述实施例仅用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟习此项技艺的人士均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。
Claims (8)
1.一种封装基板,包括:
一绝缘部;
线路层,其嵌埋于该绝缘部中;以及
表面处理层,其嵌埋于该绝缘部中并结合于该线路层的顶面上,且该表面处理层未形成于该线路层的侧面上。
2.如权利要求1所述的封装基板,其中,该表面处理层的表面齐平该绝缘部的表面,以令该表面处理层外露于该绝缘部。
3.如权利要求1所述的封装基板,其中,形成该表面处理层的材质为导电材。
4.一种电子封装件,包括:
如权利要求1所述的封装基板;以及
电子元件,其设于该绝缘部上且电性连接该线路层。
5.如权利要求4所述的电子封装件,其中,该电子元件以打线方式电性连接该线路层。
6.一种封装基板的制法,包括:
提供一绝缘部;
将线路层嵌埋于该绝缘部中;以及
形成表面处理层于该线路层的顶面上,且该表面处理层未形成于该线路层的侧面上。
7.如权利要求6所述的封装基板的制法,其中,该表面处理层的表面齐平该绝缘部的表面,以令该表面处理层外露于该绝缘部。
8.如权利要求6所述的封装基板的制法,其中,形成该表面处理层的材质为导电材。
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