CN116759312A - Preparation method of gallium nitride current aperture vertical electronic device - Google Patents
Preparation method of gallium nitride current aperture vertical electronic device Download PDFInfo
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- CN116759312A CN116759312A CN202310686283.9A CN202310686283A CN116759312A CN 116759312 A CN116759312 A CN 116759312A CN 202310686283 A CN202310686283 A CN 202310686283A CN 116759312 A CN116759312 A CN 116759312A
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 213
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 159
- 238000002360 preparation method Methods 0.000 title abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 123
- 239000013078 crystal Substances 0.000 claims abstract description 109
- 230000000903 blocking effect Effects 0.000 claims abstract description 61
- 238000000137 annealing Methods 0.000 claims abstract description 39
- 239000000463 material Substances 0.000 claims abstract description 33
- 230000007547 defect Effects 0.000 claims abstract description 30
- 239000003989 dielectric material Substances 0.000 claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims abstract description 19
- 238000005498 polishing Methods 0.000 claims abstract description 16
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000011282 treatment Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 47
- 238000005468 ion implantation Methods 0.000 claims description 39
- 239000001301 oxygen Substances 0.000 claims description 21
- 229910052760 oxygen Inorganic materials 0.000 claims description 21
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 19
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000002513 implantation Methods 0.000 claims description 12
- 229910002704 AlGaN Inorganic materials 0.000 claims description 11
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- 229910052786 argon Inorganic materials 0.000 claims description 7
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical group [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims description 7
- 229910001195 gallium oxide Inorganic materials 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 238000003780 insertion Methods 0.000 claims description 5
- 230000037431 insertion Effects 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 16
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 90
- 235000012431 wafers Nutrition 0.000 description 14
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- 230000003213 activating effect Effects 0.000 description 4
- 229910001425 magnesium ion Inorganic materials 0.000 description 4
- -1 oxygen ion Chemical class 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 230000005533 two-dimensional electron gas Effects 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010884 ion-beam technique Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
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- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
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- 229910052733 gallium Inorganic materials 0.000 description 1
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- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
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- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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Abstract
The application relates to the technical field of semiconductor devices, in particular to a preparation method of a gallium nitride current aperture vertical type electronic device. Preparing a current blocking structure by forming a defect layer in a gallium nitride single crystal substrate and respectively preparing a current blocking structure in two preset areas of the gallium nitride single crystal substrate, wherein the two preset areas are provided with preset interval distances; the material of the current blocking structure comprises a dielectric material and an ultra-wide band gap material; and bonding the top of the gallium nitride monocrystal substrate with the supporting substrate, sequentially carrying out annealing stripping and polishing treatment, and sequentially epitaxial-extending a gallium nitride channel layer, an aluminum gallium nitride barrier layer and a preparation electrode layer. The device obtained by the preparation method has the characteristics of being capable of bearing larger breakdown voltage and being difficult to generate punch-through electric leakage.
Description
Technical Field
The application relates to the technical field of semiconductor devices, in particular to a preparation method of a gallium nitride current aperture vertical type electronic device.
Background
Gallium nitride current aperture vertical electron devices (GaN Current Aperture Vertical Electron Transistor, gaN CAVET), also known as vertical gallium nitride field effect transistors (MOSFETs), combine the advantages of high concentration, high mobility of two-dimensional electron gas of AlGaN/GaN heterojunction and high breakdown field strength, high withstand voltage of vertical GaN electron devices. When the device is started, electrons reach the lower part of the grid along the horizontal direction of AlGaN/GaN heterojunction two-dimensional electron gas from the source electrode and reach the drain along the vertical direction, and referring to FIG. 1, p-GaN is used as a current blocking layer to limit a current flowing path; when the device is turned off, the electric field breaks down in the vertical direction, so the device benefits from a high breakdown voltage in the vertical direction and can greatly reduce the device area and size compared to a lateral device. The GaN CAVET device has a plurality of excellent characteristics of low on-resistance, high breakdown voltage, high output power and the like.
In the related art, the p-GaN current blocking layer of the GaN CAVET device is usually formed by adopting an ion implantation method, such as a p-GaN current blocking layer formed by Mg ion implantation, but the current blocking layer prepared by adopting the method has low doping concentration and poor performance, so that serious problems of device leakage, breakdown and the like are easily caused, and the p-GaN current blocking layer cannot bear larger breakdown voltage and is easy to cause through leakage.
Disclosure of Invention
The application aims to solve the technical problems that a GaN CAVET device obtained by a p-GaN current blocking layer formed by Mg ion implantation in the prior art is easy to leak and break down.
In order to solve the above technical problems, the present application discloses a method for manufacturing a gallium nitride current aperture vertical electronic device, which includes:
providing a gallium nitride single crystal substrate;
forming a defect layer in a gallium nitride single crystal substrate, and preparing a current blocking structure in two preset areas of the gallium nitride single crystal substrate with preset interval distance respectively; the opposite two ends of the gallium nitride single crystal substrate are respectively provided with a preset area; the bottoms of the two preset areas and the bottom of the gallium nitride single crystal substrate have a first preset distance; the tops of the two current blocking structures and the top of the gallium nitride monocrystal substrate are positioned on the same plane; the material of the current blocking structure comprises a dielectric material and an ultra-wide band gap material;
providing a supporting substrate;
bonding the top of the gallium nitride monocrystal substrate and the supporting substrate to obtain a first structure;
sequentially carrying out annealing stripping and polishing treatment on the first structure to obtain a second structure; the second structure comprises a support substrate and a first gallium nitride single crystal layer;
sequentially extending a gallium nitride channel layer and an aluminum gallium nitride barrier layer on the first gallium nitride single crystal layer of the second structure to obtain a third structure;
preparing a source electrode and a gate electrode on the top surface of the third structure, and preparing a drain electrode on the bottom surface of the third structure; the top surface of the third structure is close to the AlGaN barrier layer.
In one possible embodiment, in the case that the material of the current blocking structure is a dielectric material, forming a defect layer in the gallium nitride single crystal substrate, and preparing one current blocking structure in each of two preset regions of the gallium nitride single crystal substrate where a preset separation distance exists, respectively, including:
ion implantation is performed from the implantation surface toward the gallium nitride single crystal substrate to form a defect layer in the gallium nitride single crystal substrate;
removing gallium nitride monocrystal portions of two preset areas of the gallium nitride monocrystal substrate by utilizing photoetching and etching technologies to obtain an etched structure;
growing a dielectric material on the top surface of the etched structure;
removing the dielectric material on the injection surface; the top surface of the etched structure is the top surface of the gallium nitride monocrystal substrate;
and polishing the top surface of the etched structure to obtain the gallium nitride single crystal substrate with the two current blocking structures.
In one possible embodiment, in the case where the material of the current blocking structure is gallium oxide in ultra wide band material, forming a defect layer in the gallium nitride single crystal substrate, and preparing one current blocking structure in each of two preset regions of the gallium nitride single crystal substrate where a preset separation distance exists, the method includes:
oxygen ion implantation is carried out on the two preset areas from the surfaces of the two corresponding preset areas in the top surface of the gallium nitride single crystal substrate, so that an oxygen ion implantation area is respectively formed in the two preset areas with preset interval distances of the gallium nitride single crystal substrate;
annealing the two oxygen ion implantation areas of the gallium nitride single crystal substrate to obtain the gallium nitride single crystal substrate with two current blocking structures;
ion implantation is performed from the top surface of the gallium nitride single crystal substrate to form a defect layer in the gallium nitride single crystal substrate.
In one possible embodiment, the dielectric material includes silicon dioxide, silicon nitride, and aluminum oxide;
the ultra-wideband material comprises gallium oxide.
In one possible embodiment, the conditions for annealing the oxygen ion implanted region include:
the annealing atmosphere is vacuum or nitrogen;
the annealing temperature is 600-1100 ℃;
the annealing time comprises 30 seconds to 10 minutes.
In one possible embodiment, the conditions for annealing the first structure include:
the annealing atmosphere is vacuum, nitrogen or argon;
the annealing temperature is 300-900 ℃;
the annealing time is 1 minute to 24 hours.
In one possible embodiment, annealing, stripping and polishing are sequentially performed on the first structure to obtain a second structure, including:
stripping the first structure along the defect layer by using an annealing process to obtain an initial second structure; the initial second structure comprises a support substrate and a first gallium nitride single crystal layer;
and removing the residual defect layer on the initial second structure by using a polishing technology to obtain the second structure.
In one possible embodiment, sequentially epitaxially growing a gallium nitride channel layer and an aluminum gallium nitride barrier layer on the first gallium nitride single crystal layer of the second structure, a third structure is obtained, including:
and sequentially extending a gallium nitride channel layer, an aluminum nitride inserting layer, an aluminum gallium nitride barrier layer and a gallium nitride cap layer on the first gallium nitride single crystal layer of the second structure to obtain a third structure.
In one possible embodiment, the support substrate comprises a stack of a highly doped substrate and a lowly doped substrate;
the top of the gallium nitride single crystal substrate is bonded to the low doped substrate.
The application also discloses a gallium nitride current aperture vertical electronic device which is prepared by the method.
By adopting the technical scheme, the gallium nitride current aperture vertical electronic device provided by the application has the following beneficial effects:
preparing a current blocking structure by forming a defect layer in a gallium nitride single crystal substrate and respectively preparing a current blocking structure in two preset areas of the gallium nitride single crystal substrate, wherein the two preset areas are provided with preset interval distances; the opposite two ends of the gallium nitride single crystal substrate are respectively provided with a preset area; the bottoms of the two preset areas and the bottom of the gallium nitride single crystal substrate have a first preset distance; the tops of the two current blocking structures and the top of the gallium nitride monocrystal substrate are positioned on the same plane; the material of the current blocking structure comprises a dielectric material and an ultra-wide band gap material; providing a supporting substrate; bonding the top of the gallium nitride monocrystal substrate and the supporting substrate to obtain a first structure; sequentially carrying out annealing stripping and polishing treatment on the first structure to obtain a second structure; sequentially extending a gallium nitride channel layer and an aluminum gallium nitride barrier layer on the first gallium nitride single crystal layer of the second structure to obtain a third structure; preparing a source electrode and a gate electrode on the top surface of the third structure, and preparing a drain electrode on the bottom surface of the third structure; the top surface of the third structure is the surface opposite to the bottom surface of the second structure. Therefore, the device obtained by adopting the preparation method has the advantages of being capable of bearing larger breakdown voltage and being difficult to cause punch-through electric leakage.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a gallium nitride current aperture vertical electronic device according to an embodiment of the present application;
fig. 2 is a schematic flow chart of a method for manufacturing a gallium nitride current aperture vertical electronic device according to an embodiment of the application;
FIG. 3 is a schematic diagram of a process for fabricating a GaN current aperture vertical electronic device according to an embodiment of the application;
fig. 4 is a schematic diagram of a process for preparing a current blocking structure according to an embodiment of the present application.
The following supplementary explanation is given to the accompanying drawings:
1-gallium nitride single crystal substrate; 101-an injection plane; 102-an oxygen ion implantation region; 103-a first gallium nitride single crystal layer; 104-a second gallium nitride single crystal layer; 2-a preset area; 3-a current blocking structure; 4-a defect layer; 5-supporting the substrate; 501-a highly doped substrate; 502-a low doped substrate; 6-a first structure; 7-a second structure; 8-an initial second structure; a 9-gallium nitride channel layer; a 10-aluminum nitride insertion layer; 11-aluminum gallium nitride barrier layer; a 12-gallium nitride cap layer; 13-third structure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the application. In the description of the present application, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "top", "bottom", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may include one or more of the feature, either explicitly or implicitly. Moreover, the terms "first," "second," and the like, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein.
For the purposes of the following detailed description, it is to be understood that the application may assume various alternative variations and step sequences, except where expressly specified to the contrary. Furthermore, except in any operating examples, or where otherwise indicated, all numbers expressing, for example, quantities of ingredients used in the specification and claims are to be understood as being modified in all instances by the term "about". Accordingly, unless indicated to the contrary, the numerical parameters set forth in the following specification and attached claims are approximations that may vary depending upon the desired properties to be obtained by the present application. At the very least, and not as an attempt to limit the application of the doctrine of equivalents to the scope of the claims, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques.
Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
When a range of values is disclosed herein, the range is considered to be continuous and includes both the minimum and maximum values for the range, as well as each value between such minimum and maximum values. Further, when a range refers to an integer, each integer between the minimum and maximum values of the range is included. Further, when multiple range description features or characteristics are provided, the ranges may be combined. In other words, unless otherwise indicated, all ranges disclosed herein are to be understood to include any and all subranges subsumed therein. For example, a specified range from "1 to 10" should be considered to include any and all subranges between the minimum value of 1 and the maximum value of 10. Exemplary subranges from 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, and the like.
Referring to fig. 1, a schematic structural diagram of a gallium nitride current aperture vertical electronic device according to an embodiment of the application is shown. The GaN CAVET device comprises a stacked drain electrode, an n-GaN substrate (n-type doped gallium nitride), and n-type GaN substrate - GaN (i.e. n-type low doped gallium nitride), P-GaN current blocking layer (P-doped gallium nitride), gaN, alGaN and source gate electrode; wherein GaN and AlGaN form an AlGaN/GaN heterojunction, electrons reach the gate electrode (e.g., G structure in fig. 1) from the source electrode (e.g., S structure in fig. 1) along the two-dimensional electron gas horizontal direction of the AlGaN/GaN heterojunction, p-GaN serves as a current blocking layer to limit the current flow path, so that the electron flow can reach the drain electrode (e.g., D structure in fig. 1) along the vertical direction, and when the device is turned off, the electric field breaks down along the vertical direction, so that the device benefits from the high breakdown voltage along the vertical direction, and the device area and size can be greatly reduced compared with the lateral device. Therefore, the GaN CAVET device has many excellent characteristics of low on-resistance, high breakdown voltage, high output power, etc., however, the p-GaN current blocking layer of the GaN CAVET device in the prior art mainly adopts an ion implantation method or a regrowth method, such as a p-GaN current formed by Mg ion implantationThe current blocking layer prepared by the method has low doping concentration and poor performance, and is easy to cause serious problems of electric leakage, breakdown and the like of devices, and the other method is to grow a GaN through hole (which can be a region between two p-GaN layers as shown in figure 1) and an AlGaN/GaN heterojunction after growing p-GaN, and the step of growing the GaN through hole is carried out after growing p-GaN firstly, so that the C axis of a grown GaN crystal has deviation, and the obtained AlGaN/GaN heterojunction and GaN through hole crystal have poor quality, so that an electric leakage channel is formed; the p-GaN current blocking layer cannot bear larger drain voltage, and punch-through leakage is easy to occur. Therefore, the application discloses a preparation method of a gallium nitride current aperture vertical electronic device, referring to fig. 2, the preparation method comprises the following steps:
s201: a gallium nitride single crystal substrate 1 (structure shown in fig. 3 (a)) is provided.
In this embodiment, in order to improve the production efficiency, an array device may be produced on a gallium nitride single crystal wafer, where the gallium nitride single crystal substrate 1 may refer to a gallium nitride single crystal wafer.
S202: forming a defect layer 4 in the gallium nitride single crystal substrate 1, and preparing a current blocking structure 3 in two preset areas 2 of the gallium nitride single crystal substrate 1 with preset spacing distances respectively; opposite ends of the gallium nitride single crystal substrate 1 are respectively provided with a preset area 2; the bottoms of the two preset areas 2 are a first preset distance from the bottom of the gallium nitride single crystal substrate 1; the tops of the two current blocking structures 3 and the top of the gallium nitride single crystal substrate 1 are positioned on the same plane; the material of the current blocking structure 3 includes a dielectric material and an ultra wide band gap material.
In one possible embodiment, the dielectric material in step S202 includes silicon dioxide, silicon nitride, and aluminum oxide; the ultra-wideband material comprises gallium oxide. The method for preparing the current blocking structure 3 can be divided into two methods according to the material type of the current blocking structure 3, one is a dielectric growth method (refer to fig. 3); another method of using ion implantation and annealing activation (see fig. 4) will be described below for two methods of preparing the current blocking structure 3, respectively:
in a possible embodiment, in the case that the material of the current blocking structure 3 is a dielectric material, the material of the current blocking structure 3 may be silicon dioxide, silicon nitride, aluminum oxide, or the like. The specific embodiment of step S202 may include: ion implantation is first performed from the implantation surface 101 to the gallium nitride single crystal substrate 1 to form a defect layer 4 (a structure shown in fig. 3 (b)) in the gallium nitride single crystal substrate 1, the defect layer 4 dividing the gallium nitride single crystal substrate 1 into a first gallium nitride single crystal layer 103 and a second gallium nitride single crystal layer 104; removing gallium nitride single crystal portions of the two preset areas 2 of the gallium nitride single crystal substrate 1 by utilizing photoetching and etching technologies to obtain an etched structure (a structure shown as a graph (c) in fig. 3); growing a dielectric material on the top surface of the etched structure to obtain a structure shown in a graph (d) in fig. 3; removing the dielectric material on the implantation surface 101 to obtain a structure as shown in fig. 3 (e); the top surface of the etched structure may be the top surface of the gallium nitride single crystal substrate 1 as shown in the diagram (b) in fig. 3; the top surface of the etched structure is polished so that the current blocking structure 3 and the implantation surface 101 are in the same plane, resulting in a gallium nitride single crystal substrate 1 having two current blocking structures 3. Optionally, the two preset regions 2 are located in the first gallium nitride single crystal layer 103, and two opposite ends of the first gallium nitride single crystal layer 103 are respectively provided with one preset region 2, and the gallium nitride single crystal material in the preset region 2 is etched by using photolithography and etching technology, so that the first gallium nitride single crystal layer 103 has a convex structure. Alternatively, a patterned barrier layer can be formed on the gallium nitride single crystal substrate 1 by using a photolithography technique, specifically, an exposed portion can be etched by using an ion beam in an etching technique, and then the barrier layer is removed, thereby completing etching. Alternatively, the polishing technique may specifically be chemical mechanical polishing; the above-described method of removing the dielectric material on the implantation surface 101 includes ion beam etching or chemical wet etching. Alternatively, methods of growing the dielectric material include, but are not limited to, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, and atomic layer deposition.
It should be noted that, the above mainly describes the method of preparing the defect layer 4 and then preparing the current blocking structure 3, and the step of preparing the current blocking structure 3 and then performing ion implantation to form the defect layer 4 may be selected according to the requirement, but in this embodiment, since the surface layer of the entire substrate includes two different materials, namely gallium nitride and other dielectric materials (such as silicon dioxide), a separate implantation mode may be adopted during ion implantation, so that the ion implantation condition of implanting gallium nitride into the substrate and the ion implantation condition of implanting silicon dioxide into the substrate are different, so as to form a uniform defect layer 4.
In another possible embodiment, referring to fig. 4, in the case where the material of the current blocking structure 3 is gallium oxide in the ultra wide band gap material, the embodiment of step S202 may include: oxygen ion implantation is performed to the two preset regions 2 from the surface corresponding to the two preset regions 2 in the top surface of the gallium nitride single crystal substrate 1 (the structure shown in fig. 4 (a)) to form one oxygen ion implantation region 102 (the structure shown in fig. 4 (b)) in each of the two preset regions 2 of the gallium nitride single crystal substrate 1 having a preset spacing distance; annealing and activating the two oxygen ion implantation regions 102 of the gallium nitride single crystal substrate 1 to obtain a gallium nitride single crystal substrate 1 having two current blocking structures 3 (a structure shown in fig. 4 (c)); ion implantation is performed from the top surface of the gallium nitride single crystal substrate 1 to form a defect layer 4 (structure shown in fig. 4 (d)) within the gallium nitride single crystal substrate 1. Alternatively, when oxygen ion implantation is performed, two preset regions 2 to be implanted need to be determined first, so that oxygen ion implantation can be performed from corresponding surface regions of the top surface of the gallium nitride single crystal substrate 1, so as to form oxygen ion implantation regions 102 in the two preset regions 2, and the depth of oxygen ion implantation can be set as required.
Optionally, the oxygen ion implantation conditions include: the oxygen ion implantation energy is 1 keV-1000 keV; oxygen ion implantation dose 1×10 15 cm -2 ～1×10 18 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the Alternatively, multiple implantation schemes, such as 5keV implantation 1X 10, may be chosen 15 cm -2 Thereafter, a further 20keV implant 1X 10 16 cm -2 To improve the injection effect.
In one possible embodiment, the conditions for annealing the oxygen ion implanted region 102 include: the annealing atmosphere is vacuum or nitrogen; the annealing temperature includes 600-1100 deg.c, such as 600 deg.c, 700 deg.c, 800 deg.c, 900 deg.c, 1100 deg.c, etc. The annealing time includes 30 seconds to 10 minutes, and may be 30 seconds, 1 minute, 3 minutes, 5 minutes, 7 minutes, 10 minutes, and the like.
It is understood that the ion implantation method for forming the defect layer 4 includes hydrogen ion implantation, helium ion implantation, and hydrogen helium ion co-implantation. When the ion implantation method is hydrogen ion implantation to the gallium nitride single crystal substrate 1, the implantation energy is 10keV to 5MeV, and the implantation dose is 1×10 17 cm -2 ～1×10 18 cm -2 . The position where the defect layer 4 is formed can be adjusted as needed. Compared with the P-GaN current blocking layer formed by adopting Mg ion implantation and the P-GaN growing method in the prior art, the method has the advantages of simple preparation process, better current restriction effect of the prepared current blocking structure and more breakdown voltage resistance (the breakdown voltage of the current blocking structure in the application is about 2-3 times of the breakdown voltage of the P-GaN in the prior art), and avoids the problems of easy electric leakage, breakdown and the like caused by the traditional method.
S203: a support substrate 5 is provided.
In one possible embodiment, the support substrate 5 includes a stacked highly doped substrate 501 and a lowly doped substrate 502 (a structure shown in fig. 3 (g)), and the top of the gallium nitride single crystal substrate 1 is bonded to the lowly doped substrate 502.
The material of the supporting substrate 5 may be a wide band gap/ultra-wide band gap semiconductor material formed by one or more of silicon carbide, gallium oxide, diamond and aluminum nitride, which will greatly increase the breakdown voltage of the device. The silicon carbide, diamond and aluminum nitride materials also have extremely high heat conductivity, and can improve the heat dissipation capacity and performance of the GaN CAVET device. Alternatively, the thickness of the highly doped substrate 501 of the present application may be set to be greater than 500 microns, typically below 500 microns in the prior art, so as to further enhance the breakdown voltage of the device.
S204: the top of the gallium nitride single crystal substrate 1 is bonded to the supporting substrate 5 to obtain a first structure 6 (a structure shown in fig. 3 (h)).
The bonding method can be hydrophilic direct bonding or surface activation bonding.
Alternatively, the hydrophilic direct bonding may specifically include the steps of:
1) The two wafers to be bonded (for example, the gallium nitride single crystal substrate 1 and the support substrate 5) are activated, and specifically, one or a sequential combination of nitrogen plasma, argon plasma and oxygen plasma can be adopted for activation. The method aims to remove pollutants and natural oxide layers on the surface of the wafer and open hanging bonds on the surface of the wafer.
2) And cleaning the two activated wafers to be bonded to enable the surfaces of the wafers to be attached with-OH.
3) And bonding the two wafers under pressure.
Optionally, the wafer to be bonded may be cleaned before the step 1) to remove contaminants such as surface contaminants and particles.
The surface-activated bonding specifically may include the steps of:
and placing the two wafers to be bonded in an ultra-high vacuum environment, activating the surfaces of the wafers by using argon plasma, and pressing for direct bonding. Or placing the two wafers to be bonded in an ultrahigh vacuum environment, activating the surfaces of the wafers by adopting argon plasma, sputtering a nano Si medium layer on the surfaces of the wafers, activating the nano Si layer by the argon plasma, and directly bonding under pressure.
S205: the first structure 6 is sequentially subjected to annealing, peeling and polishing treatments to obtain a second structure 7 (a structure shown in fig. 3 (j)), the second structure 7 including the support substrate 5, the two current blocking structures 3 and the first gallium nitride single crystal layer 103.
In one possible embodiment, the annealing, stripping and polishing processes are sequentially performed on the first structure 6 in step S205, so as to obtain a second structure 7, including: stripping the first structure 6 along the defect layer 4 by an annealing process to obtain an initial second structure 8 (see fig. 3 (i)); the initial second structure 8 comprises a support substrate 5, two current blocking structures 3, a first monocrystalline layer 103 of gallium nitride and a residual defect layer 4; the residual defect layer 4 on the original second structure 8 is removed by polishing techniques, resulting in a second structure 7. Alternatively, the polishing technique for removing the defect layer 4 may be one or a combination of chemical mechanical polishing, ion beam etching, mechanical lapping, chemical wet etching.
In one possible embodiment, the conditions for annealing the first structure 6 include: the annealing atmosphere is vacuum, nitrogen or argon; the annealing temperature includes 300-900 ℃, such as 300 ℃, 500 ℃, 700 ℃, 800 ℃, 900 ℃ and the like. The annealing time includes 1 minute to 24 hours, and may be, for example, 1 minute, 10 minutes, 30 minutes, 1 hour, 3 hours, 5 hours, 12 hours, 24 hours, or the like.
The second structure 7 prepared based on the above steps has excellent single crystal quality because the gallium nitride single crystal layer is directly stripped from the gallium nitride single crystal substrate 1, avoids the problem of electric leakage caused by low crystal quality of a regrowth method, and further improves the anti-electric leakage performance, thereby greatly improving the performance and reliability of the device, and the stripped gallium nitride single crystal substrate 1 can be recycled after surface treatment, and also greatly reduces the material cost of expensive gallium nitride single crystals.
S206: a gallium nitride channel layer 9 and an aluminum gallium nitride barrier layer 11 are sequentially epitaxially grown on the first gallium nitride single crystal layer of the second structure 7, resulting in a third structure 13 (a structure shown in fig. 3 (k)).
In one possible embodiment, the specific implementation of step S206 may be: a gallium nitride channel layer 9, an aluminum nitride insertion layer 10, an aluminum gallium nitride barrier layer 11 and a gallium nitride cap layer 12 are sequentially epitaxially grown on the top surface of the second structure 7, resulting in a third structure 13.
Wherein, the aluminum nitride insertion layer 10 can improve channel electron density, and can inhibit two-dimensional electron gas from penetrating into the gallium aluminum nitride barrier layer, thereby improving channel electron mobility. The gallium nitride cap layer 12 can effectively reduce the resistance of ohmic contact, and on one hand, the gallium nitride cap layer can improve the mobility of 2DEG at the cost of slightly reducing the concentration of carriers under the action of polarization effect, and on the other hand, the Schottky contact barrier on the AlGaN/GaN heterojunction structure can be increased, so that the gate leakage current is obviously reduced. The surface and the integral property of the material of the AlGaN/GaN heterojunction structure can be improved, so that the reliability of the device is improved.
S207: preparing a source electrode and a gate electrode on the top surface of the third structure 13, and preparing a drain electrode on the bottom surface of the third structure 13 to obtain a target device (a structure shown as a graph (l) in fig. 3); the top surface of the third structure 13 is close to the aluminium gallium nitride barrier layer.
The source electrode, the drain electrode and the gate electrode can be prepared by adopting common metal electrode preparation processes, such as photoetching, metal growth, metal stripping and the like, in sequence.
The present application also discloses a gallium nitride current aperture vertical electronic device, which is prepared by the method, and the obtained gallium nitride current aperture vertical electronic device can be a structure as shown in a graph (l) in fig. 3, specifically, the gallium nitride high electron mobility transistor comprises a drain electrode, a high doped substrate 501, a low doped substrate 502, a first gallium nitride single crystal layer 103, two current blocking structures 3 positioned in the first gallium nitride single crystal layer 103, a gallium nitride channel layer 9, an aluminum nitride insertion layer 10, an aluminum gallium nitride barrier layer 11, a gallium nitride cap layer 12 and a source gate electrode, which are stacked from bottom to top. The upper surfaces of the two current blocking structures 3 and the upper surface of the gallium nitride single crystal substrate 1 have a first preset distance, the lower surfaces of the two current blocking structures 3 and the lower surface of the first gallium nitride single crystal layer 103 are located on the same plane, and the materials of the current blocking structures 3 comprise dielectric materials and ultra-wide band gap materials. The possible structure of the gallium nitride current aperture vertical electronic device can be described in the above preparation method, and will not be described herein.
The foregoing description of the preferred embodiments of the present application is not intended to limit the application, but rather, the application is to be construed in scope and spirit of the application.
Claims (10)
1. A method for manufacturing a gallium nitride current aperture vertical electronic device, comprising:
providing a gallium nitride single crystal substrate;
forming a defect layer in the gallium nitride single crystal substrate, and respectively preparing a current blocking structure in two preset areas of the gallium nitride single crystal substrate with preset interval distance; opposite two ends of the gallium nitride single crystal substrate are respectively provided with one preset area; the bottoms of the two preset areas and the bottom of the gallium nitride single crystal substrate have a first preset distance; the tops of the two current blocking structures and the top of the gallium nitride single crystal substrate are positioned on the same plane; the material of the current blocking structure comprises a dielectric material and an ultra-wide band gap material;
providing a supporting substrate;
bonding the top of the gallium nitride monocrystal substrate and the supporting substrate to obtain a first structure;
sequentially carrying out annealing stripping and polishing treatment on the first structure to obtain a second structure; the second structure comprises the support substrate and a first gallium nitride single crystal layer;
sequentially extending a gallium nitride channel layer and an aluminum gallium nitride barrier layer on the first gallium nitride single crystal layer of the second structure to obtain a third structure;
preparing a source electrode and a gate electrode on the top surface of the third structure, and preparing a drain electrode on the bottom surface of the third structure; the top surface of the third structure is close to the AlGaN barrier layer.
2. The method according to claim 1, wherein in the case where the material of the current blocking structure is a dielectric material, the forming of the defect layer in the gallium nitride single crystal substrate, and the preparing of one current blocking structure in each of two preset regions of the gallium nitride single crystal substrate where a preset separation distance exists, comprises:
ion implantation is performed from the implantation surface to the gallium nitride single crystal substrate to form the defect layer in the gallium nitride single crystal substrate;
removing gallium nitride monocrystal portions of the two preset areas of the gallium nitride monocrystal substrate by utilizing photoetching and etching technologies to obtain an etched structure;
growing a dielectric material on the top surface of the etched structure;
removing the dielectric material on the injection surface; the top surface of the etched structure is the top surface of the gallium nitride single crystal substrate;
and polishing the top surface of the etched structure to obtain the gallium nitride single crystal substrate with the two current blocking structures.
3. The method according to claim 1, wherein in the case where the material of the current blocking structure is gallium oxide in ultra wide band gap material, the forming of the defect layer in the gallium nitride single crystal substrate, and the preparing of one current blocking structure in each of two preset regions of the gallium nitride single crystal substrate where a preset separation distance exists, comprises:
oxygen ion implantation is carried out on the two preset areas from the surfaces of the two corresponding preset areas in the top surface of the gallium nitride single crystal substrate so as to respectively form an oxygen ion implantation area in the two preset areas with preset interval distances of the gallium nitride single crystal substrate;
annealing the two oxygen ion implantation areas of the gallium nitride single crystal substrate to obtain a gallium nitride single crystal substrate with two current blocking structures;
ion implantation is performed from the top surface of the gallium nitride single crystal substrate toward the gallium nitride single crystal substrate to form a defect layer within the gallium nitride single crystal substrate.
4. The method of claim 1, wherein the dielectric material comprises silicon dioxide, silicon nitride, and aluminum oxide;
the ultra-wideband material comprises gallium oxide.
5. The method according to claim 3, wherein the conditions for annealing the oxygen ion implantation region include:
the annealing atmosphere is vacuum or nitrogen;
the annealing temperature is 600-1100 ℃;
the annealing time comprises 30 seconds to 10 minutes.
6. The method of claim 1, wherein the conditions for annealing the first structure include:
the annealing atmosphere is vacuum, nitrogen or argon;
the annealing temperature is 300-900 ℃;
the annealing time is 1 minute to 24 hours.
7. The method according to claim 1, wherein the annealing, peeling and polishing the first structure sequentially to obtain a second structure comprises:
stripping the first structure along the defect layer by using an annealing process to obtain an initial second structure; the initial second structure comprises the support substrate and the first gallium nitride single crystal layer;
and removing the residual defect layer on the initial second structure by using a polishing technology to obtain the second structure.
8. The method of claim 1, wherein sequentially epitaxially growing a gallium nitride channel layer and an aluminum gallium nitride barrier layer on the first gallium nitride single crystal layer of the second structure, to obtain a third structure, comprises:
and sequentially extending the gallium nitride channel layer, the aluminum nitride insertion layer, the aluminum gallium nitride barrier layer and the gallium nitride cap layer on the first gallium nitride single crystal layer of the second structure to obtain the third structure.
9. The method of manufacturing according to claim 4, wherein the supporting substrate comprises a stacked highly doped substrate and a lowly doped substrate;
the top of the gallium nitride single crystal substrate is bonded with the low doped substrate.
10. A gallium nitride current aperture vertical electronic device, characterized in that it is produced by the method according to any of the preceding claims 1-9.
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