CN116741826A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN116741826A
CN116741826A CN202210780780.0A CN202210780780A CN116741826A CN 116741826 A CN116741826 A CN 116741826A CN 202210780780 A CN202210780780 A CN 202210780780A CN 116741826 A CN116741826 A CN 116741826A
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layer
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semiconductor device
electrode
impurity concentration
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水上诚
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Abstract

实施方式提供能够抑制元件破坏的半导体装置。根据实施方式，半导体装置具备：第一电极；第二电极；及碳化硅层，在第一方向上设于第一电极与第二电极之间，碳化硅层具有：n型的第一层，与第一电极电连接；n型的第二层，设于第一层上，杂质浓度低于第一层的杂质浓度；超结构造部，设于第二层上；p型的第三层，设于超结构造部上；及n型的第四层，设于第三层上，与第二电极电连接，超结构造部具有：多个n型柱，杂质浓度高于第二层的杂质浓度；多个p型柱，杂质浓度高于第二层的杂质浓度；以及边界区域，在与第一方向正交的第二方向上位于n型柱与p型柱之间，从第二层连续地沿第一方向延伸，杂质浓度低于n型柱以及p型柱的杂质浓度。

Description

半导体装置
相关申请
本申请享受以日本专利申请2022－33237号(申请日：2022年3月4日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的所有内容。
技术领域
实施方式主要涉及半导体装置。
背景技术
作为功率器件，已知有具有被称作超结结构的p型柱与n型柱的周期性排列结构的纵型器件。超结结构通过使p型柱与n型柱所含的杂质量为相同程度，使漂移区域耗尽而保持高耐压，并且通过经由n型柱而流过电流，从而能够实现低导通电阻。另外，使用了碳化硅(SiC)的功率器件的开发也在进行中。对于SiC器件，要求进展与硅器件不同的视点下的开发。
发明内容
实施方式提供能够抑制元件破坏的半导体装置。
根据实施方式，半导体装置具备：第一电极；第二电极；以及碳化硅层，在第一方向上设于所述第一电极与所述第二电极之间，所述碳化硅层具有：n型的第一层，与所述第一电极电连接；n型的第二层，设于所述第一层上，杂质浓度低于所述第一层的杂质浓度；超结构造部，设于所述第二层上；p型的第三层，设于所述超结构造部上；以及n型的第四层，设于所述第三层上，与所述第二电极电连接，所述超结构造部具有：多个n型柱，杂质浓度高于所述第二层的杂质浓度；多个p型柱，杂质浓度高于所述第二层的杂质浓度；以及边界区域，在与所述第一方向正交的第二方向上位于所述n型柱与所述p型柱之间，从所述第二层连续地沿所述第一方向延伸，杂质浓度低于所述n型柱以及所述p型柱的杂质浓度。
附图说明
图1是第一实施方式的半导体装置的示意剖面图。
图2是表示实施方式的超结构造部的杂质浓度分布的示意图。
图3是第二实施方式的半导体装置的示意剖面图。
图4是第三实施方式的半导体装置的示意剖面图。
图5是第四实施方式的半导体装置的示意剖面图。
图6是第五实施方式的半导体装置的示意剖面图。
图7是第六实施方式的半导体装置的示意剖面图。
具体实施方式
以下，参照附图，对实施方式进行说明。另外，在各附图中，对相同的构成标注相同的附图标记。
[第一实施方式]
如图1所示，第一实施方式的半导体装置1具备第一电极51、第二电极52以及碳化硅(SiC)层10。例如第一电极51作为漏极电极发挥功能，第二电极52作为源极电极发挥功能。
将从第一电极51朝向第二电极52的方向设为第一方向d1。碳化硅层10在第一方向d1上设于第一电极51与第二电极52之间。在第一方向d1上将箭头的方向相对设为上，将与箭头相反的一侧的方向相对设为下。
碳化硅层10具有n型的第一层11、n型的第二层12、超结构造部30、p型的第三层13以及n型的第四层14。
第一层11是SiC基板。第一层11的n型杂质浓度例如为1×1020/cm3。在第一层11的下表面设置第一电极51，第一层11与第一电极51电连接。
在第一层11上设有第二层12。第二层12在第一层(SiC基板)11上外延生长。或者，也可以在第一层11上隔着n型的第五层15设置第二层12。第五层15作为外延生长的缓冲层发挥功能。
第二层12的n型杂质浓度比第一层11的n型杂质浓度低。第二层12的n型杂质浓度例如为1×1017/cm3。第五层15的n型杂质浓度比第一层11的n型杂质浓度低，比第二层12的n型杂质浓度高。第五层15的n型杂质浓度例如是1×1018/cm3。
在第二层12上设有超结构造部30。超结构造部30具有多个n型柱31n与多个p型柱31p。n型柱31n与p型柱31p在与第一方向d1正交的第二方向d2上交替地排列。n型柱31n的下端以及p型柱31p的下端与第二层12相接。在第一方向d1上，第二层12与n型柱31n相接、第二层12与p型柱31p相接的n型柱31n以及p型柱31p的平面形状例如形成为沿与第一方向d1以及第二方向d2正交的方向(贯穿纸面的方向)延伸的带状。
n型柱31n的n型杂质浓度比第二层12的n型杂质浓度高。n型柱31n的n型杂质浓度例如是5×1017/cm3。p型柱31p的p型杂质浓度比第二层12的n型杂质浓度高。p型柱31p的p型杂质浓度例如是5×1017/cm3。
n型柱31n的n型杂质浓度与p型柱31p的p型杂质浓度为相同程度。另外，n型柱31n的第二方向d2的宽度与p型柱31p的第二方向d2的宽度大致相同。因而，n型柱31n的n型杂质量与p型柱31p的p型杂质量为相同程度。
超结构造部30还具有多个边界区域32。边界区域32位于在第二方向d2上相邻的n型柱31n与p型柱31p之间，从第二层12连续地沿第一方向d1延伸。边界区域32的平面形状与n型柱31n以及p型柱31p相同，例如形成为沿与第一方向d1以及第二方向d2正交的方向(贯穿纸面的方向)延伸的带状。
边界区域32例如是具有与第二层12相同程度的浓度的n型区域。边界区域32的n型杂质浓度比n型柱31n的n型杂质浓度以及p型柱31p的p型杂质浓度低。边界区域32的n型杂质浓度例如为1×1017/cm3。
如图2所示，在n型柱31n与p型柱31p之间存在低于n型柱31n的n型杂质浓度以及p型柱31p的p型杂质浓度且杂质浓度在宽度方向(第二方向d2)上大致一定的边界区域32。
在超结构造部30上设有多个第三层13。第三层13例如作为p型基底层发挥功能。p型柱31p的上端以及边界区域32的上端与第三层13相接。
在n型柱31n上设有n型的第七层17。第七层17与n型柱31n相接，第七层17位于在第二方向d2上相邻的第三层13之间。
在第三层13上设有第四层14。第四层14例如作为n型源极层发挥功能。第四层14的n型杂质浓度比n型柱31n的n型杂质浓度高。第四层14与第二电极52相接，与第二电极52电连接。
在第三层13上设有p型的第六层16。第六层16的p型杂质浓度比第三层13的p型杂质浓度以及p型柱31p的p型杂质浓度高。第六层16与第二电极52相接。第二电极52的电位经由第六层16被赋予到第三层13以及p型柱31p。
半导体装置1还具备设于碳化硅层10上的栅极电极53。在栅极电极53与碳化硅层10之间以及栅极电极53与第二电极52之间设有绝缘膜41。作为栅极电极53的材料，例如能够使用多晶硅。绝缘膜41例如是硅氧化膜。第三层13中的在第四层14与第七层17之间的区域(沟道区域)13a隔着绝缘膜41而与栅极电极53对置。
在半导体装置1的导通动作时，栅极电极53被赋予阈值以上的电位，在沟道区域13a形成反型层(n型沟道)。然后，电子电流经过第四层14、沟道区域13a、第七层17、n型柱31n、第二层12、第五层15以及第一层11而流过第二电极52与第一电极51之间。
若栅极电极53的电位成为比阈值低的电位，则沟道区域13a的n型沟道被截止，半导体装置1成为断开状态。在该断开状态时，在超结构造部30中，耗尽层从n型柱31n与p型柱31p的边界区域32沿横向(第二方向d2)扩展，半导体装置1的耐压得以保持。
另外，由于在第一层11与超结构造部30之间设有n型杂质浓度低于第一层11的第二层12，因此在断开状态时，耗尽层容易从p型柱31p的下端与第二层12的边界扩展。这也会提高半导体装置1的耐压。
在SiC结晶中，与Si结晶相比，容易产生横穿n型柱与p型柱的边界那样的缺陷100。n型柱与p型柱的边界是杂质浓度分布可变得陡峭的部分，若缺陷100横穿该边界，则耗尽层扩展时容易对边界的缺陷施加较强的电场，可成为破坏的原因。
根据本实施方式，通过在n型柱31n与p型柱31p之间设置比n型柱31n的n型杂质浓度以及p型柱31p的p型杂质浓度低且杂质浓度在宽度方向(第二方向d2)上为大致一定的边界区域32，从而即使存在横穿超结构造部30那样的缺陷100，也能够缓和对边界区域32的缺陷施加的电场，能够提高半导体装置1对于高电压的可靠性。
超结构造部30能够通过在第一方向d1上反复进行多次离子注入来形成。在第一层(SiC基板)11上外延生长第二层12之后，向第二层12的表面上的预定形成p型柱31p的区域注入p型杂质。作为p型杂质，例如能够使用Al、B、Ga。之后，向第二层12的表面上的预定形成n型柱31n的区域注入n型杂质。作为n型杂质，例如能够使用N、P。另外，也可以在注入n型杂质之后注入p型杂质。
在上述第一次的杂质注入之后，在杂质注入区域上外延生长一部分成为边界区域32的层(例如与第二层12相同程度的n型杂质浓度的n型层)。在该外延生长层中，与上述第一次相同地进行第二次杂质注入。之后，将在杂质注入区域上外延生长一部分成为边界区域32的层的工序和向外延生长层注入杂质的工序反复进行规定次数。之后，例如以1900℃左右的温度进行热处理，从而使注入的杂质扩散，形成n型柱31n与p型柱31p。
SiC中的杂质相比于Si中的杂质更难以热扩散，在n型柱31n与p型柱31p之间保持上述外延生长层的一部分即边界区域32。边界区域32从第二层12连续地沿第一方向延伸。
由于杂质注入位置的位置偏移，可能产生一部分的n型柱31n与一部分的p型柱31p相接的部分。例如即使在某一部分处p型杂质的注入位置在图1的第二方向d2上向左侧偏移，p型柱31p的左侧面的一部分与左侧相邻的n型柱31n的右侧面相接，该p型柱31p的右侧面与右侧相邻的n型柱31n的间隔也会相应地扩大p型柱31p偏向左侧的量。
即，不会p型柱31p的第二方向d2上的两侧面都与n型柱31n相接，p型柱31p的第二方向d2上的两侧面中的至少一个侧面不具有与n型柱31n相接的部分。同样，不会n型柱31n的第二方向d2上的两侧面都与p型柱31p相接，n型柱31n的第二方向d2上的两侧面中的至少一个侧面不具有与p型柱31p相接的部分。即使产生了n型柱31n与p型柱31p相接的部分，其数量也少，而且不会集中在特定部位。
以下，对其他实施方式进行说明。在其他实施方式中，超结构造部30的构成也与第一实施方式相同，可获得相同的效果。
[第二实施方式]
如图3所示，第二实施方式的半导体装置2具有沟槽栅构造的栅极电极53。
在p型柱31p上设有p型的第八层18。在n型柱31n上以及第八层18上设有n型的第七层17。p型柱31p的上端与第八层18相接。n型柱31n的上端与第七层17相接。在第七层17上设有第三层13。
栅极电极53隔着绝缘膜41设于贯通第四层14、第三层13以及第七层17而到达第八层18的沟槽内。在栅极电极53与第二电极52之间设有绝缘膜42。
在导通动作时，在第三层13中的隔着绝缘膜41与栅极电极53对置的沟道区域13a形成反型层(n型沟道)。电子电流经由沟道区域13a以及第七层17流过第四层14与n型柱31n之间。
[第三实施方式]
如图4所示，在第三实施方式的半导体装置3中，n型柱31n的上端、p型柱31p的上端以及边界区域32的上端与设于超结构造部30的第三层13相接。
栅极电极53在p型柱31p的上方隔着绝缘膜41设于贯通第四层14而到达第三层13的中途的深度的沟槽内。在导通动作时，在第三层13中的隔着绝缘膜41与栅极电极53对置的沟道区域13a中形成反型层(n型沟道)，电子电流经由沟道区域13a流过第四层14与n型柱31n之间。
[第四实施方式]
如图5所示，在第四实施方式的半导体装置4中，n型柱31n的上端、p型柱31p的上端以及边界区域32的上端与设于超结构造部30的第三层13相接。
栅极电极53隔着绝缘膜41设于贯通第四层14以及第三层13而到达n型柱31n的沟槽内。在导通动作时，在第三层13中的隔着绝缘膜41与栅极电极53对置的沟道区域13a中形成反型层(n型沟道)，电子电流经由沟道区域13a流过第四层14与n型柱31n之间。
[第五实施方式]
如图6所示，在第五实施方式的半导体装置5中，在n型柱31n上设有p型的第九层19。而且，在n型柱31n上以覆盖第九层19的方式设有n型的第十一层22。n型柱31n的上端与第九层19以及第十一层22相接。在p型柱31p上设有p型的第十层21。p型柱31p的上端与第十层21相接。在第十层21上以及第十一层22上设有第三层13。
栅极电极53隔着绝缘膜41设于贯通第四层14、第三层13以及第十一层22而到达第九层19的沟槽内。在导通动作时，在第三层13中的隔着绝缘膜41与栅极电极53对置的沟道区域13a中形成反型层(n型沟道)，电子电流经由沟道区域13a以及第十一层22流过第四层14与n型柱31n之间。
[第六实施方式]
如图7所示，在第六实施方式的半导体装置6中，在超结构造部30与第三层13之间设有n型的第七层17、p型的第八层18以及p型的第十层21。
例如在上方设有第十层21的p型柱31p与在上方设有第八层18的p型柱31p在第二方向d2上交替地排列。第十层21与p型柱31p的上端以及第三层13的下表面相接。第七层17设于n型柱31n上，还覆盖第八层18。
栅极电极53隔着绝缘膜41设于贯通第四层14、第三层13、以及第八层18上的第七层17而到达第八层18的沟槽内。在导通动作时，在第三层13中的隔着绝缘膜41与栅极电极53对置的沟道区域13a中形成反型层(n型沟道)，电子电流经由沟道区域13a以及第七层17而流过第四层14与n型柱31n之间。
虽然说明了本发明的几个实施方式，但这些实施方式是作为例子而提出的，并不意图限定发明的范围。这些新的实施方式能够以其他各种方式实施，在不脱离发明的主旨的范围内能够进行各种省略、替换、变更。这些实施方式及其变形包含在发明的范围、主旨中，并且包含在权利要求书所记载的发明及其等价的范围中。

Claims (15)

1.一种半导体装置，具备：
第一电极；
第二电极；以及
碳化硅层，在第一方向上设于所述第一电极与所述第二电极之间，
所述碳化硅层具有：
n型的第一层，与所述第一电极电连接；
n型的第二层，设于所述第一层上，杂质浓度低于所述第一层的杂质浓度；
超结构造部，设于所述第二层上；
p型的第三层，设于所述超结构造部上；以及
n型的第四层，设于所述第三层上，与所述第二电极电连接，
所述超结构造部具有：
多个n型柱，杂质浓度高于所述第二层的杂质浓度；
多个p型柱，杂质浓度高于所述第二层的杂质浓度；以及
边界区域，在与所述第一方向正交的第二方向上位于所述n型柱与所述p型柱之间，从所述第二层连续地沿所述第一方向延伸，杂质浓度低于所述n型柱以及所述p型柱的杂质浓度。
2.根据权利要求1所述的半导体装置，
所述边界区域为n型。
3.根据权利要求1所述的半导体装置，
所述边界区域的上端与所述第三层相接。
4.根据权利要求1所述的半导体装置，
所述n型柱的所述第二方向上的两侧面中的至少一个侧面不具有与所述p型柱相接的部分。
5.根据权利要求1所述的半导体装置，
所述p型柱的所述第二方向上的两侧面中的至少一个侧面不具有与所述n型柱相接的部分。
6.根据权利要求1所述的半导体装置，
所述碳化硅层还具有n型的第五层，该n型的第五层设于所述第一层与所述第二层之间，具有低于所述第一层且高于所述第二层的杂质浓度。
7.根据权利要求1所述的半导体装置，
所述第四层的n型杂质浓度高于所述n型柱的n型杂质浓度。
8.根据权利要求1所述的半导体装置，
在所述第一方向上，所述第二层与所述n型柱相接，所述第二层与所述p型柱相接。
9.根据权利要求1所述的半导体装置，
还具备设于所述碳化硅层上的栅极电极，
所述第三层具有隔着绝缘膜而与所述栅极电极对置的沟道区域。
10.根据权利要求1所述的半导体装置，
还具备从所述碳化硅层的上表面到达所述第三层的栅极电极，
所述第三层具有隔着绝缘膜而与所述栅极电极对置的沟道区域。
11.根据权利要求10所述的半导体装置，
所述栅极电极位于所述p型柱的上方。
12.根据权利要求1所述的半导体装置，
还具备从所述碳化硅层的上表面起贯通所述第三层的栅极电极，
所述第三层具有隔着绝缘膜而与所述栅极电极对置的沟道区域。
13.根据权利要求12所述的半导体装置，所述栅极电极位于所述p型柱的上方。
14.根据权利要求12所述的半导体装置，所述栅极电极位于所述n型柱的上方。
15.根据权利要求12所述的半导体装置，所述栅极电极到达所述n型柱。
CN202210780780.0A 2022-03-04 2022-07-04 半导体装置 Pending CN116741826A (zh)

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