CN116685854A - Method and device for checking time delay parameters - Google Patents

Abstract

A method and a device for checking time delay parameters, the method comprises the following steps: acquiring a first group of parameters and a second group of parameters, wherein the first group of parameters comprise time delay parameters of a message transmitted in at least one module of a Register Transfer Level (RTL) circuit, and the second group of parameters comprise time delay parameters of at least one module counted when the message is transmitted in an Electronic System Level (ESL) model design; if the first group of parameters are not matched with the second group of parameters, determining that errors exist in the second group of parameters, calibrating the second group of parameters to obtain a third group of parameters, and utilizing the third group of parameters to evaluate the message transmission delay, so that errors caused by sampling RTL delay parameters by a developer can be avoided.

Description

Method and device for checking time delay parameters Technical Field

The application relates to the field of chip testing, in particular to a method and a device for testing delay parameters of an ESL model.

Background

The transmission delay of the message in the switch is a key index for testing the performance of the switch, namely, along with the rapid development of communication service, the delay performance index of the switch chip is also more and more important. For switch chips, large-scale and high-complexity chip designs are ubiquitous, and chip designers need to evaluate and master chip delay performance metrics at any time during the chip development process. In this process, once the delay performance index of the chip does not meet the chip design specification, the chip designer needs to adjust the chip architecture as soon as possible, so as to ensure that the delay performance index of the chip meets the design specification, thereby ensuring the competitiveness of the chip in the final chip feeding process.

For a switch chip designer, the method for evaluating the message transmission delay in the chip development process comprises the following two steps: one is evaluated by means of electronic design automation (Electronics Design Automation, EDA) verification; the other is evaluated by means of an electronic system level design (Electronic System Level, ESL) chip model. For large-scale and high-complexity switch chip designs, a typical chip designer uses an ESL chip model to replace the real register transfer hierarchy (Register Transfer Level, RTL) for latency evaluation.

The ESL model models the chip by using C/C++ high-level language, the code complexity and the scale are far smaller than those of RTL codes, and further, the chip performance evaluation work including time delay evaluation can be efficiently supported. However, the ESL model is just a model and is not equivalent to RTL code; in order to ensure the time delay precision of the ESL model evaluation, all parameters related to the time delay in the RTL circuit need to be reversely marked into the ESL chip model, so that the accuracy and the effectiveness of the time delay performance index of the ESL chip model evaluation can be ensured.

Currently, the implementation means of reversely marking the delay parameter in the RTL circuit to the ESL chip model is that the delay parameter sampling is carried out on the RTL circuit by depending on chip designers. For example, a code developer obtains a delay parameter in an RTL circuit by reading an RTL code, and because different developers understand the difference of the RTL code or understand the RTL code, factors such as omission and the like can cause a larger error of the obtained RTL delay parameter, the accuracy is not high when the delay parameter in the RTL circuit is reversely marked to an ESL chip model. In the actual project test, the error of the message transmission delay data estimated by the ESL model after the inverse standard delay parameter in the above way can reach 1 microsecond (mu s), but the requirement of the industry on the overall delay performance index of the switch is not more than 0.4 mu s, so the requirements of high precision and low delay are still not met.

Disclosure of Invention

The application provides a method and a device for checking delay parameters, which are used for detecting whether the obtained delay parameters of an ESL circuit are accurate or not and improving the accuracy of evaluating the message transmission delay by using an ESL model. Specifically, the application discloses the following technical scheme:

in a first aspect, the present application provides a method for verifying a delay parameter, where the method is applicable to a network device, and the network device may be a server or a functional module integrated on the server, and the method includes:

acquiring a first set of parameters and acquiring a second set of parameters, wherein the first set of parameters comprise delay parameters of message transmission in at least one module of a Register Transfer Level (RTL) circuit; the second group of parameters comprise time delay parameters of the at least one module counted when the message is transmitted by the ESL model designed at the electronic system level;

and if the first group of parameters are not matched with the second group of parameters, determining that the second group of parameters have errors, calibrating the second group of parameters to obtain a third group of parameters, and utilizing the third group of parameters to evaluate the message transmission delay.

According to the method, when the error exists in the delay parameter of the ESL model, the delay parameter of the ESL model is calibrated, and the message delay evaluation is performed by using the calibrated parameter, so that the error caused by sampling of the RTL delay parameter by a developer is avoided.

In addition, the method also splits the end-to-end delay data into a plurality of small-granularity delay indexes, namely transmission delay parameters corresponding to each module, and evaluates the delay data in each small-granularity delay parameter index, so that the evaluation result is finer and more accurate.

With reference to the first aspect, in a possible implementation manner of the first aspect, the at least one module includes a first module, and the acquiring a first set of parameters includes: and acquiring the time difference between the time point of the message reaching the input interface of the first module and the time point of the message reaching the output interface.

With reference to the first aspect, in another possible implementation manner of the first aspect, before the acquiring the first set of parameters, the method further includes: judging whether the data transmitted by the message in the RTL circuit chip is real data or not, and if so, acquiring the first group of parameters.

With reference to the first aspect, in a further possible implementation manner of the first aspect, determining whether data transmitted by the message in the RTL circuit chip is real data includes: judging whether the indication mark carried by the message initial part of the message is 1.

With reference to the first aspect, in still another possible implementation manner of the first aspect, when the packet is a first packet set, where the first packet set includes N packets with different lengths, N is greater than or equal to 2, and N is a positive integer, the acquiring the first set of parameters includes: and acquiring a weighted average value of the delay parameters transmitted by the N messages in the same module. In the implementation manner, the weighted average of the N messages is calculated as the RTL circuit delay parameter, and compared with the method for obtaining the first group of parameters through a single message, the method has higher precision.

With reference to the first aspect, in a further possible implementation manner of the first aspect, the acquiring a first set of parameters includes: and acquiring the first group of parameters from a chip delay accuracy verification table (CLAT), wherein the CLAT comprises delay parameters transmitted by each module in the at least one module.

With reference to the first aspect, in a further possible implementation manner of the first aspect, the acquiring a second set of parameters includes: and acquiring the time delay parameter of the message transmitted by at least one module in the ESL model based on ESL modeling and ESL simulation technology.

In a second aspect, the present application also provides a device for checking a delay parameter, the device comprising:

The system comprises an acquisition unit, a Register Transfer Level (RTL) circuit and a storage unit, wherein the acquisition unit is used for acquiring a first group of parameters and a second group of parameters, the first group of parameters comprise delay parameters of a message transmitted in at least one module of the RTL circuit, and the second group of parameters comprise delay parameters of the at least one module counted when the message is transmitted in an ESL (electronic system level) model;

and the processing unit is used for checking that errors exist in the second group of parameters when the first group of parameters are not matched with the second group of parameters, calibrating the second group of parameters to obtain a third group of parameters, and utilizing the third group of parameters to evaluate the message transmission delay.

With reference to the second aspect, in a possible implementation manner of the second aspect, the at least one module includes a first module, and the obtaining unit is further configured to obtain a time difference between a time point when the packet reaches an input interface and a time point when the packet reaches an output interface of the first module.

With reference to the second aspect, in another possible implementation manner of the second aspect, the processing unit is further configured to determine, before the acquiring unit acquires the first set of parameters, whether data transmitted by the message in the RTL circuit chip is real data, and if so, acquire the first set of parameters.

Further, the processing unit is further configured to determine that the data is real data when an indication mark carried by a message start portion of the message is "1".

With reference to the second aspect, in another possible implementation manner of the second aspect, when the packet is a first packet set, the first packet set includes N packets with different lengths, N is greater than or equal to 2, and N is a positive integer, and the obtaining unit is further configured to obtain a weighted average of delay parameters of transmission of the N packets in the same module.

With reference to the second aspect, in a further possible implementation manner of the second aspect, the apparatus further includes a storage unit, where the storage unit is configured to store a chip delay precision verification table CLAT, where the CLAT table includes a delay parameter transmitted by each module of the at least one module; the acquiring unit is further configured to acquire the first set of parameters from the CLAT of the storage unit.

With reference to the second aspect, in a further possible implementation manner of the second aspect, the obtaining unit is further configured to obtain a delay parameter of transmission of the packet in at least one module in the ESL model based on ESL modeling and ESL simulation technologies.

In a third aspect, the present application also provides a detection apparatus comprising at least one processor and interface circuitry, wherein the interface circuitry is to provide instructions and/or data to the at least one processor; the at least one processor is configured to execute the instructions to implement the method in the foregoing first aspect and various implementations of the first aspect.

In addition, the device further comprises a memory, wherein the memory is used for storing the instructions and/or data.

In the alternative, the at least one processor and the interface circuit may be integrated in one processing chip or chip circuit.

Optionally, the detecting device is a network device, and the network device includes, but is not limited to, a server and a controller.

In a fourth aspect, the application also provides a computer readable storage medium having instructions stored therein such that when the instructions are run on a computer or processor, they can be used to perform the method of the foregoing first aspect and various implementations of the first aspect.

In addition, the present application also provides a computer program product comprising computer instructions which, when executed by a computer or processor, implement the method of the foregoing first aspect and various implementations of the first aspect.

In a fifth aspect, the present application further provides a server, including the apparatus in the foregoing second aspect and the various implementation manners of the second aspect, or including the apparatus in the foregoing third aspect, configured to implement the foregoing first aspect and the method in the various implementation manners of the first aspect.

It should be noted that, the beneficial effects corresponding to the technical solutions of the foregoing second aspect to the various implementation manners of the fifth aspect are the same as the beneficial effects of the foregoing first aspect and the various implementation manners of the first aspect, and detailed descriptions of the beneficial effects of the foregoing first aspect and the various implementation manners of the first aspect are omitted.

Drawings

Fig. 1 is a schematic diagram of a wireless communication system according to an embodiment of the present application;

FIG. 2 is a schematic diagram of an RTL circuit chip model according to an embodiment of the present application;

fig. 3 is a flowchart of a method for checking a delay parameter according to an embodiment of the present application;

fig. 4 is a flowchart of another method for checking delay parameters according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a verification device for time delay parameters according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a detection device according to an embodiment of the present application.

Detailed Description

In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the following description refers to the technical solutions in the embodiments of the present application with reference to the accompanying drawings. Before the technical scheme of the embodiment of the application is described, firstly, an application scene of the technical scheme of the application is described.

The technical scheme of the application can be applied to a detection device which can be used for evaluating the transmission delay of the chip in the chip test stage of the switch or the router. The detection device is integrated as a functional module, such as an android application package (Android application package, APK), in a third party device, including but not limited to a server, a controller, and other network devices.

The switch or router is a device in a wireless communication system, for example, in a wireless local area network (Wireless Local Area Network, WLAN), as shown in fig. 1, and includes at least one server, a switch, a base station (Node B or eNB), a terminal device, and the like. The terminal device includes a User Equipment (UE), a smart phone, a smart screen Television (TV), a notebook computer, a tablet computer, a personal computer (personal computer, PC), a personal digital assistant (personal digital assistant, PDA), a foldable terminal, a wearable device (e.g., a smart watch or a bracelet) having a wireless communication function, and the like.

In addition, the switch or the router can be applied to other communication systems, such as a wired transmission system, and the chip structure and composition of the switch or the router are not limited in this embodiment.

The terminology that may be used in the chip testing process is presented below.

(1) Electronic system level design (Electronic System Level, ESL), which is a design method of a chip simulator, common simulators have functions simulation, performance simulation, instruction simulation, and the industry also has many design platforms and tools of simulators, such as: coware, carbon, mentor, etc. ESL is a set of methodologies that enable development, optimization, and verification of complex system on chip (SoC) architecture and embedded software in a tightly coupled manner that can provide the verification basis for downstream Register Transfer Level (RTL) implementations. In addition, ESL utilizes high-level languages such as C/C++ to simulate hardware behaviors through a software model, provides various levels of software simulation platforms for SoC systems, provides an operable verification environment for SoC system architecture verification and embedded software development, and effectively supports iterative development of the SoC systems.

(2) Register transfer hierarchy (Register Transfer Level, RTL), which may also be referred to as a "register transfer stage". In integrated circuit design, RTL is used to describe the level of abstraction of synchronous digital circuit operation.

(3) Electronic design automation (Electronics Design Automation, EDA), the EDA technology is to use a computer as a tool, and a designer fuses the latest achievements of electronic technology, computer technology, information processing and intelligent technology on an EDA software platform to perform automatic design of electronic products. The advent of EDA technology has greatly improved the efficiency and operability of circuit designs.

(4) LIFO and FIFO. Depending on the message forwarding characteristics, the following message forwarding delay types may be included:

first-in first-out (last bit in first bit out, LIFO) and last-in first-out (first bit in first bit out, FIFO) are two methods of measuring transmission delay. The FIFO method refers to the time interval between the last bit (bit) of a frame entering a switch port and the first bit of a frame being forwarded from said switch port. The time interval is the time required for the exchanger to search the table entry, schedule buffer and forward after the exchanger receives the message completely.

The FIFO method refers to the time interval between the first bit of a frame entering the device port and the first bit of a frame being forwarded from the device port. In a cut-through mode, the message is forwarded as soon as the message header reaches the switch, and the message is not buffered.

The following describes the technical scheme of the application in detail.

The embodiment of the application provides a method for checking time delay parameters, which is used for improving the accuracy of ESL chip model sampling parameters, and comprises three stages, namely: a sampling phase, a comparison phase and a calibration phase. The implementation of these three phases is described below.

1. Sampling phase

In this embodiment, the execution body is exemplified by a detection device, and in the "first and sampling phases", the detection device needs to obtain two sets of parameters, the first set of parameters is the delay parameter of the RTL circuit, and the second set of parameters is the delay parameter obtained by using the ESL model. First, a procedure for obtaining a first set of parameters, i.e. the RTL circuit delay parameters, is described.

Referring to fig. 2, a schematic diagram of an RTL circuit chip model is provided in this embodiment, in which a number of complex circuit structures are simplified into blocks. In this embodiment, the circuit structure of each module is not limited, and the RTL circuit chip shown in fig. 2 includes 3 blocks, which are respectively labeled as block 0, block 1, and block 2, where "0", "1", and "2" are identifiers of blocks, and the identifiers of each block are different. In addition, other more or fewer modules may be included in the circuit chip, which is not limited in this embodiment.

In the RTL circuit chip model, each block comprises at least one input interface and at least one output interface, for example, the input interface of the block 0 is set as a, and the output interface is set as b; the input interface of the block 1 is b, and the output interface is c; the input interface of the block 2 is c, the output interface is d, and the delay (latency) of the transmission of the message or the data in each block is conveniently recorded by marking the input/output interface of each block. Specifically, when the first message is transmitted through any block, the transmission delay in the block may be characterized as: the time difference Δt between the time point of the message header of the first message reaching the input interface of the block and the time point of the message header of the first message reaching the output interface is: transmission delay = point in time when the output interface is reached-point in time when the input interface is reached.

Referring to fig. 3, the method for obtaining the delay parameter of the RTL circuit includes:

step 101: a first set of parameters is obtained, the first set of parameters including delay parameters for transmission of at least one message in at least one module of the RTL circuit.

Specifically, when the delay parameter of the RTL circuit is sampled, it is first required to determine whether the transmission of (one or more) messages in the RTL circuit chip satisfies a preset condition, and when the preset condition is satisfied, the delay parameter of at least one block counted during the current message transmission is obtained. If the preset condition is not met, the sampling fails and resampling is needed.

Wherein the judging whether the preset condition is satisfied comprises: and detecting whether the received message data is real data. If yes, determining that the message transmission meets the preset condition; if the judgment result is NO, the preset condition is not met. For example, if the received message is a first message, determining whether an indicator carried in a start-of-packet (sop) of the first message is "1"; if the data is '1', determining that the data transmitted in the first message is true data, namely meeting the preset condition; if the sop indicator flag is "0", then no real data is transmitted, i.e. the preset condition is not met.

In addition, the detection device also acquires the first signal at the same time when receiving the first message. Wherein the signal flag (flag) of the first signal is valid, e.g. indicated as "1" in the signal flag of the first signal. Wherein the first signal and/or the first message may be transmitted on an interface bus and may pass through at least one block during transmission.

In the logic of the chip circuit, in order to represent that a real message is transmitted through the chip interface, the chip circuit typically transmits a valid signal of 1bit (bit) on the interface bus, so as to detect whether there is valid message transmission at the current moment, which may be called as a valid signal flag. If the content carried in the preset field in the signal is 1, the signal is valid, and the data on the interface bus is valid data; if the signal flag indicates that the content is "0", it indicates that the signal is invalid, i.e. no data packet from the RTL circuit chip is received, and thus the first set of parameters cannot be obtained.

In addition, the determining whether the data transmitted in the first packet is real data may be determined by a sop indicator, and since the interface bus is limited by a bit width (bus-width), it is required to cut a longer length packet into a plurality of bus-width units when transmitted, where each bus-width unit may also be referred to as a packet slicing unit, and each packet slicing unit is used to transmit real and valid data. In the "sampling phase", the statistical delay is followed by the FIFO method, and only the time of the beginning part fragment (sop mark) of the message is acquired.

For example, taking block 0 as an example, the transmission delay of the first message passing through block 0 may be represented as latency_ab, the sampling Point of the input interface a may be represented by start Point, the sampling Point of the output interface b is represented by end Point, and Δt (latency_ab) =t (end Point) -t (start Point). Similarly, the transmission delay of the first message in block 1 is latency_bc, and the transmission delay in block 2 is latency_cd.

Optionally, the delay parameter of each block in the RTL circuit chip model is represented by a "chip delay accuracy verification table" (Chip Latency Accuracy Verification Table, abbreviated as CLAT table) as shown in table 1 below.

TABLE 1 CLAT TABLE

In table 1, block represents a module, and latex name is a transmission delay name, which has uniqueness within the same module. The start point is the starting position of a transmission delay sampling point and can be used for valid signal marking of a chip interface bus; the end point is the end position of the transmission delay sampling point and can be used for valid signal marking of the chip interface bus.

It should be appreciated that the above-described CLAT table may be preconfigured and stored in the detection means. In addition, it should be noted that the parameters in the CLAT table may be set freely by the chip developer, i.e. it is determined which delay parameters need to be collected and compared, and the setting process of the parameters in this embodiment is not limited.

In the 'one sampling stage', the detection device utilizes the interface signal monitoring function provided by EDA technology to add the input/output interface signal of each block into the EDA verification environment, sends a first message to the input interface of block 0 in the RTL circuit chip at the beginning, and then samples the timestamp of the sampling point position of the first message transmitted in each block in the EDA verification environment.

Specifically, in the step 101, for the block 0, a delay parameter Δt (latency_ab, inter-ab interface delay) of the block 0 as the first group parameter is obtained by using each block as a unit; for the module block 1, acquiring a time delay parameter delta t (latency_bc, bc inter-interface time delay) of the first group of parameters which are the block 1; the module block 2 acquires a time delay parameter delta t (latency_cd, cd inter-interface time delay) of the first group of parameters which are the block 2; for the chip circuit modules consisting of the modules block 0, block 1 and block 2, the obtained first set of parameters includes delay parameters Δt (latency_ab), Δt (latency_bc) and Δt (latency_cd).

Optionally, in order to improve the accuracy of sampling, the first set of parameters may also be a weighted average of delay parameters of N packets transmitted in the same module, where N is a positive integer and N is greater than or equal to 2. For example, in a message sampling manner, the chip circuit transmits a first message set to the interface bus, where the first message set includes N messages with standard lengths, for example, n=5, and the standard lengths of the 5 messages are respectively: 64Byte, 256Byte, 1518Byte, 4096Byte, 9600Byte, etc. Sampling data (i.e., transmitted delay parameters) is obtained in the RTL circuit model for each length of message, and then the set of data is averaged to obtain a corresponding first set of parameters.

For example, taking block 0 as an example, transmitting each message in the first message set to block 0 respectively, and under the condition that the preset condition is met, acquiring a time stamp of an input/output interface of each message in block 0, and then calculating a time delay parameter of each message in block 0, wherein the time delay parameter corresponds to 5 messages 64B, 256B, 1518B, 4096B and 9600B of the first message set, and 5 time delay parameters are respectively Δt1, Δt2, Δt3, Δt4 and Δt5; a weighted average (Δtmann) from Δt1 to Δt5 is calculated, resulting in a Δtmann for the first set of parameters for block 0. Similarly, for block 1 and block 2, the first set of parameters for each block is calculated and also obtained using the same weighted average method. For an RTL circuit chip model containing 3 blocks, the first set of parameters obtained includes 3 Δtays. Such as Δt0 average, Δt1 average, Δt2 average, correspond to block 0, block 1, and block 2, respectively.

According to the method, a standard circuit delay parameter sampling method is defined by multiplexing EDA verification monitor (an interface signal monitoring function provided by EDA technology): the valid signal and the sop signal of the input/output interface of each block are added into an EDA verification environment, one or more messages are input at the input interface of the module at the beginning of the chip, sampling is carried out according to the valid signal and the sop signal change on the input interface in the EDA verification environment, and the time stamp of the message at the corresponding input/output interface is obtained, so that the RTL circuit delay parameter of each block can be accurately counted, and a basis is provided for the subsequent parameter comparison stage.

Step 102: a second set of parameters is obtained using the ESL model, the second set of parameters including delay parameters of at least one module of ESL model statistics.

The second set of parameters is similar to the above step 101, and the transmission delay of a message in each block in the ESL model is obtained by using each block as a unit, or a weighted average of delays of multiple messages with different lengths transmitted in the same block is obtained.

It should be understood that the first message or the first message set {64Byte, 256B, 1518B, 4096B, 9600B } transmitted in the second set of parameters is the same as the message transmitted by the interface bus in the RTL circuit chip model, and the process of acquiring the transmission delay parameter of the ESL model in this embodiment is not described in detail.

Alternatively, the first set of parameters and the second set of parameters may be recorded in the CLAT table, and the statistics obtained are shown in table 2. And, optionally, the method further comprises: the above table 2 is stored in the storage unit of the detection device.

TABLE 2 CLAT TABLE

In one example, referring to Table 2, the calculated first and second sets of parameters for block 0 are 10 and 10, with units being (μs); the first and second sets of parameters for block 1 are 8 and 8; the first and second sets of parameters for block 2 are 12 and 10.

2. Comparison stage

103: and judging whether the first group of parameters and the second group of parameters are matched, namely judging whether the delay parameters of the RTL circuit are identical to the delay parameters counted by the ESL model.

Specifically, each block is used as a unit to perform comparison, if the first set of parameters is a delay Δt (latency_ab) of a first message transmitted through the block 0, the second set of parameters is a transmission delay Δt' (latency_ab) of the block 0 acquired by the first message in the ESL model, for example. Whether Δt (latency_ab) and Δt' (latency_ab) are the same or whether the difference between the two is within an allowable range is compared.

Similarly, if the detected RTL circuit module includes 3 blocks, comparing whether the first set of parameters and the second set of parameters corresponding to each block are the same or whether the delay difference of each set of parameters is within the allowable range.

104: if not, i.e. the first set of parameters and the second set of parameters do not match or are not identical, it is determined that there is an error in the second set of parameters (delay parameters counted by the ESL model).

105: if so, i.e., the first set of parameters and the second set of parameters match or are the same, it is determined that there is no error in the second set of parameters. Then, the detection device utilizes the second group of parameters to evaluate the message transmission delay, namely utilizes the delay parameters counted by the ESL model to evaluate the chip transmission delay performance index, and an accurate evaluation result can be obtained.

For example, of the two sets of parameters counted in table 2, for block 0, the first set of parameters Δt (latency_ab) =10, the second set of parameters Δt ' (latency_ab) =10, i.e., Δt (latency_ab) =Δt ' (latency_ab), and the second set of parameters Δt ' (latency_ab) are determined to be sampled accurately.

Similarly, for block 1, the first set of parameters Δt (latency_bc) =8, the second set of parameters Δt ' (latency_bc) =8, i.e., Δt (latency_bc) =Δt ' (latency_bc), then the second set of parameters Δt ' (latency_ab) is determined to be sampled accurately. For block 2, the first set of parameters Δt (latency_cd) =12, the second set of parameters Δt ' (latency_cd) =10, i.e. Δt (latency_cd) > Δt ' (latency_cd), and then the second set of parameters Δt ' (latency_cd) are determined to be inaccurate in sampling values.

In addition, for an ESL circuit model that includes 3 blocks entirely, if one or more of the 3 blocks have "no match," the sampling results for determining the second set of parameters are inaccurate for the entire ESL circuit. In other words, the sampling result of the entire (overlap) ESL circuit model is accurate only if the sampling result of all block comparisons is "accurate".

It should be noted that, in the data counted in table 1 or table 2, the tester wants to detect the transmission delay of which module, calls the timestamp corresponding to the input/output interface of the module, and further calculates the first set of parameters and the second set of parameters.

3. Calibration phase

When it is determined in the step 103 that the second set of parameters have errors, the method further includes, after the step 104:

106: and calibrating the second group of parameters to obtain a third group of parameters, and utilizing the third group of parameters to evaluate the message transmission delay.

One possible implementation is to take the first set of parameters as input for calibrating the ESL model parameters, correct the delay parameters (i.e. the second set of parameters) of the ESL model statistics, and obtain the third set of parameters. Wherein the third set of parameters matches the first set of parameters.

According to the method, when the error exists in the sampled delay parameters of the ESL model, the delay parameters of the ESL model are calibrated, and the message delay evaluation is performed by using the calibrated parameters, so that the error caused by the sampling of the RTL delay parameters by a developer is avoided.

Alternatively, the flow of the method of this embodiment may be illustrated by fig. 4, and referring to fig. 4, the method includes 3 partial flows, and the (1) th part is "time delay parameter collection", and the flow is a preparation stage of the method. Specifically, in the "delay parameter collection" process of part (1), the relevant functions are implemented by developing an own delay evaluation form, such as a CLAT table. Through the CLAT form, the chip developer confirms the relevant delay parameter content and marks the names of the input interface and the output interface of each block in the RTL circuit.

Part (2) is a "delay parameter sampling" flow, corresponding to the "one, sampling phase" of the foregoing embodiment, and in the "delay parameter sampling" process of part (2), the delay parameter sampling includes: RTL circuit delay parameter samples (first set of parameters) and ESL model delay parameter samples (second set of parameters).

The sampling of the RTL circuit delay parameter can be determined by recording a start position (start point) and an end position (end point) of an interface sampling point of each block in a CLAT form, and adding a signal of each interface sampling point into an EDA verification environment monitor component to obtain the RTL circuit delay parameter. For example, the RTL circuit transmission delay Δt (latency) =t (end point) -t (start point) of any block. In addition, the delay parameter of the ESL model is recorded by the information of the interface signal in the CLAT table, for example, the corresponding interface modeling characteristic is found in the ESL model, and the delay parameter data of any block in the ESL model is obtained based on the ESL modeling and ESL simulation technology.

Part (3) is "delay parameter comparison and calibration", and the process corresponds to the "second, comparison phase" and the "third, calibration phase" of the foregoing embodiment. In the process of comparing and calibrating the delay parameters in the part (3), comparing the specific numerical values of the delay parameters of the RTL circuit and the delay parameters of the ESL model based on the CLAT table, and if the two groups of parameters are the same or matched, indicating that the delay parameters of the ESL model are accurate; otherwise, determining the delay parameter of the ESL model is inaccurate.

Further, if the comparison determines that the delay parameters counted by the ESL model are inaccurate, the delay parameters of the ESL model are calibrated. For example, taking the RTL circuit delay parameter as the input of the calibration ESL model, correcting the ESL model delay parameter to obtain a corrected delay parameter, and then using the corrected delay parameter to evaluate the message transmission delay.

It should be noted that if the RTL circuit delay parameter is used to evaluate the message transmission delay, it cannot be realized for a large-scale chip with complex service, because the implementation cost and the cost are very high, so in order to measure the delay in the large-scale chip and avoid the high cost caused by evaluating the message by the RTL circuit delay parameter, further, the embodiment of the application adopts the higher-order ESL model delay parameter of the C language to realize the message delay evaluation, and at this time, the error ESL model delay parameter needs to be calibrated by using the RTL circuit delay parameter, so as to obtain the corrected ESL delay parameter.

The method solves the problem of insufficient accuracy of the delay evaluation of the switch chip, rapidly marks RTL circuit parameters influencing the delay of the chip into an ESL model, evaluates whether the delay parameters of the ESL model are accurate or not through the high-accuracy chip ESL model, corrects the delay parameters of the ESL model with errors, and finally evaluates the message transmission delay through the corrected delay parameters of the ESL model to obtain an accurate delay result.

In addition, in this embodiment, the end-to-end delay data is further split into a plurality of small-granularity delay indexes, that is, transmission delay parameters corresponding to each block, and the delay data is evaluated in each small-granularity delay parameter index, so that the evaluation result is finer and more accurate.

It should be noted that, the method can provide not only the end-to-end transmission delay data of the chip, but also the transmission delay parameter data with any length (the length is smaller than the end-to-end delay of the chip) according to the needs of the chip developer, and provides convenience for the chip developer to evaluate the delay indexes of different modules and different subsystems in the chip.

Embodiments of the apparatus corresponding to the above-described method embodiments are described below.

Fig. 5 is a schematic structural diagram of a verification device for delay parameters according to an embodiment of the present application. The device may be the foregoing detecting device, or a third party device, where the third party device includes the function of the detecting device, and may implement the method for checking the delay parameter in the foregoing embodiment.

Specifically, as shown in fig. 5, the apparatus may include: an acquisition unit 501 and a processing unit 502. In addition, the apparatus may further include other units or modules such as a storage unit (the storage unit is not shown in fig. 5), which is not limited in this embodiment.

The obtaining unit 501 is configured to obtain a first set of parameters and a second set of parameters, where the first set of parameters includes a delay parameter of a packet transmitted in at least one module of the RTL circuit, the second set of parameters includes a delay parameter of the at least one module counted by the packet when the ESL model is transmitted, and the detected RTL circuit and ESL circuit are divided into at least one module (block) in advance, where each module includes an input interface and an output interface of a signal.

And the processing unit 502 is configured to verify that an error exists in the second set of parameters when the first set of parameters is not matched with the second set of parameters, calibrate the second set of parameters to obtain a third set of parameters, and perform an evaluation operation of the message transmission delay by using the third set of parameters.

Optionally, in a specific embodiment, if the at least one module includes a first module, the obtaining unit 501 is further configured to obtain a time difference between a time point when the packet reaches the input interface and a time point when the packet reaches the output interface of the first module.

Further, the obtaining unit 501 is further configured to obtain the first set of parameters by multiplexing an EDA verification monitor or an interface signal monitoring function provided by using EDA technology.

Optionally, in another specific embodiment, the processing unit 502 is further configured to determine, before the obtaining unit 501 obtains the first set of parameters, whether the data transmitted by the message in the RTL circuit chip is real data, and if so, obtain the first set of parameters.

Further, when the indication mark carried by the message start part (sop) of the message is judged to be '1', the data transmitted in the message is determined to be real data.

Optionally, in another specific embodiment, when the message is a first message set, where the first message set includes N messages with different lengths, N is greater than or equal to 2, N is a positive integer, and the obtaining unit 501 is further configured to obtain a weighted average of delay parameters of transmission of the N messages in the same module.

Optionally, in another specific embodiment, the storage unit is configured to store a CLAT table, where the CLAT table includes a delay parameter transmitted by each module of the at least one module. The obtaining unit 501 is further configured to obtain the first set of parameters from the CLAT stored in the storage unit.

Optionally, the CLAT table further stores the second set of parameters, and a comparison result obtained by comparing the first set of parameters with the second set of parameters.

Optionally, in another specific embodiment, the obtaining unit 501 is further configured to obtain a delay parameter of at least one module in the ESL model for transmitting the message based on ESL modeling and ESL simulation technology.

The device combines EDA verification technology and ESL model technology, rapidly marks RTL circuit parameters into an ESL model, ensures that accurate time delay data can be acquired at any time in the chip development process, and improves the efficiency of acquiring chip transmission time delay parameters.

In addition, in a hardware implementation, the embodiment of the application further provides a detection device, which may be a chip circuit or may be a functional module integrated in a third party device, such as an APK packet. In addition, the detection device may further include the aforementioned verification device for the delay parameter.

Fig. 6 shows a schematic structural diagram of the detection device, including: at least one processor 110 and interface circuitry 120, wherein the at least one processor 110 and interface circuitry 120 are coupled by a bus. Further, optionally, other modules or units may be included, such as memory 130, at least one pin, and the like.

The at least one processor 110 is a control center of the chip circuit, and may be used to implement the method for checking the delay parameter in the foregoing embodiment.

Further, the at least one processor 110 may be comprised of integrated circuits (Integrated Circuit, ICs), such as a single packaged IC, or may be comprised of multiple packaged ICs connected to the same function or different functions. For example, the processor may include a central processing unit (central processing unit, CPU) or a digital signal processor (digital signal processor, DSP), etc.

In addition, the at least one processor 110 may also include a hardware chip, which may be a logic circuit, an application specific integrated circuit (application specific integrated circuit, ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), general-purpose array logic (generic array logic, GAL), or any combination thereof.

The memory 130 is used for storing and exchanging various data or signals, including a first message, a first set of messages, a first set of parameters, a second set of parameters, or a CLAT table. Furthermore, the memory 130 may have stored therein a computer program or code.

In particular, the memory 130 may include volatile memory (volatile memory), such as random access memory (random access memory, RAM); non-volatile memory (non-volatile memory) may also be included, such as flash memory (flash memory), hard disk (HDD) or Solid State Drive (SSD), and memory 130 may also include a combination of the above types of memory.

Alternatively, the memory 130 may be integrated into the at least one processor 110 as a storage medium, or may be configured outside the processor, which is not limited in this embodiment.

The memory 130 is configured to store information such as the first set of parameters, the second set of parameters, the received message, and the CLAT table.

The interface circuit 120, including at least one input interface and an output interface, may use any transceiver-like device. For example, the interface circuit 120 is connected to an RTL circuit chip, and is configured to obtain the time delay parameter of the RTL circuit, i.e., the first set of parameters. In addition, the interface circuit 120 is further configured to obtain a delay parameter of at least one module of the ESL model statistics, i.e. the aforementioned second set of parameters.

It should be appreciated that the interface circuit 120 is also used to communicate with other devices, either internal or external, such as ethernet, WLAN, etc.

In addition, when the detection device is used as a third party device, such as a server and a controller, the third party device may further include a mobile communication module, a wireless communication module, and the like. The mobile communication module includes: a module with wireless communication functions such as 2G/3G/4G/5G communication. Further, filters, switches, power amplifiers, low noise amplifiers (low noise amplifier, LNA), etc. may also be included. In addition, the wireless communication module may provide a solution for wireless communication including WLAN, bluetooth (BT), global navigation satellite system (global navigation satellite system, GNSS), etc. applied on a server or controller.

It should be understood that other more or fewer components may be included in the detection device, and the structure illustrated in the embodiments of the present application is not limited to the specific structure. And the components shown in fig. 6 may be implemented in hardware, software, firmware, or any combination thereof.

When implemented in software, may be implemented in whole or in part in the form of a computer program product. For example, in the apparatus shown in fig. 5 described above, the functions of the acquisition unit 501 and the processing unit 502 may be implemented by at least one processor 110 and the interface circuit 120, and the functions of the storage unit may be implemented by the memory 130.

In addition, the embodiment of the application also provides a wireless communication system, as shown in fig. 1, which comprises at least one server, a switch, a UE and an eNB. The structure of each device in the system may be the same as or different from that shown in fig. 6.

When the architecture shown in fig. 6 is employed, the at least one processor 110 obtains the first set of parameters and the second set of parameters using the interface circuit 120, where the first set of parameters includes delay parameters of a message transmitted in at least one module of the RTL circuit, and the second set of parameters includes delay parameters of the at least one module counted by the message when the ESL model is transmitted. In addition, the at least one processor 110 is further configured to determine whether the first set of parameters and the second set of parameters match, if not, determine that an error exists in the second set of parameters, calibrate the second set of parameters to obtain a third set of parameters, and perform an evaluation operation of the message transmission delay by using the third set of parameters.

When detecting that the sampled delay parameter of the ESL model has errors, the system provided in the system calibrates the delay parameter of the ESL model and evaluates the message delay by using the calibrated parameter, thereby avoiding errors caused by sampling the RTL delay parameter by a developer.

In addition, the present application also provides a computer program product comprising one or more computer program instructions. When loaded and executed by a computer, produces, in whole or in part, a flow or function as described in the various embodiments above. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus.

The computer program instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a network node, computer, server, or data center to another node by wire or wirelessly.

Furthermore, in the description of the present application, unless otherwise indicated, "a plurality" means two or more than two. In addition, in order to facilitate the clear description of the technical solution of the embodiments of the present application, in the embodiments of the present application, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.

The embodiments of the present application described above do not limit the scope of the present application.

Claims (16)

1. A method of verifying a delay parameter, the method comprising:

   acquiring a first set of parameters, wherein the first set of parameters comprise delay parameters of message transmission in at least one module of a Register Transfer Level (RTL) circuit;

   acquiring a second set of parameters, wherein the second set of parameters comprise time delay parameters of the at least one module counted when the message is transmitted by an ESL model designed at an electronic system level;

   and if the first group of parameters are not matched with the second group of parameters, determining that the second group of parameters have errors, calibrating the second group of parameters to obtain a third group of parameters, and utilizing the third group of parameters to evaluate the message transmission delay.
2. The method of claim 1, wherein the at least one module comprises a first module, the obtaining a first set of parameters comprising:

   and acquiring the time difference between the time point of the message reaching the input interface of the first module and the time point of the message reaching the output interface.
3. The method according to claim 1 or 2, wherein prior to the obtaining the first set of parameters, further comprising:

   judging whether the data transmitted by the message in the RTL circuit chip is real data or not, and if so, acquiring the first group of parameters.
4. The method of claim 3, wherein determining whether the data transmitted by the message within the RTL circuit chip is authentic data comprises:

   judging whether the indication mark carried by the message initial part of the message is 1.
5. The method according to any one of claims 1-4, wherein when the message is a first message set, the first message set includes N messages of different lengths, N is greater than or equal to 2, and N is a positive integer, the obtaining the first set of parameters includes:

   and acquiring a weighted average value of the delay parameters transmitted by the N messages in the same module.
6. The method of any of claims 1-5, wherein the obtaining a first set of parameters comprises:

   and acquiring the first group of parameters from a chip delay accuracy verification table (CLAT), wherein the CLAT comprises delay parameters transmitted by each module in the at least one module.
7. The method of any of claims 1-6, wherein the obtaining a second set of parameters comprises:

   and acquiring the time delay parameter of the message transmitted by at least one module in the ESL model based on ESL modeling and ESL simulation technology.
8. A device for verifying a delay parameter, the device comprising:

   the system comprises an acquisition unit, a Register Transfer Level (RTL) circuit and a storage unit, wherein the acquisition unit is used for acquiring a first group of parameters and a second group of parameters, the first group of parameters comprise delay parameters of a message transmitted in at least one module of the RTL circuit, and the second group of parameters comprise delay parameters of the at least one module counted when the message is transmitted in an ESL (electronic system level) model;

   and the processing unit is used for checking that errors exist in the second group of parameters when the first group of parameters are not matched with the second group of parameters, calibrating the second group of parameters to obtain a third group of parameters, and utilizing the third group of parameters to evaluate the message transmission delay.
9. The apparatus of claim 8, wherein the at least one module comprises a first module,

   the obtaining unit is further configured to obtain a time difference between a time point when the packet reaches the input interface and a time point when the packet reaches the output interface of the first module.
10. The device according to claim 8 or 9, wherein,

    the processing unit is further configured to determine, before the obtaining unit obtains the first set of parameters, whether data transmitted by the message in the RTL circuit chip is real data, and if so, obtain the first set of parameters.
11. The apparatus of claim 10, wherein the device comprises a plurality of sensors,

    the processing unit is further configured to determine that the data is real data when an indication mark carried by a message start portion of the message is "1".
12. The apparatus according to any one of claims 8-11, wherein when the message is a first message set, the first message set includes N messages of different lengths, N is greater than or equal to 2, and N is a positive integer,

    the obtaining unit is further configured to obtain a weighted average of delay parameters of the N packets transmitted in the same module.
13. The apparatus according to any one of claims 8-12, further comprising a memory unit,

    the storage unit is used for storing a chip delay precision verification table (CLAT), and the CLAT table comprises delay parameters transmitted by each module in the at least one module;

    the acquiring unit is further configured to acquire the first set of parameters from the CLAT of the storage unit.
14. The apparatus according to any one of claims 8 to 13, wherein,

    the acquisition unit is further configured to acquire a delay parameter of transmission of the message in at least one module in the ESL model based on ESL modeling and ESL simulation technologies.
15. A detection apparatus, characterized by comprising: at least one processor and an interface circuit,

    the interface circuit is used for providing instructions and/or data for the at least one processor;

    the at least one processor configured to execute the instructions to implement the method of any one of claims 1 to 7.
16. A computer readable storage medium, characterized in that the computer readable storage medium has stored therein computer program instructions which, when executed, implement the method of any of claims 1 to 7.