CN116684954A - Clock synchronization verification system, method, server, chip and electronic equipment - Google Patents
Clock synchronization verification system, method, server, chip and electronic equipment Download PDFInfo
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Abstract
The application provides a clock synchronization verification system, a clock synchronization verification method, a server, a chip and electronic equipment, and relates to the technical field of communication. A clock synchronization verification system comprising: the device comprises a verification module, a tested master chip and a tested slave chip, wherein the verification module is communicated with the tested master chip and the tested slave chip; the master chip to be tested comprises a first time service module, a first sending end and a first receiving end, the slave chip to be tested comprises a second time service module, a second sending end and a second receiving end, the first sending end is connected with the second receiving end, the second sending end is connected with the first receiving end, the verification module is used for verifying whether clocks of the master chip to be tested and the slave chip to be tested are synchronous or not according to timing information and hardware time of the master chip to be tested and timing information and hardware time of the slave chip to be tested, and when the clocks are not synchronous, clock synchronization can be achieved by adjusting the time inside the master chip to be tested or the slave chip to be tested.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a clock synchronization verification system, a clock synchronization verification method, a clock synchronization server, a clock synchronization chip, and an electronic device.
Background
For wireless communication, clock synchronization between base stations is crucial, and a commonly used clock calibration method is based on an IEEE1588 protocol, and the 1588 protocol is a precision clock synchronization protocol standard of a network measurement and control system.
However, in the communication service, when the master device and the slave device perform data transmission, the data format of the transmission data is often required to be processed, and the change of the data format of the transmission data may generate delay jitter, which affects the accurate clock synchronization of the chips in the master device and the slave device, so that the data transmission efficiency of the master device and the slave device is reduced, and the data transmission between the master device and the slave device mainly depends on the data transmission between the running chips, so that it is required to verify whether the clocks between the built-in chips of the master device and the slave device are synchronous before the data transmission between the master device and the slave device.
Disclosure of Invention
In view of the above, the present application aims to provide a clock synchronization verification system, a method, a server, a chip and an electronic device, which can solve the verification problem of the clock synchronization of the existing chip.
Based on the above object, in a first aspect, the present application proposes a clock synchronization verification system, the system comprising: the device comprises a verification module, a tested master chip and a tested slave chip, wherein the verification module is communicated with the tested master chip and the tested slave chip; the tested main chip comprises a first time service module, a first sending end and a first receiving end, the tested slave chip comprises a second time service module, a second sending end and a second receiving end, the first sending end is connected with the second receiving end, and the second sending end is connected with the first receiving end; the first time service module is used for recording timing information and hardware time of the tested master chip when the tested master chip sends or receives a message, the second time service module is used for recording timing information and hardware time of the tested slave chip when the tested slave chip sends or receives a message, the hardware time of the tested master chip is used for calculating link delay of the tested master chip, and the hardware time of the tested slave chip is used for calculating link delay of the tested slave chip; the verification module is used for verifying whether clocks of the tested master chip and the tested slave chip are synchronous or not according to the timing information and the hardware time of the tested master chip and the timing information and the hardware time of the tested slave chip.
Optionally, the system further comprises a first packet sending module, a first data acquisition module, a simulation operation module, a second packet sending module and a second data acquisition module; the first packet sending module and the first data acquisition module are connected with the tested main chip, the second packet sending module and the second data acquisition module are connected with the tested auxiliary chip, the simulation operation module is respectively connected with the first data acquisition module and the second data acquisition module, and the simulation operation module is used for simulating the function execution process of the tested main chip and the tested main chip according to the data acquired by the first data acquisition module and the second data acquisition module.
In a second aspect, there is also provided a clock synchronization verification method, which is applied to the clock synchronization verification system in the first aspect, and includes: acquiring first data when a first message is transmitted between a tested master chip and a tested slave chip, wherein the first message is sent out by the tested master chip; obtaining the time when the first message leaves the tested master chip and the time when the first message reaches the tested slave chip according to the first data; acquiring second data when a second message is transmitted between a tested slave chip and a tested master chip, wherein the second message is sent out by the tested slave chip; obtaining the time when the second message leaves the tested slave chip and the time when the second message reaches the tested master chip according to the second data; and obtaining a first time difference according to the time when the first message leaves the tested master chip, the time when the first message reaches the tested slave chip and the time when the second message leaves the tested slave chip, and determining a clock verification result between the tested master chip and the tested slave chip according to the first time difference.
Optionally, the first data includes first timing information and first hardware time of the master chip to be tested when the master chip to be tested sends a first message to the slave chip to be tested, and second timing information, second hardware time and first timestamp information of the slave chip to be tested when the slave chip to be tested receives the first message, where the method includes: obtaining the link delay of the tested main chip according to the first hardware time, and obtaining the time of the first message leaving the tested main chip according to the link delay of the tested main chip and first timing information; obtaining the link delay of the tested slave chip according to the second hardware time and the first time stamp information of the tested slave chip, and obtaining the time of the first message reaching the tested slave chip according to the link delay of the tested slave chip and the second timing information.
Optionally, the second data includes third timing information and third hardware time of the slave chip to be tested when the slave chip to be tested sends the second message to the master chip to be tested, and fourth timing information, fourth hardware time and second timestamp information of the master chip to be tested when the master chip to be tested receives the second message, where the method includes: obtaining the link delay of the tested slave chip according to the third hardware time, and obtaining the time when the second message leaves the tested slave chip according to the link delay of the tested slave chip and third time counting information; obtaining the link delay of the tested main chip according to the fourth hardware time and the second time stamp information of the tested main chip, and obtaining the time of the second message reaching the tested main chip according to the link delay and the fourth timing information of the tested main chip.
Optionally, the method comprises: acquiring simulation time of the tested master chip and simulation time of the tested slave chip at preset time, and obtaining a second time difference according to the simulation time of the tested master chip and the simulation time of the tested slave chip; and determining a clock verification result between the tested master chip and the tested slave chip according to the deviation of the second time difference and the first time difference.
In a third aspect, there is also provided a clock synchronization verification server, including: the first data module is used for acquiring first data when a first message is transmitted between a tested master chip and a tested slave chip, wherein the first message is sent out by the tested master chip; the first calculation module is used for obtaining the time when the first message leaves the tested master chip and the time when the first message reaches the tested slave chip according to the first data; the second data module is used for acquiring second data when a second message is transmitted between the tested slave chip and the tested master chip, and the second message is sent out by the tested slave chip; the second calculation module is used for obtaining the time when the second message leaves the tested slave chip and the time when the second message reaches the tested master chip according to the second data; the verification module is used for obtaining a first time difference according to the time when the first message leaves the tested master chip, the time when the first message reaches the tested slave chip and the time when the second message leaves the tested slave chip, and determining a clock verification result between the tested master chip and the tested slave chip according to the first time difference.
In a fourth aspect, there is also provided a chip, the chip including a master chip under test and a slave chip under test; the measured master chip or the measured slave chip is used for acquiring time data between the measured master chip and the measured slave chip and obtaining a clock verification result between the measured master chip and the measured slave chip according to the time data; the time data comprises first timing information and first hardware time of the tested master chip when the tested master chip sends a first message to the tested slave chip, and second timing information, second hardware time and first time stamp information of the tested slave chip when the tested slave chip receives the first message; and when the tested slave chip sends a second message to the tested master chip, third timing information and third hardware time of the tested slave chip, and when the tested master chip receives the second message, fourth timing information, fourth hardware time and second timestamp information of the tested master chip.
In a fifth aspect, there is also provided an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor runs the computer program to implement the method of the second aspect.
In a sixth aspect, there is also provided a computer readable storage medium having stored thereon a computer program for execution by a processor to implement the method of any of the second aspects.
In general, the present application has at least the following benefits:
the clock synchronization verification system provided by the embodiment forms a clock verification platform, provides a verification environment for clock verification of the chip, verifies whether clocks of the tested master chip and the tested slave chip are synchronous or not by acquiring timing information and hardware time of the tested master chip and timing information and hardware time of the tested slave chip when the chip is in the verification environment, and can realize clock synchronization by adjusting the time inside the tested master chip or the tested slave chip when the clocks are not synchronous.
Drawings
In the drawings, the same reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily drawn to scale. It is appreciated that these drawings depict only some embodiments according to the disclosure and are not therefore to be considered limiting of its scope.
FIG. 1 is a schematic diagram of the clock synchronization verification system of the present application;
FIG. 2 shows a clock synchronization schematic diagram of the present embodiment;
fig. 3 is a flowchart showing steps of the clock synchronization verification method of the present embodiment;
fig. 4 is a schematic diagram showing the structure of a clock synchronization verification server according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application;
fig. 6 is a schematic diagram of a storage medium according to an embodiment of the present application.
Detailed Description
The application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be noted that, for convenience of description, only the portions related to the present application are shown in the drawings.
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
Fig. 1 shows a schematic diagram of the structure of the clock synchronization verification system of the present application. In an embodiment of the present application, the clock synchronization verification system 100 includes: verification module 103, master chip under test 101 and slave chip under test 102, the verification module communicates with master chip under test 101 and slave chip under test 102.
In this embodiment, the clock synchronization verification system 100 may form a clock verification platform, and may be used to verify whether clocks of the master chip 101 and the slave chip 102 are synchronized by acquiring data during verification of the master chip 101 and the slave chip 102 when the master chip 101 and the slave chip 102 are in a verification environment. The verification module of the present embodiment may be a processor or an integrated module with data functionality. The verification module communicates with the tested master chip and the tested slave chip through the same Ethernet.
In this embodiment, the measured master chip 101 includes a first time service module 104, a first transmitting end tx1 and a first receiving end rx1, and the measured slave chip 102 includes a second time service module 105, a second transmitting end tx2 and a second receiving end rx2, where the first transmitting end tx1 is connected to the second receiving end rx2, and the second transmitting end tx2 is connected to the first receiving end rx1.
In this embodiment, the first time service module 104 may be a PTP module, that is, a standardized precise time protocol (picture transfer protocol, PTP), which is a timing module inside a chip, and the first time service module 104 is used for recording timing information and hardware time of a measured main chip when the measured main chip sends or receives a message. Similarly, the second timing module 105 is configured to record timing information and hardware time of the slave chip to be tested when the slave chip to be tested sends or receives a message.
The first transmitting end tx1 in this embodiment is configured to transmit data of a master chip to be tested to the second receiving end rx2 of a slave chip to be tested, and the second transmitting end tx2 is configured to transmit data of the slave chip to be tested to the first receiving end rx1 of the master chip to be tested, so that the master chip 101 to be tested and the slave chip 102 to be tested are located under the same network, so as to realize data transmission between the master chip to be tested and the slave chip to be tested, and detect whether clocks between the master chip and the slave chip are synchronous according to time parameters in a data interaction process.
In this embodiment, the timing information and the hardware time of the master chip to be tested are time information recorded in different timing modes, for example, when the master chip to be tested sends 1588 messages to the slave chip to be tested, the processing module obtains TOD timing information and hardware time hw_time1 from the first timing module, where the TOD timing information includes s, ns and ns decimal information, the time of TOD is counted to the power of 9 in ns, s bits are added by 1 ns, and the count starts again from 0. hw_time1 contains ns information and hw_time1 is accumulated in ns.
In this embodiment, the hardware time is used to calculate the link delay, the hardware time of the master chip under test is used to calculate the link delay of the master chip under test, and the hardware time of the slave chip under test is used to calculate the link delay of the slave chip under test. The link delay may be the time required for data transfer delay due to data format conversion or hardware configuration itself when data is transferred inside the chip.
In this embodiment, the verification module is configured to verify whether clocks of the master chip to be tested and the slave chip to be tested are synchronous according to timing information and hardware time of the master chip to be tested, and timing information and hardware time of the slave chip to be tested.
Referring to fig. 1, in this embodiment, the clock synchronization verification system further includes a first packet sending module, a first data acquisition module, an analog operation module, a second packet sending module, and a second data acquisition module; the first packet sending module and the first data acquisition module are connected with the tested main chip, the second packet sending module and the second data acquisition module are connected with the tested auxiliary chip, the simulation operation module is respectively connected with the first data acquisition module and the second data acquisition module, and the simulation operation module is used for simulating the function execution process of the tested main chip and the tested main chip according to the data acquired by the first data acquisition module and the second data acquisition module.
In one example, the first packet sending module and the second packet sending module each include a packet sending module for sending 1588 messages from the tested master chip to the tested slave chip, the second packet sending module is for sending 1588 messages from the tested slave chip to the tested master chip, the first data collecting module is for collecting input and output data of the tested master chip, the second data collecting module is for collecting input and output data of the tested slave chip, the simulation running module is for simulating function execution processes of the tested master chip and the tested slave chip, and the simulation running module may be a reference model (rm) for simulating executable programs of simulation simulator hardware corresponding to the tested chip.
In one example, the tested master chip and the tested slave chip each include mac, pcs and serdes, where mac is a protocol data interface for receiving a packet of data, pcs is a physical coding layer for coding, and serdes is a serializer/deserializer.
The clock synchronization verification system provided by the embodiment forms a clock verification platform, provides a verification environment for clock verification of the chip, verifies whether clocks of the tested master chip and the tested slave chip are synchronous or not by acquiring timing information and hardware time of the tested master chip and timing information and hardware time of the tested slave chip when the chip is in the verification environment, and can realize clock synchronization by adjusting the time inside the tested master chip or the tested slave chip when the clocks are not synchronous.
Fig. 2 shows a clock synchronization schematic diagram of the present embodiment. Wherein delay is the link delay, delta is the time difference between the measured master chip and the measured slave chip, t1 is the time when the message leaves the measured master chip, t2 is the time when the message reaches the measured slave chip, the packet is reversely sent, t3 is the time when the message leaves the measured slave chip, and t4 is the time when the message reaches the measured master chip.
As can be seen from fig. 2, t2=t1+delay+delta, t4=t3+delay-delta, and the two equations are subtracted to obtain delta= ((t2+t3) - (t1+t4))/2, so as to obtain the time difference delta between the master chip to be tested and the slave chip to be tested.
Based on the clock synchronization verification system shown in fig. 1 and the clock synchronization principle shown in fig. 2, fig. 3 shows a step flowchart of the clock synchronization verification method of the present embodiment, and the present embodiment further provides a clock synchronization verification method applied to the clock synchronization verification system shown in fig. 1, and referring to fig. 3, the clock synchronization verification method includes steps S301 to S305 as follows:
s301, first data when a first message is transmitted between a tested master chip and a tested slave chip are obtained.
In this embodiment, the first message is sent by the master chip to be tested, and the first data includes first timing information and first hardware time of the master chip to be tested when the master chip to be tested sends the first message to the slave chip to be tested, and second timing information, second hardware time and first timestamp information of the slave chip to be tested when the slave chip to be tested receives the first message.
For example, when the measured master chip sends a first message to the measured slave chip, the first timing information of the measured master chip is T1 and a first hardware time hw_time1, the T1 is stored in the message, the hw_time1 is sent to the measured master chip by the first transmitter module driver through the interface, after the measured master chip receives the first message, according to the configuration of the internal link of the measured master chip, the link delay Δt1 of mac, pcs and serdes is calculated, the delay Δt1 is written into the correction field of 1588, when the measured slave chip receives the first message sent by the measured master chip, the timestamp information timestamp of the arrival of the first message is transmitted to the second data acquisition module through the interface to be acquired, and the second data acquisition module acquires the second timing information T2 and the second hardware time hw_time2 from the second timing module. The first data includes a first timing information T1, a first hardware time hw_time1, a second timing information T2, a second hardware time hw_time2, and a first timestamp information timestamp1.
S302, according to the first data, obtaining the time when the first message leaves the tested master chip and the time when the first message reaches the tested slave chip.
In this embodiment, the link delay of the tested main chip is obtained according to the first hardware time, and the time when the first message leaves the tested main chip is obtained according to the link delay of the tested main chip and the first timing information. It can be understood that, due to the existence of the link delay Δt1, the time t1=t1+Δt1, T1 and Δt1 when the first packet is sent from the first sending end of the tested main chip can be resolved from the first packet.
And obtaining the link delay of the tested slave chip according to the second hardware time and the first time stamp information of the tested slave chip, and obtaining the time of the first message reaching the tested slave chip according to the link delay of the tested slave chip and the second timing information. It can be understood that, since the first timestamp information timestamp1 is obtained by the hardware time of the second time service module when the first packet arrives at the first receiving end, and the second hardware time hw_time2 is the time when the second data acquisition module receives the packet, the time between the time when the packet arrives at the slave chip under test and the time when the packet leaves the slave chip under test and is received by the second data acquisition module can be taken as the link delay of the slave chip under test (hw_time2-timestamp 1), in this embodiment, the second timing information is T2, and the time when the first packet arrives at the slave chip under test can be expressed as t2=t2- (hw_time2-timestamp 1).
S303, second data when a second message is transmitted between the tested slave chip and the tested master chip is obtained.
In this embodiment, the second message is sent from the slave chip under test. The second data comprises third timing information and third hardware time of the tested slave chip when the tested slave chip sends a second message to the tested master chip, and fourth timing information, fourth hardware time and second timestamp information of the tested master chip when the tested master chip receives the second message.
For example, when the measured slave chip sends a second message to the measured master chip, the third timing information of the measured slave chip is T3 and third hardware time hw_time3, T3 may be stored in the message, hw_time3 may be sent to the measured slave chip by the second packet sending module through the interface, after the measured slave chip receives the second message, according to the configuration of the measured slave chip internal link, the link delay Δt2 of mac, pcs and serdes may be calculated, the delay Δt2 is written into the correction field of 1588, when the measured master chip receives the second message sent from the measured slave chip, the timestamp information time stamp2 reached by the second message is transmitted to the first data acquisition module through the interface, and the first data acquisition module may acquire fourth timing information T4 and fourth hardware time hw_time4 from the first time service module. It can be seen that the second data includes the third timing information T3, the third hardware time hw_time3, the fourth timing information T4, the fourth hardware time hw_time4 and the second timestamp information timestamp2.
S304, according to the second data, obtaining the time when the second message leaves the tested slave chip and the time when the second message reaches the tested master chip.
In this embodiment, the link delay of the measured slave chip is obtained according to the third hardware time, and the time when the second message leaves the measured slave chip is obtained according to the link delay of the measured slave chip and the third timing information. It can be understood that, due to the existence of the link delay Δt2, the time t3=t3+Δt2, T3 and Δt2 of the second packet sent from the second sending end of the slave chip to be tested can be resolved from the second packet.
And obtaining the link delay of the tested main chip according to the fourth hardware time of the tested main chip and the second time stamp information, and obtaining the time of the second message reaching the tested main chip according to the link delay of the tested main chip and the fourth timing information. It can be understood that, since the second timestamp information timestamp2 is obtained by the hardware time of the first time service module when the second message arrives at the second receiving end, and the fourth hardware time hw_time4 is the time when the first data acquisition module receives the message, the time from the time when the message arrives at the measured main chip to the time when the message leaves the measured main chip and is received by the first data acquisition module can be used as the link delay of the measured main chip, and denoted as (hw_time4-timestamp 2), in this embodiment, the time when the first message arrives at the measured sub chip can be denoted as t4=t4- (hw_time4-timestamp 2) when the second timing information is T4.
S305, according to the time when the first message leaves the tested master chip, the time when the first message reaches the tested slave chip and the time when the second message leaves the tested slave chip, the time when the second message reaches the tested master chip is obtained, a first time difference is obtained, and a clock verification result between the tested master chip and the tested slave chip is determined according to the first time difference.
In this embodiment, the representation of t1, t2, t3, t4 can be obtained in steps S301 to S304, and the first time difference between the master chip and the slave chip to be tested is as follows in combination with the original knowledge of fig. 2:
delta_cal＝((t2+t3)-(t1+t4))/2
the clock verification result between the tested master chip and the tested slave chip is determined according to the first time difference, for example, the larger the difference between the first time difference and the preset value is, the time of the tested master chip and the time of the tested slave chip are not synchronous, and when the first time difference is smaller than the preset value, the time synchronization precision of the tested master chip and the tested slave chip is satisfied.
When the clock verification result indicates that the clocks of the tested master chip and the tested slave chip are not synchronous, the TOD time information of the tested master chip and the tested slave chip, namely the timing information of the tested master chip or the timing information of the tested slave chip, can be adjusted so as to adjust the time difference between the two chips.
The clock synchronization verification provided by the embodiment is an ideal test flow and adjustment method, in an actual application environment, such as UVM (Universal Verification Methodology) environment, considering that the time difference between the tested master chip and the tested slave chip can be directly obtained, the clocks of the tested master chip and the tested slave chip are clocks provided by themselves, the same frequency can be completely achieved, after adjustment is performed once, the clocks of the tested master chip and the tested slave chip can be kept completely synchronous, and the significance of multiple test adjustment is not great.
In this embodiment, the clock synchronization verification further includes obtaining a simulation time of the master chip to be tested and a simulation time of the slave chip to be tested at a preset time, and obtaining a second time difference according to the simulation time of the master chip to be tested and the simulation time of the slave chip to be tested; and determining a clock verification result between the tested master chip and the tested slave chip according to the deviation of the second time difference and the first time difference.
For example, when the TOD times of the measured master chip and the measured slave chip are respectively counted to a certain time point, for example, 100ns, and at this time, the simulation time realtem 1 and the realtem 2 of the UVM platform are respectively recorded, then the second time difference delta_real=realtem 1-realtem 2 is obtained according to the clock synchronization verification method of the above embodiment, delta_cal is obtained at this time, the tolen sending of the data packet is performed, each round of sending the packet compares the difference between delta_real and delta_cal, whether the clocks between the measured master chip and the measured slave chip are synchronous or not is repeatedly verified through the repeated sending of the tolen, and meanwhile, whether the time stamping precision of the measured master chip and the measured slave chip can meet the expectations can be verified.
In addition, the above is clock verification of the tested master chip and the tested slave chip in the verification environment, and the time data of the tested master chip and the tested slave chip may be collected by the first data collection module or the second data collection module, and then processed by the processing module. In the actual sample test, since the time information of the tested master chip and the tested slave chip are isolated from each other, all the time information needs to be sent to the same chip for processing and calculating, for example, all the time information needs to be sent to the tested slave chip for processing and calculating, when the tested master chip receives the message sent by the tested slave chip, the tested slave chip cannot know the TOD time when the tested master chip receives the message, and at this time, the tested master chip needs to send the TOD time of the tested master chip to the tested slave chip in the form of 1588message for calculating, that is, the to-be-tested chip which does not execute the calculation needs to send the message for many times. Specifically, the master chip and the slave chip can be arranged on the same test circuit and connected with the same crystal oscillator so as to keep the clocks of the tested master chip and the tested slave chip homologous.
According to the clock synchronization verification method provided by the embodiment, the first data are obtained when the first message is transmitted between the tested master chip and the tested slave chip, and the time when the first message leaves the tested master chip and the time when the first message reaches the tested slave chip are obtained according to the first data; obtaining the time when the second message leaves the tested slave chip and the time when the second message reaches the tested master chip according to the second data by obtaining the second data when the second message is transmitted between the tested slave chip and the tested master chip; and obtaining a first time difference according to the data, determining a clock verification result between the tested master chip and the tested slave chip according to the first time difference, and realizing clock synchronization by adjusting a time service module of the tested master chip and the tested slave chip when the clocks of the tested master chip and the tested slave chip are not synchronous.
Fig. 4 is a schematic structural diagram of a clock synchronization verification server according to the present embodiment, which is configured to execute the clock synchronization verification method according to the foregoing embodiment, as shown in fig. 4, where the clock synchronization verification server 400 includes:
A first data module 401, configured to obtain first data when a first message is transmitted between a master chip to be tested and a slave chip to be tested, where the first message is sent by the master chip to be tested;
a first calculation module 402, configured to obtain, according to the first data, a time when the first packet leaves the tested master chip and a time when the first packet reaches the tested slave chip;
a second data module 403, configured to obtain second data when a second message is transferred between a slave chip to be tested and a master chip to be tested, where the second message is sent by the slave chip to be tested;
a second calculation module 404, configured to obtain, according to the second data, a time when the second packet leaves the measured slave chip and a time when the second packet reaches the measured master chip;
the verification module 405 is configured to obtain a first time difference according to a time when the first message leaves the tested master chip, a time when the first message reaches the tested slave chip, and a time when the second message leaves the tested slave chip, and the time when the second message reaches the tested master chip, and determine a clock verification result between the tested master chip and the tested slave chip according to the first time difference.
In one example, the first data includes first timing information and first hardware time of the master chip to be tested when the master chip to be tested sends a first message to the slave chip to be tested, and second timing information, second hardware time and first timestamp information of the slave chip to be tested when the slave chip to be tested receives the first message, and the first calculation module 402 is configured to obtain a link delay of the master chip to be tested according to the first hardware time, and obtain a time when the first message leaves the master chip to be tested according to the link delay of the master chip to be tested and the first timing information; obtaining the link delay of the tested slave chip according to the second hardware time and the first time stamp information of the tested slave chip, and obtaining the time of the first message reaching the tested slave chip according to the link delay of the tested slave chip and the second timing information.
In one example, the second data includes third timing information and third hardware time of the slave chip to be tested when the slave chip to be tested sends the second message to the master chip to be tested, and fourth timing information, fourth hardware time and second timestamp information of the master chip to be tested when the master chip to be tested receives the second message, and a second calculation module 404, configured to obtain a link delay of the slave chip to be tested according to the third hardware time, and obtain a time when the second message leaves the slave chip to be tested according to the link delay of the slave chip to be tested and the third timing information; obtaining the link delay of the tested main chip according to the fourth hardware time and the second time stamp information of the tested main chip, and obtaining the time of the second message reaching the tested main chip according to the link delay and the fourth timing information of the tested main chip.
In one example, the verification module 405 is configured to obtain a simulation time of the master chip to be tested and a simulation time of the slave chip to be tested at a preset time, and obtain a second time difference according to the simulation time of the master chip to be tested and the simulation time of the slave chip to be tested; and determining a clock verification result between the tested master chip and the tested slave chip according to the deviation of the second time difference and the first time difference.
The clock synchronization verification server provided by the above embodiment of the present application and the clock synchronization verification method provided by the embodiment of the present application have the same advantageous effects as the method adopted, operated or implemented by the application program stored therein, because of the same inventive concept.
The embodiment also provides a chip comprising a master chip and a slave chip ， The master chip of the present embodiment is the master chip to be tested provided in the above embodiment, and the slave chip of the present embodiment is the slave chip to be tested provided in the above embodiment. The master chip or the slave chip is used for acquiring time data between the master chip and the slave chip and obtaining a clock verification result between the tested master chip and the tested slave chip according to the time data, that is, the master chip can be used as an execution main body for obtaining the clock verification result between the tested master chip and the tested slave chip according to the time data, and the slave chip can also be used as an execution main body for obtaining the clock verification result between the tested master chip and the tested slave chip according to the time data.
The time data comprises first timing information and first hardware time of the tested master chip when the tested master chip sends a first message to the tested slave chip, and second timing information, second hardware time and first time stamp information of the tested slave chip when the tested slave chip receives the first message; and when the tested slave chip sends a second message to the tested master chip, third timing information and third hardware time of the tested slave chip, and when the tested master chip receives the second message, fourth timing information, fourth hardware time and second timestamp information of the tested master chip.
For example, in an actual sample test, since time information of a master chip to be tested and time information of a slave chip to be tested are isolated from each other, all time information needs to be sent to the same chip for processing and calculating, for example, all time information needs to be sent to the slave chip to be tested for processing and calculating, when the master chip to be tested receives a message sent by the slave chip to be tested, the slave chip to be tested cannot know the TOD time when the master chip to be tested receives the message, and at this time, the master chip to be tested needs to send the TOD time of the master chip to be tested to the slave chip to be tested in the form of 1588message for calculating, that is, the process that the to be tested chip not executing the calculation needs to send the message for many times needs to be explained that, in the actual sample test, in order to adjust two clocks to be synchronous, the clocks of the master chip to be tested need to be kept identical. Specifically, the master chip and the slave chip can be arranged on the same test circuit and connected with the same crystal oscillator so as to keep the clocks of the tested master chip and the tested slave chip homologous.
The embodiment of the application also provides an electronic device corresponding to the clock synchronization verification method provided by the previous embodiment, so as to execute the clock synchronization verification method. The embodiment of the application is not limited.
Referring to fig. 5, a schematic diagram of an electronic device according to some embodiments of the present application is shown. As shown in fig. 5, the electronic device 20 includes: a processor 200, a memory 201, a bus 202 and a communication interface 203, the processor 200, the communication interface 203 and the memory 201 being connected by the bus 202; the memory 201 stores a computer program that can be executed on the processor 200, and the processor 200 executes the clock synchronization verification method provided in any one of the foregoing embodiments of the present application when executing the computer program.
The memory 201 may include a high-speed random access memory (RAM: random Access Memory), and may further include a non-volatile memory (non-volatile memory), such as at least one disk memory. The communication connection between the system network element and at least one other network element is implemented via at least one communication interface 203 (which may be wired or wireless), the internet, a wide area network, a local network, a metropolitan area network, etc. may be used.
Bus 202 may be an ISA bus, a PCI bus, an EISA bus, or the like. The buses may be classified as address buses, data buses, control buses, etc. The memory 201 is configured to store a program, and the processor 200 executes the program after receiving an execution instruction, and the clock synchronization verification method disclosed in any of the foregoing embodiments of the present application may be applied to the processor 200 or implemented by the processor 200.
The processor 200 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 200 or by instructions in the form of software. The processor 200 may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU for short), a network processor (Network Processor, NP for short), etc.; but may also be a Digital Signal Processor (DSP), application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be embodied directly in the execution of a hardware decoding processor, or in the execution of a combination of hardware and software modules in a decoding processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in the memory 201, and the processor 200 reads the information in the memory 201, and in combination with its hardware, performs the steps of the above method.
The electronic equipment provided by the embodiment of the application and the clock synchronization verification method provided by the embodiment of the application have the same beneficial effects as the method adopted, operated or realized by the electronic equipment based on the same inventive concept.
The embodiment of the present application further provides a computer readable storage medium corresponding to the clock synchronization verification method provided in the foregoing embodiment, referring to fig. 6, the computer readable storage medium is shown as an optical disc 30, on which a computer program (i.e. a program product) is stored, where the computer program, when executed by a processor, performs the clock synchronization verification method provided in any of the foregoing embodiments.
It should be noted that examples of the computer readable storage medium may also include, but are not limited to, a phase change memory (PRAM), a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), a Read Only Memory (ROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a flash memory, or other optical or magnetic storage medium, which will not be described in detail herein.
The computer readable storage medium provided by the above embodiment of the present application has the same advantageous effects as the method adopted, operated or implemented by the application program stored therein, because of the same inventive concept as the clock synchronization verification method provided by the embodiment of the present application.
It should be noted that:
the algorithms and displays presented herein are not inherently related to any particular computer, virtual system, or other apparatus. Various general-purpose systems may also be used with the teachings herein. The required structure for a construction of such a system is apparent from the description above. In addition, the present application is not directed to any particular programming language. It will be appreciated that the teachings of the present application described herein may be implemented in a variety of programming languages, and the above description of specific languages is provided for disclosure of enablement and best mode of the present application.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the above description of exemplary embodiments of the application, various features of the application are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed application requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this application.
Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiments. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.
Various component embodiments of the application may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that some or all of the functions of some or all of the components in a virtual machine creation system according to embodiments of the application may be implemented in practice using a microprocessor or Digital Signal Processor (DSP). The present application can also be implemented as an apparatus or system program (e.g., a computer program and a computer program product) for performing a portion or all of the methods described herein. Such a program embodying the present application may be stored on a computer readable medium, or may have the form of one or more signals. Such signals may be downloaded from an internet website, provided on a carrier signal, or provided in any other form.
It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that various changes and substitutions are possible within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A clock synchronization verification system, the system comprising: the device comprises a verification module, a tested master chip and a tested slave chip, wherein the verification module is communicated with the tested master chip and the tested slave chip;
the tested main chip comprises a first time service module, a first sending end and a first receiving end, the tested slave chip comprises a second time service module, a second sending end and a second receiving end, the first sending end is connected with the second receiving end, and the second sending end is connected with the first receiving end;
the first time service module is used for recording timing information and hardware time of the tested master chip when the tested master chip sends or receives a message, the second time service module is used for recording timing information and hardware time of the tested slave chip when the tested slave chip sends or receives a message, the hardware time of the tested master chip is used for calculating link delay of the tested master chip, and the hardware time of the tested slave chip is used for calculating link delay of the tested slave chip;
The verification module is used for verifying whether clocks of the tested master chip and the tested slave chip are synchronous or not according to the timing information and the hardware time of the tested master chip and the timing information and the hardware time of the tested slave chip.
2. The system of claim 1, further comprising a first packet sending module, a first data acquisition module, a simulation run module, a second packet sending module, and a second data acquisition module;
the first packet sending module and the first data acquisition module are connected with the tested main chip, the second packet sending module and the second data acquisition module are connected with the tested auxiliary chip, the simulation operation module is respectively connected with the first data acquisition module and the second data acquisition module, and the simulation operation module is used for simulating the function execution process of the tested main chip and the tested main chip according to the data acquired by the first data acquisition module and the second data acquisition module.
3. A clock synchronization verification method, characterized in that the method is applied to the clock synchronization verification system according to claim 1 or 2, the method comprising:
Acquiring first data when a first message is transmitted between a tested master chip and a tested slave chip, wherein the first message is sent out by the tested master chip;
obtaining the time when the first message leaves the tested master chip and the time when the first message reaches the tested slave chip according to the first data;
acquiring second data when a second message is transmitted between a tested slave chip and a tested master chip, wherein the second message is sent out by the tested slave chip;
obtaining the time when the second message leaves the tested slave chip and the time when the second message reaches the tested master chip according to the second data;
and obtaining a first time difference according to the time when the first message leaves the tested master chip, the time when the first message reaches the tested slave chip and the time when the second message leaves the tested slave chip, and determining a clock verification result between the tested master chip and the tested slave chip according to the first time difference.
4. The method of claim 3, wherein the first data includes first timing information and first hardware time of the master chip under test when the master chip under test sends a first message to the slave chip under test, and second timing information, second hardware time and first timestamp information of the slave chip under test when the slave chip under test receives the first message, the method comprising:
Obtaining the link delay of the tested main chip according to the first hardware time, and obtaining the time of the first message leaving the tested main chip according to the link delay of the tested main chip and first timing information;
obtaining the link delay of the tested slave chip according to the second hardware time and the first time stamp information of the tested slave chip, and obtaining the time of the first message reaching the tested slave chip according to the link delay of the tested slave chip and the second timing information.
5. A method according to claim 3, wherein the second data includes third timing information and third hardware time of the slave chip under test when the slave chip under test transmits the second message to the master chip under test, and fourth timing information, fourth hardware time and second timestamp information of the master chip under test when the master chip under test receives the second message, the method comprising:
obtaining the link delay of the tested slave chip according to the third hardware time, and obtaining the time when the second message leaves the tested slave chip according to the link delay of the tested slave chip and third time counting information;
obtaining the link delay of the tested main chip according to the fourth hardware time and the second time stamp information of the tested main chip, and obtaining the time of the second message reaching the tested main chip according to the link delay and the fourth timing information of the tested main chip.
6. A method according to claim 3, characterized in that the method comprises:
acquiring simulation time of the tested master chip and simulation time of the tested slave chip at preset time, and obtaining a second time difference according to the simulation time of the tested master chip and the simulation time of the tested slave chip;
and determining a clock verification result between the tested master chip and the tested slave chip according to the deviation of the second time difference and the first time difference.
7. A clock synchronization verification server, comprising:
the first data module is used for acquiring first data when a first message is transmitted between a tested master chip and a tested slave chip, wherein the first message is sent out by the tested master chip;
the first calculation module is used for obtaining the time when the first message leaves the tested master chip and the time when the first message reaches the tested slave chip according to the first data;
the second data module is used for acquiring second data when a second message is transmitted between the tested slave chip and the tested master chip, and the second message is sent out by the tested slave chip;
the second calculation module is used for obtaining the time when the second message leaves the tested slave chip and the time when the second message reaches the tested master chip according to the second data;
The verification module is used for obtaining a first time difference according to the time when the first message leaves the tested master chip, the time when the first message reaches the tested slave chip and the time when the second message leaves the tested slave chip, and determining a clock verification result between the tested master chip and the tested slave chip according to the first time difference.
8. The chip is characterized by comprising a tested master chip and a tested slave chip;
the measured master chip or the measured slave chip is used for acquiring time data between the measured master chip and the measured slave chip and obtaining a clock verification result between the measured master chip and the measured slave chip according to the time data;
the time data comprises first timing information and first hardware time of the tested master chip when the tested master chip sends a first message to the tested slave chip, and second timing information, second hardware time and first time stamp information of the tested slave chip when the tested slave chip receives the first message; and when the tested slave chip sends a second message to the tested master chip, third timing information and third hardware time of the tested slave chip, and when the tested master chip receives the second message, fourth timing information, fourth hardware time and second timestamp information of the tested master chip.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor runs the computer program to implement the method of any one of claims 3-6.
10. A computer readable storage medium having stored thereon a computer program, wherein the program is executed by a processor to implement the method of any of claims 3-6.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117873944A (en) * | 2024-03-13 | 2024-04-12 | 深圳曦华科技有限公司 | Delay information determining method, delay information determining device, computer equipment and storage medium |
| CN118509334A (en) * | 2024-07-18 | 2024-08-16 | 常州楠菲微电子有限公司 | Time stamp precision verification device and method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117873944A (en) * | 2024-03-13 | 2024-04-12 | 深圳曦华科技有限公司 | Delay information determining method, delay information determining device, computer equipment and storage medium |
| CN118509334A (en) * | 2024-07-18 | 2024-08-16 | 常州楠菲微电子有限公司 | Time stamp precision verification device and method |
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