CN108120917A - Test clock circuit determines method and device - Google Patents
Test clock circuit determines method and device Download PDFInfo
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- CN108120917A CN108120917A CN201611075594.8A CN201611075594A CN108120917A CN 108120917 A CN108120917 A CN 108120917A CN 201611075594 A CN201611075594 A CN 201611075594A CN 108120917 A CN108120917 A CN 108120917A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
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Abstract
The embodiment of the invention discloses a kind of test clock circuits to determine method and device, the described method includes：Circuit is grouped and obtains test grouping；All circuits of one test grouping use same test clock；The point of addition of multiplexer unit is determined according to the test grouping, and the multiplexer unit is added in the point of addition；Wherein, the multiplexer unit is used to select the test signal or functional clock and is grouped the test signal or functional clock the input test of selection；According to test clock balance policy and the maximum strategy of common path, determine that the test clock inputs the bifurcation site of different transmission path in a test grouping；Wherein, the test clock balance policy be used for make a test clock a plurality of transmission path propagation delay time difference within a preset range；Common path of the maximum strategy of the common path for a test clock to be made to pass through when passing through a plurality of transmission path maximizes.
Description
Technical field
The present invention relates to circuit fields more particularly to a kind of test clock circuit to determine method and device.
Background technology
Chip internal there are a large amount of cross clock domains asynchronous circuit, and when persistent fault is tested, these cross clock domains
Asynchronous circuit is converted into synchronous path, thus there are substantial amounts of sequential fault paths to need to repair.
There are following some for the scheme of current Testability Design (Design for Testability, DFT) clock
Defect：Full chip equalization is made to low speed test clock, causes clock tree delays big.By so definite design circuit, make real
It, can not be as the perfect balance in circuit determination process, so as to cause actual circuit due to process deviation problem after the circuit of border
The piece upper deviation (On Chip Variation, OCV) it is very big.
In addition, OCV is excessive will to be present with substantial amounts of sequential fault path.It, can by the Buffer insertion on data path
To repair part sequential fault, but chip area can be increased；Some sequential fault path recovery not, this part road
Footpath cannot be tested, and can reduce the test coverage of chip.
The content of the invention
In view of this, an embodiment of the present invention is intended to provide a kind of test clock circuits to determine method and device, at least partly
It solves the above problems
In order to achieve the above objectives, the technical proposal of the invention is realized in this way：
First aspect of the embodiment of the present invention provides a kind of test clock circuit and determines method, including：
Acquisition test grouping is grouped to circuit, wherein, all circuits that a test is grouped use same
Test clock；
The point of addition of multiplexer unit is determined according to the test grouping, and it is described more in point of addition addition
Road Multiplexing Unit；Wherein, the multiplexer unit is for selecting the test signal or functional clock and will be described in selection
Test signal or the functional clock input test grouping；
According to test clock balance policy and the maximum strategy of common path, determine that the test clock inputs a survey
The bifurcation site of different transmission path in examination grouping；Wherein, the test clock balance policy is used to that a test clock to be made to exist
The propagation delay time difference of a plurality of transmission path is within a preset range；The maximum strategy of the common path is used to make described in one
Test clock passes through the common path passed through during a plurality of transmission path and maximizes.
Based on said program, described be grouped to circuit obtains test grouping, including at least one of：
It is grouped according to the relation between clock domain, obtains the test grouping；
It is grouped according to circuit scale, obtains the test grouping；
It is grouped according to the interaction path between disparate modules, obtains test grouping；
It is grouped according to the position relationship between module, obtains test grouping.
Based on said program, the relation according between clock domain is grouped, and obtains the test grouping, including：
The module that different functional clocks is covered is divided into different test groupings.
It is described to be grouped according to circuit scale based on said program, the test grouping is obtained, including：
When a module includes the use of the submodule of difference in functionality clock, and the scale of the module is more than size threshold
When, the submodule for using different functional clocks is grouped, obtains at least two test groupings.
Based on said program, the interaction path according between disparate modules is grouped, and obtains test grouping, bag
It includes：
Two modules that interaction path number is more than to the first preset number are divided into a test grouping；
And/or
Interaction path number less than the second preset number and is assigned into different institutes using two modules of difference in functionality clock
State test grouping.
Based on said program, the position relationship according between module is grouped, and obtains test grouping, including：
When the distance between two modules are more than the first pre-determined distance, described two modules are assigned to the different surveys
Examination grouping；
And/or
When the distance between two modules are less than the second pre-determined distance, described two modules are assigned into the same survey
Examination grouping.
Based on said program, after the test grouping is obtained, the method further includes：
It is grouped according to the test, increases the buffer for marking the test clock on circuit.
Second aspect of the embodiment of the present invention provides a kind of test clock circuit determining device, including：
Grouped element obtains test grouping for being grouped to circuit；Wherein, all circuits of a test grouping make
With same test clock；
Adding device, for determining the point of addition of multiplexer unit according to the test grouping, and in the addition
Add the multiplexer unit in position；Wherein, the multiplexer unit is used to select the test signal or functional clock
And the test signal or functional clock the input test of selection are grouped；
Determination unit, for according to test clock balance policy and the maximum strategy of common path, determining the test clock
The bifurcation site of different transmission path in the test grouping of input one；Wherein, the test clock balance policy is used to make
One test clock a plurality of transmission path propagation delay time difference within a preset range；The maximum strategy of the common path
Common path for a test clock to be made to pass through when passing through a plurality of transmission path maximizes.
Based on said program, the grouped element specifically for being grouped according to the relation between clock domain, obtains institute
State test grouping；And/or be grouped according to circuit scale, obtain the test grouping；And/or according between disparate modules
Interaction path be grouped, obtain test grouping；And/or be grouped according to the position relationship between module, it is tested
Grouping.
Based on said program, the grouped element, specifically for the module for covering different functional clocks, by two institutes
It states module and is divided into different test groupings.
Based on said program, the grouped element, specifically for including the use of the son of difference in functionality clock when a module
Module, and the scale of the module be more than size threshold when, the submodule for using different functional clocks is grouped, obtain
At least two test groupings.
Based on said program, the grouped element, specifically for interaction path number is more than two of the first preset number
Module is divided into a test grouping；And/or interaction path number less than the second preset number and is used into difference in functionality clock
Two modules, assign to different test groupings.
Based on said program, the grouped element, specifically for when the distance between two modules be more than first it is default away from
From when, described two modules are assigned into the different test and are grouped；And/or when the distance between two modules are less than second
During pre-determined distance, described two modules are assigned into the same test and are grouped.
Based on said program, described device further includes：
Indexing unit marks for after the test grouping is obtained, being grouped in increase on circuit according to the test
The buffer of the test clock.
Test clock circuit provided in an embodiment of the present invention determines method and device, when progress test clock determines, meeting
It carries out the multiple tests of circuit grouping acquisition to be grouped, the circuit in a test grouping uses same test clock, and is determining
It, will be according to test clock balance policy and common path most when test clock is input to the different transmission path of test grouping
Big strategy so that the common path that the test clock in a test grouping passes through in different transmission path maximizes, so as to
The transmission in not common path is reduced, it, should so as to reduce so as to reduce because delay inequality is big caused by not common path transmission the problem of
Use the phenomenon that OVC on actual circuit is big；And because test grouping determines that OVC reduces, and then reduce sequential and break rules,
And the number for the buffer introduced that breaks rules further for sequential to be repaired, so as to reduce the scale of entire chip, so as to subtract
Chip area is lacked.At the same time, reduce because what can not partly be repaired can not survey path, so as to reduce because sequential breaks rules
The phenomenon that caused diminution coverage of test clock and low test coverage.Therefore test clock provided in an embodiment of the present invention
Circuit determines method and device, has the characteristics of OCV is small, and test coverage is high and chip area is small.
Description of the drawings
Fig. 1 is the flow diagram that a kind of test clock circuit provided in an embodiment of the present invention determines method；
Fig. 2 is a kind of structure diagram of test clock circuit determining device provided in an embodiment of the present invention；
Fig. 3 is the flow diagram that another test clock circuit provided in an embodiment of the present invention determines method；
Fig. 4 to Fig. 9 is the grouping schematic diagram of test grouping provided in an embodiment of the present invention；
Figure 10 is the schematic diagram of test clock circuit provided in an embodiment of the present invention；
Figure 11 is based on obtaining with carrying out test clock circuit design on the same functional clock circuits of Figure 10 for existing method
Circuit diagram.
Specific embodiment
Technical scheme is further elaborated below in conjunction with Figure of description and specific embodiment.
As shown in Figure 1, the present embodiment provides a kind of test clock circuits to determine method, including：
Step S110：Circuit is grouped and obtains test grouping；All circuits of one test grouping use same
Test clock；
Step S120：The point of addition of multiplexer unit is determined according to the test grouping, and in the point of addition
Add the multiplexer unit；Wherein, the multiplexer unit is used to that the test signal or functional clock to be selected to input
The test grouping；
Step S130：According to test clock balance policy and the maximum strategy of common path, the test clock input is determined
The bifurcation site of different transmission path in one test grouping；Wherein, the test clock balance policy is used to make one
Test clock a plurality of transmission path propagation delay time difference within a preset range；The common path maximum strategy is used for
Maximize the common path that a test clock passes through when passing through a plurality of transmission path.
The test clock circuit determines that method can be referred to as test clock circuit design method again.The functional clock can
Work clock after being determined for circuit, the test clock are the clock measured to circuit.
The transmission path is input port to the path between output port in the present embodiment；Two transmission paths it
Between at least part it is different.The transmission input port of multiple transmission paths in a usual test grouping is identical, still
Output port is different.For example, include transmission path A and transmission path B in a test grouping；Transmission path A and transmission
B some path in path is shared, and another part is that separated, shared part is referred to as the common path, is separated
Part be referred to as not common path.In the present embodiment again input test clock when, can follow the test clock public
Path is most talked about, like this so that the logic gate on transmission path A and transmission path B shared path and path as far as possible,
On the one hand the use of gate circuit can be reduced, on the other hand since the common path of test clock process is longer, the non-public affairs of process
Path is shorter altogether, so as to which the transmission time delay difference caused by not common path is with regard to smaller, therefore can reduce OVC.
The step S110 is is grouped circuit, for example, these circuits include many modules, the division of these modules
Be based on function or based on physical distance, circuit has been divided many modules in a word, between these modules or
Circuit in module is grouped.
The grouping of the step S110 may include, carries out circuit grouping according to the covering of functional clock, obtains the test
Grouping.The circuit of the covering of same functional clock under normal conditions can be assigned in a test grouping, will not assign to two surveys
In examination grouping.The circuit of different functional clock coverings may assign to a test grouping, can also assign to different tests
In grouping, this may be decided by the other parameter of circuit, for example, the circuit scale of two different functional clock coverings.Here
Circuit scale can refer to：Interaction path between the number and/or logic gate of the logic gate that module includes etc..
The test clock that one test grouping uses, i.e., the test clock that all circuits pass through in a test grouping,
From same test clock.In the step s 120, addition multiplexer unit is grouped according to test.
The usual multiplexer unit includes two inputs and an output, an input for input test clock,
Another input is carrying out for input function clock, the output for exporting the test clock or the functional clock
During test, the multiplexer unit will select to export the test clock, and when circuit works normally, the multiplexing is single
Member will select output function clock, so that circuit is worked normally based on functional clock.It therefore in the present embodiment will be according to test point
Group determines the point of addition of multiplexer unit.For example, a test grouping includes an input, multiple test outputs；Usually
The number of the multiplexer unit is equal with the number of the test output.And the point of addition of the multiplexer unit is
The test clock has respectively entered the fork in the road that different tests export corresponding different paths.
The point of addition of certain multiplexer unit, the also input with difference in functionality clock in the test grouping rise
Beginning position is related；For example, a test grouping includes the circuit of two functional clock coverings, this when, the test
When clock is input to the fork in the road of two functional clocks, the multichannel is set in the fork in the road of the circuit of difference in functionality clock covering
Multiplexing Unit can so realize difference in functionality clock and test clock, the selection in test and work.
In specific implementation, the step S120 may include：The multiplexer unit of difference test grouping adds respectively, together
One test grouping is added respectively using the multiplexer unit of the transmission path of difference in functionality clock.
In step s 130, when carrying out circuit design, not only need to follow test clock balance policy, it is also necessary to follow
The maximum strategy of common path.Like this, the common path that a test clock passes through in a test grouping is maximum, so as to
Not common path reduces, because the inconsistent generation test delay variation in not common path just reduces, it is clear that so determine
Circuit because common path more be applied in actual circuit, even if there is process deviation, as not common path subtracts
It is few, so as to reduce the delay that not common path generates, so as to achieve the effect that reduce OVC.
Due to having carried out circuit grouping in the present embodiment, test grouping, the survey that different test groupings uses are obtained
It is different to try clock, it is possible to reduce sequential breaks rules and increases the phenomenon that chip area is big because sequential breaks rules, and can reduce because of sequential
Coverage rate reduces phenomenon caused by fault can not repair.
In some embodiments, the step S110 may include at least one of：
It is grouped according to the relation between clock domain, obtains the test grouping；
It is grouped according to circuit scale, obtains the test grouping；
It is grouped according to the interaction path between disparate modules, obtains test grouping；
It is grouped according to the position relationship between module, obtains test grouping.
One clock domain can be that the circuit of a functional clock covering can be regarded as a clock domain, in the present embodiment may be used
It is grouped with the relation directly according to clock domain, for example, different clock domains can be divided into different test groupings or, be total to
A test grouping can be divided into the different clock-domains of same clock source.
The circuit scale can be determined according to the connection path between the number and logic gate of logic gate.One test point
The data of the logic gate for the circuit that group includes should not be excessive, also should not be too small, and too small to may result in test clock excessive or more
The problem of road Multiplexing Unit is excessive increases circuit cost；If excessive when may result in follow-up common path maximum strategy and meeting,
Test clock pass through common path on the whole for seldom, so as to influence OVC.
If there are many interaction path between two modules and the logic gate of two modules between connection it is very much, it is clear that this
Two modules it is in close relations, can assign in a test grouping, can be with if interaction seldom and uses different functional clocks
Different test groupings is assigned to, to reduce OVC as far as possible.
Specifically, the relation according between clock domain is grouped, and obtains the test grouping, including：
The module that different functional clocks is covered is divided into different test groupings.
Specifically, it is described to be grouped according to circuit scale, the test grouping is obtained, including：
When a module includes the use of the submodule of difference in functionality clock, and the scale of the module is more than size threshold
When, the submodule for using different functional clocks is grouped, obtains at least two test groupings.
Specifically such as, the interaction path according between disparate modules is grouped, and obtains test grouping, including：It will
Two modules that interaction path number is more than the first preset number are divided into a test grouping；It is and/or interaction path number is few
In the second preset number and using two modules of difference in functionality clock, different test groupings is assigned to.
Here the first preset number and second preset number is all preset threshold value, and usually described first is pre-
If number is more than second preset data.
Specifically such as, the position relationship according between module is grouped, and obtains test grouping, including：
When the distance between two modules are more than pre-determined distance, described two modules are assigned into the different test point
Group；
And/or
When the distance between two modules are less than the second pre-determined distance, described two modules are assigned into the same survey
Examination grouping.
Here distance can show distance, two module wide aparts on chip, it is clear that just for the position relationship
It is not necessary to using a test clock, different test clocks can be used；If distance of two modules on chip is close,
Obviously a test clock can be shared.The distance of distance can be by first pre-determined distance and the second pre-determined distance table
Show.First pre-determined distance is typically larger than second pre-determined distance.
In some embodiments, after the step S110, the method further includes：
It is grouped according to the test, increases the buffer for marking the test clock on circuit.
A usual test clock corresponds to a buffer, which is arranged to special marking；So
Subsequently facilitate in circuit design application process, according to the number for the buffer being marked, determine test clock number and
The coverage or distributing position of each test clock.
The buffer of the test clock is marked in the present embodiment, is generally arranged at the bifurcation site.This certain reality
Test clock different in example is applied, can be generated by same test clock source.The buffer is inserted into the present embodiment only
It need to perform, can be performed after the step S120 after the step S110, it can also be in the step S120
It performs before, the step of can specifically being set according to operational requirements, not limited in the embodiment of the present invention, set buffer
It is preferred that it can be located at before step S130.As further improvement of this embodiment, the buffer is preferably arranged on an institute
On the common path for stating test grouping, the convenient correspondence for subsequently checking the buffer and test clock.
As shown in Fig. 2, the present embodiment provides a kind of test clock circuit determining device, including：
Grouped element 110 obtains test grouping for being grouped to circuit；All circuits of one test grouping use
Same test clock；
Adding device 120 for determining the point of addition of multiplexer unit according to the test grouping, and adds described
Position is added to add the multiplexer unit；Wherein, the multiplexer unit is for when selecting the test signal or function
Clock, and the test signal or functional clock the input test of selection are grouped；
Determination unit 130, for maximum tactful according to test clock balance policy and common path, when determining the test
Clock inputs the bifurcation site of different transmission path in a test grouping；Wherein, the test clock balance policy is used for
Make a test clock a plurality of transmission path propagation delay time difference within a preset range；The common path maximum plan
Common path slightly for a test clock to be made to pass through when passing through a plurality of transmission path maximizes.
Test clock circuit determining device described in the present embodiment can be applied to the information processing apparatus in various electronic equipments
It puts, the electronic equipment can be desktop computer, laptop or tablet computer or various servers or cloud computing platform etc..
The grouped element 110, adding device 120 and the determination unit 130 can all correspond to the place in electronic equipment
Manage device or process circuit.The processor may include central processor CPU, Micro-processor MCV, digital signal processor DSP, should
With processor AP or programmable array PLC etc..The process circuit may include application-specific integrated circuit ASIC etc..The processor or
Process circuit can realize the function of above-mentioned unit by the execution of executable code.
Described device will carry out functional circuit in definite test clock circuit in the present embodiment, function electricity here
The circuit of some functions is is realized in road, for example, completing the circuit of one or more functions on chip.The test clock circuit is
For the circuit tested functional circuit.
In the present embodiment by testing the definite of grouping and based on test clock balance policy and common path maximum
Change strategy to determine test clock bifurcation site, the circuit so designed can be caused to be applied in actual circuit, there is OCV
Small, sequential repairs the characteristics of difficulty is small, test coverage is high and chip area is small.
In some embodiments, the grouped element 110, specifically for being grouped according to the relation between clock domain,
Obtain the test grouping；And/or be grouped according to circuit scale, obtain the test grouping；And/or according to different moulds
Interaction path between block is grouped, and obtains test grouping；And/or be grouped according to the position relationship between module, it obtains
Grouping must be tested.
How the grouped element 110 specifically carries out test grouping in the present embodiment, reference can be made in previous embodiment
Corresponding part.Relation of the clock domain between the corresponding clock domain of functional clock.
Specifically, the grouped element 110 specifically for the module for covering different functional clocks, is divided into different
Test grouping.
Again specifically, the grouped element 110, specifically for including the use of the submodule of difference in functionality clock when a module
Block, and the scale of the module be more than size threshold when, the submodule for using different functional clocks is grouped, be divided into
Few two test groupings.
In addition, the grouped element 110, specifically for interaction path number to be more than to two modules point of the first preset number
For a test grouping；And/or interaction path number less than the second preset number and is used into two of difference in functionality clock
Module assigns to different test groupings.
In certain embodiments, the grouped element 110, specifically for being more than first in advance when the distance between two modules
If apart from when, described two modules are assigned into the different test and are grouped；And/or when the distance between two modules are less than
During the second pre-determined distance, described two modules are assigned into the same test and are grouped.
Described device also introduces in the present embodiment：Indexing unit, after being grouped in the acquisition test, according to
The test is grouped in the buffer for increasing on circuit and marking the test clock.Here indexing unit, will be according to the survey
Examination grouping, increases the buffer for marking the test clock on circuit, thus subsequently when carrying out circuit identification, it can basis
The buffer of labeled test clock determines each test grouping, the information such as number of test clock.It is described in the present embodiment
Indexing unit can be specifically used for the Buffer Insertion to the bifurcation site, so subsequently can also be according to the buffering
Device determines the common path and not common path that test clock is passed through in a test grouping.
Several specific examples are provided below in conjunction with above-mentioned any embodiment：
Example one：
This example introduces a kind of DFT clock schemes and implementation method based on grouping strategy, to reduce OCV effects, reduces
Repair the difficulty of sequence problem.This example rationally designs DFT clock schemes according to the scale and realization method of Digital Logic, and
Low speed test clock is grouped, can effectively reduce OCV effects, is suitble to the design of large scale digital logic chip to need
It asks.
As shown in figure 3, the method that this example provides includes three parts：
S1：It is divided according to module, module scale, asynchronous paths quantity and Module implementations are grouped clock；
S2：Multiplexer unit is rationally inserted into according to grouping relation；
S3：Test clock tree integrates, first balanced to the test clock progress in test grouping when test clock tree is comprehensive, then
Test clock being grouped test carries out balanced.
Here asynchronous paths quantity is the quantity using the transmission path of difference in functionality clock.
The method specifically may include：
The first step is grouped according to the relation pair clock between the corresponding clock domain of functional clock：The survey of disparate modules
Examination clock is divided into different groups；Module can be further grouped when larger in inside modules, and interaction path is more
Submodule can be at same test grouping, and the few submodule of interaction path can be at different test groupings；In same module not
When relatively disperseing with submodule, the different test that be divided into of different submodules can be grouped.
Second step is inserted into the road multiplexer unit of test clock：Road multiplexer unit should be added in inside modules；No
Multiplexer unit with test grouping adds respectively；The road of the test clock of difference in functionality clock domain is more in same test grouping
Road Multiplexing Unit adds respectively.
3rd step, the test clock be grouped to the examination of each drive test on test clock, it is necessary to increased the buffering of test clock
Device (Buffer), is identified the test clock, and ending tool identifies after convenience.
4th step when carrying out clock tree synthesis, first carries out balanced, guarantor to the test clock in each test grouping group
The delay difference for demonstrate,proving test clock tree is as far as possible small；Then equilibrium is carried out to the test clock of different test groups, so that it is guaranteed that entire electricity
The equilibrium of the test clock on road.
Like this, using this exemplary method, it can effectively reduce the OCV of test clock, reduce test clock tree
Delay, reduce the difficulty for repairing sequence problem, improve chip testing coverage rate so as to reach, reduce the purpose of chip area.
Example two：
This example combines Fig. 3 to Figure 11, and concrete example illustrates the test clock circuit side of determining provided in an embodiment of the present invention
Method, including：
The first step：It is grouped acquisition test grouping；The basic principle of grouping has：
Disparate modules assign to different test groupings, as shown in figure 4, modules A and module B, have been divided into test point respectively
Group a and test grouping b；
When module is larger, the circuit of a module can be assigned to different test groupings, as shown in figure 5, by module C
It has been divided into test grouping c1 and test grouping c2；
The more submodule of interaction path or part are assigned into same test grouping, as shown in figure 5, module C includes portion
Divide C1, part C2, part C3 and part C4, wherein, the interaction path of part C1 and part C2 are more, the friendship of part C3 and part C4
Mutual path is more, and road is also interacted between other parts and is handed over less or without interaction path；According to the number of interaction path, by module C
Interior circuit has assigned to two test groupings, is test grouping c1 and test grouping c2 respectively, wherein test grouping c1 includes portion
Divide C1 and part C2；Test grouping c2 includes test grouping C3 and test grouping C4.
When the physical location of different piece is relatively scattered in same module, different test groupings can be assigned to, such as Fig. 6 institutes
Show, the physical location of part D1 and part D2 relatively, assign to the portion in same test grouping d1, module D in module D
The physical location for dividing D3 and part D4 relatively, assigns to same test grouping d2.
Next, being grouped according to test, multiplexer unit is inserted into.One end linkage function clock of multiplexer unit,
One end connecting test clock.Same test is grouped the corresponding test clock of clock and comes from same source.In order to give test clock
The comprehensive starting point that provides of tree on test clock path, it is necessary to increase buffer.
Fig. 7 is into Fig. 9, starting point of the buffer as test clock tree in the transmission path of test clock, the starting point pair
The synthesis of test clock tree in foregoing bifurcation site, should be carried out, ensures the equilibrium of test clock tree in test grouping.Then into
The full chip clock tree synthesis of row, ensures the full chip equalization of test clock.
In Fig. 7 into Fig. 9, logic gate is the multiplexer unit in dotted line frame, and black triangle expression is buffer.
What Figure 10 and Figure 11 corresponded to is the circuit of same functional clock, and Figure 10 is to utilize side provided in this embodiment
Method first carries out test grouping, then each test grouping test clock is set respectively, and follow test clock strategy and most
Big public path policy, determines the bifurcation site of test clock, and in bifurcation site Buffer insertion, in Fig. 10 slash shade
The small triangle represented is the buffer of the mark test clock.Obvious comparison chart 11, utilizes a test clock pair
Entire circuit is tested, it is clear that the common path that the test clock in a test grouping in Figure 10 is passed by be it is longer,
Not common transmission path is shorter, it is clear that can reduce OCV.
In several embodiments provided herein, it should be understood that disclosed device and method can pass through it
Its mode is realized.Apparatus embodiments described above are only schematical, for example, the division of the unit, is only
A kind of division of logic function can have other dividing mode, such as in actual implementation：Multiple units or component can combine or
It is desirably integrated into another system or some features can be ignored or does not perform.In addition, shown or discussed each composition portion
Point mutual coupling or direct-coupling or communication connection can be the INDIRECT COUPLINGs by some interfaces, equipment or unit
Or communication connection, can be electrical, mechanical or other forms.
The above-mentioned unit illustrated as separating component can be or may not be physically separate, be shown as unit
The component shown can be or may not be physical location, you can be located at a place, can also be distributed to multiple network lists
In member；Part or all of unit therein can be selected to realize the purpose of this embodiment scheme according to the actual needs.
In addition, each functional unit in various embodiments of the present invention can be fully integrated into a processing module, also may be used
To be each unit individually as a unit, can also two or more units integrate in a unit；It is above-mentioned
The form that hardware had both may be employed in integrated unit is realized, can also be realized in the form of hardware adds SFU software functional unit.
One of ordinary skill in the art will appreciate that：Realizing all or part of step of above method embodiment can pass through
The relevant hardware of program instruction is completed, and foregoing program can be stored in a computer read/write memory medium, the program
Upon execution, the step of execution includes above method embodiment；And foregoing storage medium includes：It is movable storage device, read-only
Memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disc or
The various media that can store program code such as person's CD.
The above description is merely a specific embodiment, but protection scope of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in change or replacement, should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (14)
1. a kind of test clock circuit determines method, which is characterized in that including：
Acquisition test grouping is grouped to circuit, wherein, all circuits of a test grouping use same test
Clock；
The point of addition of multiplexer unit is determined according to the test grouping, and adds the multichannel in the point of addition and answers
Use unit；Wherein, the multiplexer unit is for selecting the test signal or functional clock and by the test of selection
Signal or the functional clock input test grouping；
According to test clock balance policy and the maximum strategy of common path, determine that the test clock inputs a test point
The bifurcation site of different transmission path in group；Wherein, the test clock balance policy is used to make a test clock a plurality of
The propagation delay time difference of the transmission path is within a preset range；The maximum strategy of the common path is used to make a test
Clock passes through the common path passed through during a plurality of transmission path and maximizes.
2. according to the method described in claim 1, it is characterized in that,
Described be grouped to circuit obtains test grouping, including at least one of：
It is grouped according to the relation between clock domain, obtains the test grouping；
It is grouped according to circuit scale, obtains the test grouping；
It is grouped according to the interaction path between disparate modules, obtains test grouping；
It is grouped according to the position relationship between module, obtains test grouping.
3. according to the method described in claim 2, it is characterized in that,
The relation according between clock domain is grouped, and obtains the test grouping, including：
The module that different functional clocks is covered is divided into different test groupings.
4. according to the method described in claim 2, it is characterized in that,
It is described to be grouped according to circuit scale, the test grouping is obtained, including：
It is right when a module includes the use of the submodule of difference in functionality clock, and the scale of the module is more than size threshold
It is grouped using the submodule of different functional clocks, obtains at least two test groupings.
5. according to the method described in claim 2, it is characterized in that,
The interaction path according between disparate modules is grouped, and obtains test grouping, including：
Two modules that interaction path number is more than to the first preset number are divided into a test grouping；
And/or
Interaction path number less than the second preset number and is assigned into the different surveys using two modules of difference in functionality clock
Examination grouping.
6. according to the method described in claim 2, it is characterized in that,
The position relationship according between module is grouped, and obtains test grouping, including：
When the distance between two modules are more than the first pre-determined distance, described two modules are assigned into the different test point
Group；
And/or
When the distance between two modules are less than the second pre-determined distance, described two modules are assigned into the same test point
Group.
7. method according to any one of claims 1 to 6, which is characterized in that
After the test grouping is obtained, the method further includes：
It is grouped according to the test, increases the buffer for marking the test clock on circuit.
8. a kind of test clock circuit determining device, which is characterized in that including：
Grouped element obtains test grouping for being grouped to circuit, wherein, all circuits for testing grouping use same
One test clock；
Adding device, for determining the point of addition of multiplexer unit according to the test grouping, and in the point of addition
Add the multiplexer unit；Wherein, the multiplexer unit is used to select the test signal or functional clock and incite somebody to action
The test signal or functional clock input the test grouping of selection；
Determination unit, for according to test clock balance policy and the maximum strategy of common path, determining the test clock input
The bifurcation site of different transmission path in one test grouping；Wherein, the test clock balance policy is used to make one
Test clock a plurality of transmission path propagation delay time difference within a preset range；The common path maximum strategy is used for
Maximize the common path that a test clock passes through when passing through a plurality of transmission path.
9. device according to claim 8, which is characterized in that
The grouped element specifically for being grouped according to the relation between clock domain, obtains the test grouping；And/or
It is grouped according to circuit scale, obtains the test grouping；And/or divided according to the interaction path between disparate modules
Group obtains test grouping；And/or be grouped according to the position relationship between module, obtain test grouping.
10. device according to claim 9, which is characterized in that
The grouped element specifically for the module for covering different functional clocks, is divided into different test groupings.
11. device according to claim 9, which is characterized in that
The grouped element, specifically for including the use of the submodule of difference in functionality clock when a module, and the module
When scale is more than size threshold, the submodule for using different functional clocks is grouped, obtains at least two tests
Grouping.
12. device according to claim 9, which is characterized in that
The grouped element is divided into a survey specifically for two modules that interaction path number is more than to the first preset number
Examination grouping；And/or interaction path number is assigned to not less than the second preset number and using two modules of difference in functionality clock
Same test grouping.
13. device according to claim 9, which is characterized in that
The grouped element, specifically for when the distance between two modules be more than the first pre-determined distance when, by described two moulds
Block assigns to different test groupings；And/or when the distance between two modules are less than the second pre-determined distance, by described in
Two modules assign to the same test grouping.
14. according to claim 8 to 13 any one of them device, which is characterized in that
Described device further includes：
Indexing unit, for after the test grouping is obtained, being grouped according to the test on circuit described in increasing mark
The buffer of test clock.
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| CN115510779A (en) * | 2022-11-22 | 2022-12-23 | 飞腾信息技术有限公司 | Clock tree comprehensive processing method, device, equipment and medium based on chip design |
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