CN102323530A - Device and method for testing clock - Google Patents
Device and method for testing clock Download PDFInfo
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- CN102323530A CN102323530A CN201110138637A CN201110138637A CN102323530A CN 102323530 A CN102323530 A CN 102323530A CN 201110138637 A CN201110138637 A CN 201110138637A CN 201110138637 A CN201110138637 A CN 201110138637A CN 102323530 A CN102323530 A CN 102323530A
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Abstract
The invention provides a device and a method for testing a clock. The device comprises an upper frequency deviation clock circuit, a lower frequency deviation clock circuit, a voltage adjusting circuit and a gating switching circuit, wherein the upper frequency deviation clock circuit is used for generating an upper limit clock signal of which a frequency value is an upper limit value of a limited clock frequency limited by a chip to be tested; the lower frequency deviation clock circuit is used for generating a lower limit clock signal of which a frequency value is a lower limit value of a clock frequency limited by the chip to be tested; the voltage adjusting circuit is connected with the upper frequency deviation clock circuit and the lower frequency deviation clock circuit and is used for respectively adjusting the voltage magnitudes of the upper limit clock signal and the lower limit clock signal; and the gating switching circuit is connected with the frequency deviation clock circuit and the lower frequency deviation clock circuit and is used for providing one of the upper limit clock signal and the lower limit clock signal for the chip to be tested for testing the chip to be tested. Various limit clock signals can be provided by adopting the technical scheme of the invention, so that the chip to be tested can be tested under the limit clock condition, and further, can be tested more comprehensively.
Description
Technical field
The present invention relates to the clock test technology, relate in particular to a kind of test clock device and method of testing.
Background technology
The clock part that for various communication chips, is absolutely necessary, for example: the transmission of the synchrodata of various communication interfaces all be unable to do without clock.Usually, the clock of communication chip derives from the source clock of the peripheral input of communication chip, and the clock circuit through chip internal carries out producing after frequency division or the frequency multiplication.Communication chip has certain requirement to the voltage amplitude and the frequency range of clock, and when the voltage amplitude of clock and frequency were all in desired scope, communication chip can operate as normal.
For various communication chips, confirm that through the chip testing flow process quality of communication chip is one necessary program in the communication products manufacture process, and clock is absolutely necessary also in the chip testing process.Existing chip detecting method normally under the voltage amplitude and the condition of frequency in the desired scope of chip that guarantee clock, comes communication chip is carried out performance and functional test.
But, the performance the when performance of communication chip and function not only are embodied in its clock and are in the normal range of operation, the performance of communication chip under various clock maximum conditions also can reflect the performance and the function of this communication chip.Therefore, also need under the clock maximum conditions, performance and the function to communication chip test, become urgent problem in the chip testing process and how to produce the clock maximum conditions.
Summary of the invention
The present invention provides a kind of test clock device and method of testing, in order to clock limit test condition to be provided, more all sidedly the performance and the function of chip are tested.
The present invention provides a kind of test clock device, comprising:
Last frequency deviation clock circuit is used to produce the upper limit clock signal that frequency values is the higher limit of the clock frequency that chip to be measured limited;
Following frequency deviation clock circuit is used to produce the lower limit clock signal that frequency values is the lower limit of the clock frequency that said chip to be measured limited;
Voltage-regulating circuit is connected with said frequency deviation clock circuit down with the said frequency deviation clock circuit of going up, and is used for adjusting respectively the voltage amplitude of said upper limit clock signal and said lower limit clock signal;
The gating commutation circuit is connected with said frequency deviation clock circuit down with the said frequency deviation clock circuit of going up, and is used for that one of them offers said chip to be measured with said upper limit clock signal and said lower limit clock signal, so that said chip to be measured is tested.
The present invention provides a kind of method of testing of using test clock device provided by the invention, comprising:
Frequency deviation clock circuit or following frequency deviation clock circuit on the gating commutation circuit control gating; So that upper limit clock signal or lower limit clock signal to be provided to chip to be measured; The voltage-regulating circuit adjustment is by the clock circuit of said gating commutation circuit gating, to adjust the voltage amplitude of said upper limit clock signal or said lower limit clock signal;
Under the voltage amplitude that said upper limit clock signal or said lower limit clock signal are adjusted to, said chip to be measured is tested, and obtained test result.
Test clock device provided by the invention and method of testing; Produce upper limit clock signal and the lower limit clock signal that frequency is respectively the clock frequency upper lower limit value of chip qualification to be measured through last frequency deviation clock circuit and following frequency deviation clock circuit; And through frequency deviation clock circuit on the gating commutation circuit gating and one of following frequency deviation clock circuit; One of them offers chip to be measured with upper limit clock signal and lower limit clock signal; And then the voltage amplitude of the clock signal of the clock circuit of gating output is regulated through voltage-regulating circuit; Thereby various limit clock signals are provided, make and under the clock maximum conditions, to test, thereby chip more to be measured is tested chip to be measured.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do one to the accompanying drawing of required use in embodiment or the description of the Prior Art below introduces simply; Obviously, the accompanying drawing in describing below is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
The structural representation of the test clock device that Fig. 1 provides for one embodiment of the invention;
The structural representation of the test clock device that Fig. 2 provides for another embodiment of the present invention;
Fig. 3 A is the implementation structure synoptic diagram of the last frequency deviation clock circuit 11 that provides of one embodiment of the invention;
Fig. 3 B is the implementation structure synoptic diagram of the following frequency deviation clock circuit 12 that provides of one embodiment of the invention;
Fig. 3 C is the implementation structure synoptic diagram of the standard time clock circuit 15 that provides of one embodiment of the invention;
Fig. 3 D is the implementation structure synoptic diagram of the gating commutation circuit 14 that provides of one embodiment of the invention;
Fig. 3 E is the structural representation of the test clock device that provides of further embodiment of this invention;
The process flow diagram of the method for testing that Fig. 4 provides for one embodiment of the invention;
The process flow diagram of the method for testing that Fig. 5 provides for further embodiment of this invention.
Embodiment
For the purpose, technical scheme and the advantage that make the embodiment of the invention clearer; To combine the accompanying drawing in the embodiment of the invention below; Technical scheme in the embodiment of the invention is carried out clear, intactly description; Obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
The structural representation of the test clock device that Fig. 1 provides for one embodiment of the invention.As shown in Figure 1, the device of present embodiment comprises: go up frequency deviation clock circuit 11, following frequency deviation clock circuit 12, voltage-regulating circuit 13 and gating commutation circuit 14.
Last frequency deviation clock circuit 11 is used to produce frequency values and is the upper limit clock signal of the higher limit of the clock frequency that chip 10 to be measured limited.Following frequency deviation clock circuit 12 is used to produce frequency values and is the lower limit clock signal of the lower limit of the clock frequency that chip 10 to be measured limited.Voltage-regulating circuit 13 is connected with following frequency deviation clock circuit 12 with last frequency deviation clock circuit 11, is used for adjusting respectively the voltage amplitude of upper limit clock signal and lower limit clock signal.Gating commutation circuit 14 is connected with following frequency deviation clock circuit 12 with last frequency deviation clock circuit 11, is used for that one of them offers chip 10 to be measured with upper limit clock signal and lower limit clock signal, so that chip 10 to be measured is tested.
Usually, chip 10 is surveyed in every hospitality all can have certain requirement to its clock signal, and the most commonly voltage amplitude and the clock frequency deviation to clock signal has certain requirement.In digital circuit, have two kinds of logical zeros and 1, the level of expression 0 is called low level, and the level of expression 1 is called high level, and high level and low level in the digital circuit are called as logic level.The voltage amplitude of clock is meant the logic level of clock signal in digital circuit.For example: a communication chip to the requirement of its clock voltage of signals amplitude is: the low level scope arrives 0.8V for-0.3 volt (V); The high level scope is that 2.0V is to 3.6V; This just limited the low level amplitude lower limit (for example-0.3V) with its higher limit (for example 0.8V), and the lower limit of high level amplitude (for example 2.0V) and its higher limit (for example 3.6V).
Clock signal is according to certain voltage amplitude, the pulse signal that sends continuously at interval with certain hour.The time interval between the pulse signal is called the cycle, and the pulse signal number that will in the unit interval (for example 1 second), be produced is called frequency.The standard measure of quantity of frequency is hertz (Hz).Because clock signal also is a pulse signal; So also there is this characterisitic parameter of frequency in clock signal; And being meant in the actual realization of clock circuit, clock frequency deviation makes of the drift of clock circuit nominal frequency to both sides because of circuit devcie parameter difference, environmental difference; Clock frequency deviation possibly be just to squint, and also possibly be that negative bias moves.Wherein, clock frequency deviation=(clock actual frequency-clock nominal frequency)/clock nominal frequency * 10
6(100,000/several) (part per million; Abbreviate as: ppm).For example: a communication chip to the frequency deviation of its clock signal require for 25MHz+/-20ppm, this is 25MHz+20ppm with regard to the higher limit that has limited this communication chip clock frequency also, the lower limit of clock frequency is 25MHz-20ppm.
The test clock device of present embodiment is mainly used in chip 10 to be measured (mainly being meant communication chip) is carried out performance test, the more concrete clock maximum conditions that provide when chip 10 to be measured tested.Concrete; After chip to be measured 10 is confirmed, just can obtain the higher limit of the clock frequency that chip 10 to be measured limits, lower limit, voltage amplitude higher limit and the voltage amplitude lower limit etc. of clock frequency to the requirement (can in the chip handbook, provide usually) of its clock signal according to chip 10 to be measured.And the last frequency deviation clock circuit 11 of present embodiment provides the frequency clock signal identical with the higher limit of clock frequency (being upper limit clock signal); Regulate through the voltage amplitude of 13 pairs of upper limit clock signals of voltage-regulating circuit again, can make the voltage amplitude of upper limit clock signal reach voltage amplitude higher limit or lower limit.Wherein, when the voltage amplitude of upper limit clock signal reaches the voltage amplitude higher limit, the clock signal of importing chip 10 to be measured will be the clock signal that voltage amplitude and clock frequency are maximum limit.When the voltage amplitude of upper limit clock signal reaches the voltage amplitude lower limit, the clock signal of importing chip 10 to be measured will be that voltage amplitude is that minimum limit value, clock frequency are the clock signal of maximum limit.
Further; The following frequency deviation clock circuit 12 of present embodiment provides the frequency clock signal identical with the lower limit of clock frequency (being the lower limit clock signal); Regulate through the voltage amplitude of 13 pairs of lower limit clock signals of voltage-regulating circuit again, can make the voltage amplitude of lower limit clock signal reach voltage amplitude higher limit or lower limit.Wherein, when clock voltage of signals amplitude reaches the voltage amplitude higher limit in limited time instantly, the clock signal of importing chip 10 to be measured will be that voltage amplitude is the clock signal that maximum limit, clock frequency are minimum limit value.When clock voltage of signals amplitude reaches the voltage amplitude lower limit in limited time instantly, the clock signal of importing chip 10 to be measured will be the clock signal that voltage amplitude and clock frequency are minimum limit value.
Based on above-mentioned; The test clock device of present embodiment is through frequency deviation clock circuit 11 and following frequency deviation clock circuit 12 on the gating commutation circuit 14 difference gatings; Respectively upper limit clock signal (comprising that voltage amplitude is respectively the upper limit clock signal of voltage amplitude maximal value and voltage amplitude minimum value) and lower limit clock signal (comprising that voltage amplitude is respectively the lower limit clock signal of voltage amplitude maximal value and voltage amplitude minimum value) are offered chip 10 to be measured; Reaching the purpose that limit clock test condition is provided to chip 10 to be measured, and then make and chip more to be measured is tested.
By above-mentioned visible; The test clock device of present embodiment; Through last frequency deviation clock circuit, following frequency deviation clock circuit, voltage-regulating circuit and gating commutation circuit various limit clock signals can be provided; Make and under limit clock condition, to test, realize the purpose of more comprehensively chip to be measured being tested chip to be measured.
The structural representation of the test clock device that Fig. 2 provides for another embodiment of the present invention.Present embodiment is based on realization embodiment illustrated in fig. 1, and is as shown in Figure 2, and the test clock device of present embodiment also comprises: standard time clock circuit 15.
Standard time clock circuit 15 is connected with gating commutation circuit 14, is used to produce the standard clock signal of frequency values in the clock frequency normal range that chip 10 to be measured is limited.Wherein, Clock frequency value between the lower limit of the higher limit of clock frequency and clock frequency can be considered the clock frequency normal range; For example: suppose a communication chip to the frequency deviation of its clock signal require for 25MHz+/-20ppm; Then the higher limit of this communication chip clock frequency is 25MHz+20ppm; The lower limit of clock frequency is 25MHz-20ppm, and the frequency values between 25MHz-20ppm and 25MHz+20ppm is the normal range of the desired clock frequency of this communication chip.In this was given an example, the standard time clock circuit 15 of present embodiment was used to produce the clock signal (be standard clock signal) of frequency values between 25MHz-20ppm and 25MHz+20ppm.Further specify; The standard time clock circuit 15 of present embodiment is clock on the plate of various communication chips; The voltage amplitude of the standard clock signal that it is exported between voltage amplitude higher limit and voltage amplitude lower limit, i.e. the required voltage amplitude of communication chip operate as normal.
Further, the gating commutation circuit 14 of present embodiment will be used for that one of them offers chip 10 to be measured with the standard clock signal of the lower limit clock signal of the upper limit clock signal of last frequency deviation clock circuit 11 outputs, frequency deviation clock circuit 12 outputs down and 15 outputs of standard time clock circuit.
The test clock device of present embodiment is except providing to chip to be measured the limit clock condition; Can also standard clock signal be provided to chip to be measured, make and to accomplish simultaneously performance and the functional test of chip to be measured under various clock conditions through the test clock device of present embodiment.Promptly adopt the test clock device of present embodiment that chip to be measured is carried out performance and functional test, can simplify test operation, improve testing efficiency.
Further, the standard time clock circuit 15 of present embodiment can also be connected with voltage-regulating circuit 13.Like this; Voltage-regulating circuit 13 can be regulated standard time clock circuit 15; Except providing the standard clock signal of voltage amplitude in normal range to chip 10 to be measured; Can also provide frequency values in normal range and voltage amplitude is the standard clock signal of voltage amplitude higher limit or lower limit, under this clock signal, chip 10 to be measured is done further test, the test performance when further improving test chip 10 to be measured.
Fig. 3 A is the implementation structure synoptic diagram of the last frequency deviation clock circuit 11 that provides of one embodiment of the invention.Shown in Fig. 3 A, the last frequency deviation clock circuit 11 of present embodiment comprises: go up frequency deviation crystal oscillator chip 111, first pull-up resistor 112, first filter capacitor 113 and second filter capacitor 114.Wherein, first filter capacitor 113 and second filter capacitor 114 constitute the first filtering electronic circuit, but are not limited to this.
Wherein, the crystal oscillator frequency of last frequency deviation crystal oscillator chip 111 is the higher limit of the clock frequency that limited of chip 10 to be measured.Shown in Fig. 3 A, last frequency deviation crystal oscillator chip 111 comprises four pins, is respectively drawing pin DOWN1 on first, the first power pins VCC1, the first clock output pin CLK1 and the first ground pin GND1.Drawing pin DOWN1 is the output enable control pin of last frequency deviation crystal oscillator chip 111 on first, on first drawing pin DOWN1 by unsettled or on move the first power pins VCC1 to and all can make frequency deviation crystal oscillator chip 111 effectively export upper limit clock signals.The first power pins VCC1 is the power supply input pin of last frequency deviation crystal oscillator chip 111, is used to receive external voltage signal.
Concrete, first pull-up resistor 112 is connected on first between the drawing pin DOWN1 and the first power pins VCC1, is used for drawing pin DOWN1 on first is pulled to the first power pins VCC1; Wherein according to the difference of last frequency deviation crystal oscillator chip 111, the resistance of first pull-up resistor 112 can be different, and for example: first pull-up resistor 112 can be 4700 ohm resistance.First filter capacitor 113 and second filter capacitor 114 are parallel between the first power pins VCC1 and the first ground pin GND1, in order to the driving voltage on the first power pins VCC1 is carried out filtering when last frequency deviation crystal oscillator chip 111 starting of oscillations; Wherein, appearance value and the number of can adaptability selecting filter capacitor according to concrete filtering requirements.Voltage-regulating circuit 13 is connected with the first power pins VCC1; Be used for upwards that frequency deviation crystal oscillator chip 111 provides driving voltage, and the size of the driving voltage through this changes self output reaches the purpose of regulating the voltage amplitude of going up the upper limit clock signal that frequency deviation clock circuit 11 exports.Wherein, the first clock output pin CLK1 is the upper limit clock signal output terminal of frequency deviation clock circuit 11, and gating commutation circuit 14 is connected with the first clock output pin CLK1, is used to receive upper limit clock signal.In the present embodiment, selected crystal oscillator chip itself does not have driving voltage, is used for obtaining driving voltage through voltage-regulating circuit 13, and promptly voltage-regulating circuit 13 also has the effect that the frequency deviation crystal oscillator chip 111 that makes progress provides driving voltage.
In this explanation, the various crystal oscillator chips that every crystal oscillator frequency can satisfy the higher limit of the clock frequency that chip 10 to be measured limited all can be used as the last frequency deviation crystal oscillator chip 111 of present embodiment.Because the implementation structure of different crystal oscillator chips is different, its peripheral circuit is also different, but it realizes that principle is basic identical.
It is simple that the mode that present embodiment adopts the crystal oscillator chip to realize going up the frequency deviation clock circuit has an implementation structure, the crystal oscillator frequency accuracy advantage of higher that provides.
Fig. 3 B is the implementation structure synoptic diagram of the following frequency deviation clock circuit 12 that provides of one embodiment of the invention.Shown in Fig. 3 B, the following frequency deviation clock circuit 12 of present embodiment comprises: following frequency deviation crystal oscillator chip 121, second pull-up resistor 122, the 3rd filter capacitor 123 and the 4th filter capacitor 124.Wherein, the 3rd filter capacitor 123 and the 4th filter capacitor 124 constitute the second filtering electronic circuit, but are not limited to this.
Wherein, the crystal oscillator frequency of following frequency deviation crystal oscillator chip 121 is the lower limit of the clock frequency that limited of chip 10 to be measured.Shown in Fig. 3 B, following frequency deviation crystal oscillator chip 121 comprises four pins, is respectively drawing pin DOWN2 on second, second source pin VCC2, second clock output pin CLK2 and the second ground pin GND2.Drawing pin DOWN2 is the following output enable control pin of frequency deviation crystal oscillator chip 121 on second, on second drawing pin DOWN2 by unsettled or on move second source pin VCC2 to and all can make down frequency deviation crystal oscillator chip 121 effective bottoming clock signals.Second source pin VCC2 is used to receive external voltage signal for the power supply input pin of following frequency deviation crystal oscillator chip 121.
Concrete, second pull-up resistor 122 is connected on second between the drawing pin DOWN2 and second source pin VCC2, is used for drawing pin DOWN2 on second is pulled to second source pin VCC2; Wherein according to the difference of following frequency deviation crystal oscillator chip 121, the resistance of second pull-up resistor 122 can be different, and for example: second pull-up resistor 122 can be 4700 ohm resistance.The 3rd filter capacitor 123 and the 4th filter capacitor 124 are parallel between the second source pin VCC2 and the second ground pin GND2, in order to when descending 121 starting of oscillations of frequency deviation crystal oscillator chip, the driving voltage on the second source pin VCC2 is carried out filtering; Wherein, appearance value and the number of can adaptability selecting filter capacitor according to concrete filtering requirements.Voltage-regulating circuit 13 is connected with second source pin VCC2; Being used for downward frequency deviation crystal oscillator chip 121 provides driving voltage, and reaches the adjusting purpose of the voltage amplitude of the lower limit clock signal of frequency deviation clock circuit 12 outputs down through the size of regulating the driving voltage of self exporting.Wherein, second clock output pin CLK2 is down the lower limit clock signal output terminal of frequency deviation clock circuit 12, and gating commutation circuit 14 is connected with second clock output pin CLK2, is used to receive the lower limit clock signal.In the present embodiment, selected crystal oscillator chip itself does not have driving voltage, is used for obtaining driving voltage through voltage-regulating circuit 13, and promptly voltage-regulating circuit 13 also has the effect that downward frequency deviation crystal oscillator chip 121 provides driving voltage.
In this explanation, the various crystal oscillator chips that every crystal oscillator frequency can satisfy the lower limit of the clock frequency that chip 10 to be measured limited all can be used as the following frequency deviation crystal oscillator chip 121 of present embodiment.Because the implementation structure of different crystal oscillator chips is different, its peripheral circuit is also different, but it realizes that principle is basic identical.
It is simple that present embodiment adopts the crystal oscillator chip to realize that down the mode of frequency deviation clock circuit has an implementation structure, the crystal oscillator frequency accuracy advantage of higher that provides.
Fig. 3 C is the implementation structure synoptic diagram of the standard time clock circuit 15 that provides of one embodiment of the invention.Shown in Fig. 3 C, the standard time clock circuit 15 of present embodiment comprises: standard crystal oscillator chip 151, the 3rd pull-up resistor 152, the 5th filter capacitor 153 and the 6th filter capacitor 154.Wherein, the 5th filter capacitor 153 and the 6th filter capacitor 154 constitute the 3rd filtering electronic circuit.
Wherein, the crystal oscillator frequency of standard crystal oscillator chip 151 is in the normal range of the clock frequency that chip 10 to be measured is limited.Shown in Fig. 3 C, standard crystal oscillator chip 151 comprises four pins, is respectively drawing pin DOWN3 on the 3rd, the 3rd power pins VCC3, the 3rd clock output pin CLK3 and three locations pin GND3.Drawing pin DOWN3 is the output enable control pin of standard crystal oscillator chip 151 on the 3rd, on the 3rd drawing pin DOWN3 by unsettled or on move the 3rd power pins VCC3 to and all can make standard crystal oscillator chip 151 effective outputting standard clock signals.The 3rd power pins VCC3 is the power supply input pin of standard crystal oscillator chip 151, is used to receive external voltage signal.
Concrete, the 3rd pull-up resistor 152 is connected on the 3rd between the drawing pin DOWN3 and the 3rd power pins VCC3, is used for drawing pin DOWN3 on the 3rd is pulled to the 3rd power pins VCC3; Wherein according to the difference of standard crystal oscillator chip 151, the resistance of the 3rd pull-up resistor 152 can be different, and for example: the 3rd pull-up resistor 152 can be 4700 ohm resistance.The 5th filter capacitor 153 and the 6th filter capacitor 154 are parallel between the 3rd power pins VCC3 and the three locations pin GND3, in order to the driving voltage on the 3rd power pins VCC3 is carried out filtering when 151 starting of oscillations of standard crystal oscillator chip; Wherein, appearance value and the number of can adaptability selecting filter capacitor according to concrete filtering requirements.The 3rd power pins VCC3 is connected with an external power source (not shown), is used for to standard crystal oscillator chip 151 driving voltage being provided; Because standard time clock circuit 15 can be clock on the plate of chip 10 to be measured, therefore, this external power source can adopt the power-supply system that voltage signal is provided to chip 10 to be measured.Wherein, the 3rd clock output pin CLK3 is the standard clock signal output terminal of standard time clock circuit 15, and gating commutation circuit 14 is connected with the 3rd clock output pin CLK3, is used for the acceptance criteria clock signal.In the present embodiment, the crystal oscillator chip of being chosen itself does not have driving voltage, needs the outside to drive, but is not limited to this.
In this explanation, the various crystal oscillator chips that every crystal oscillator frequency can satisfy the clock frequency normal range that chip 10 to be measured limited all can be used as the standard crystal oscillator chip 151 of present embodiment.Because the implementation structure of different crystal oscillator chips is different, its peripheral circuit is also different, but it realizes that principle is basic identical.In addition, except this embodiment, standard crystal oscillator chip 151 also can adopt other implementation.
Further; The external power source that is connected with the 3rd power pins VCC3 can be voltage-regulating circuit 13; Promptly the 3rd power pins VCC3 is connected with voltage-regulating circuit 13; Then voltage-regulating circuit 13 also can be adjusted standard time clock circuit 15, with the voltage amplitude of adjustment standard clock signal, thereby makes except provide frequency and voltage amplitude all the clock signal within the chip 10 required scopes to be measured to chip 10 to be measured; Can also provide frequency within chip 10 required scopes to be measured and voltage amplitude is respectively the clock signal of voltage amplitude higher limit or lower limit, chip 10 more to be measured is carried out performance and functional test.
It is simple that present embodiment adopts the crystal oscillator chip to realize that the mode of standard time clock circuit has an implementation structure, the crystal oscillator frequency accuracy advantage of higher that provides.
Fig. 3 D is the implementation structure synoptic diagram of the gating commutation circuit 14 that provides of one embodiment of the invention.Shown in Fig. 3 D, the gating commutation circuit 14 of present embodiment comprises: first input end 141, second input end 142, the 3rd input end 143, first output terminal 144, second output terminal 145, the 3rd output terminal 146 and select control end 147.
Wherein, first input end 141 is connected with last frequency deviation clock circuit 11, specifically is to be connected with the first clock output pin CLK1 shown in Fig. 3 A; In addition, first input end 141 is also through selecting control end 147 to be connected with first output terminal 144.Second input end 142 is connected with following frequency deviation clock circuit 12, specifically is to be connected with the CLK2 of second clock output pin shown in Fig. 3 B; In addition, second input end 142 is also through selecting control end 147 to be connected with second output terminal 145.The 3rd input end 143 is connected with standard time clock circuit 15, specifically is to be connected with the 3rd clock output pin CLK3 shown in Fig. 3 C; In addition, the 3rd input end 143 is also through selecting control end 147 to be connected with the 3rd output terminal 146.First output terminal 144, second output terminal 145 are connected with chip 10 to be measured respectively with the 3rd output terminal 146, and being used for provides test to use voltage signal to chip 10 to be measured.
Wherein, Select control end 147 to be used to control first input end 141 and first output terminal 144, second input end 142 and second output terminal 145 and the 3rd input end 143 and 146 one of them conducting of the 3rd output terminal, realize that promptly one of them offers chip 10 to be measured with upper limit clock signal, lower limit clock signal and standard clock signal.
In the present embodiment, select control end 147 control the 3rd input end 143 and 146 conductings of the 3rd output terminal under the default situations, with consistent with the original realization of product design.Wherein, the gating control signal can be exported by processor, also can adopt logical device output.
Fig. 3 E is the structural representation of the test clock device that provides of further embodiment of this invention.In the present embodiment, the test clock device specifically is made up of circuit structure shown in Fig. 3 A-Fig. 3 D, and its concrete annexation is not being given unnecessary details, and sees for details shown in Fig. 3 E.
The test clock device of present embodiment is realized through crystal oscillator chip and simple logical circuit; Only need carry out blocked operation between the different clocks source and can realize that the adjustment of amplitude and frequency deviation exports; Need be through not obtaining clock source on the plate; Through a large amount of processors and logical device the clock source is carried out exporting required voltage amplitude clock signal after the complicated digital processing again; Also need not carry out complicated editor to the clock source and change the clock signal that output needs frequency, therefore have circuit structure and realize simply the advantage that cost is low through a large amount of processors and logical device.
The process flow diagram of the method for testing that Fig. 4 provides for one embodiment of the invention.Present embodiment realizes that based on the test clock circuit shown in Fig. 1-Fig. 3 E is arbitrary the method for present embodiment comprises:
Frequency deviation clock circuit on step 401, the gating commutation circuit control gating provides upper limit clock signal to chip to be measured.
Concrete; Frequency deviation clock circuit on the gating commutation circuit gating; To go up the frequency deviation clock circuit and be connected, import chip to be measured with the upper limit clock signal that will go up the output of frequency deviation clock circuit, under the clock frequency upper bound condition, chip to be measured is carried out performance and functional test with chip to be measured.
The frequency deviation clock circuit is gone up in step 402, voltage-regulating circuit adjustment, with the voltage amplitude of adjustment upper limit clock signal.
Concrete; When needs are tested chip to be measured under limit clock condition, voltage-regulating circuit can with the voltage amplitude of upper limit clock signal adjust to the voltage amplitude higher limit that chip to be measured limits (for example: the higher limit of low level higher limit or high level) or lower limit (for example: the lower limit of low level lower limit or high level).
Step 403, under the voltage amplitude that upper limit clock signal is adjusted to, chip to be measured is tested, and obtained test result.
When voltage-regulating circuit is adjusted to the voltage amplitude higher limit that chip to be measured limits with the voltage amplitude of upper limit clock signal, can, voltage amplitude and clock frequency carry out performance and functional test under being the condition of maximum limit to chip to be measured.
When voltage-regulating circuit is adjusted to the voltage amplitude lower limit that chip to be measured limits with the voltage amplitude of upper limit clock signal, can be that minimum limit value and clock frequency are under the condition of maximum limit chip to be measured to be carried out performance and functional test at voltage amplitude.
Frequency deviation clock circuit under step 404, the gating commutation circuit control gating is to provide the lower limit clock signal to chip to be measured.
Further; Frequency deviation clock short circuit under the gating commutation circuit gating; The frequency deviation clock circuit is connected with chip to be measured, the lower limit clock signal of frequency deviation clock circuit output is down imported chip to be measured, under the clock frequency lower limit condition, chip to be measured is carried out performance and functional test.
Concrete, when needs were tested chip to be measured under limit clock condition, voltage-regulating circuit can be adjusted to voltage amplitude higher limit or the lower limit that chip to be measured limits with the voltage amplitude of lower limit clock signal.
When voltage-regulating circuit is adjusted to the voltage amplitude higher limit that chip to be measured limits with the voltage amplitude of lower limit clock signal, can be that maximum limit and clock frequency are under the condition of minimum limit value chip to be measured is carried out performance and functional test at voltage amplitude.
When voltage-regulating circuit is adjusted to the voltage amplitude lower limit that chip to be measured limits with the voltage amplitude of upper limit clock signal, can, voltage amplitude and clock frequency carry out performance and functional test under being the condition of minimum limit value to chip to be measured.
Wherein, in the present embodiment, the execution sequence of step 401-step 403 and step 404-step 406 is not done qualification.In addition, need explain also that the step 401-step 406 that present embodiment provides is merely a kind of the giving an example that chip to be measured is tested under limit clock condition, be not limited to this.For example: according to actual testing requirement, this limit clock test method can also only comprise above-mentioned steps 401-step 403, being to test under the condition of maximum limit in clock frequency.Again for example: according to actual testing requirement, this limit clock test method can also only comprise step 404-step 406, being to test under the condition of minimum limit value in clock frequency.
The method of testing of present embodiment, the test clock circuit that adopts the foregoing description to provide is realized, can under various limit clock conditions, carry out performance and functional test to chip to be measured, has the advantage that test process is simple, testing efficiency is high, testing cost is low.
Further, as shown in Figure 5, the method for testing of present embodiment also comprises:
Step 407, logical commutation circuit gating standard time clock circuit are to provide standard clock signal to chip to be measured.
Step 408, under the condition of standard clock signal, chip to be measured is tested, and is obtained test result.
Wherein, the execution sequence of above-mentioned steps 401-step 403, step 404-step 406, step and 407-step 408 is not done qualification.
Further; When the standard time clock circuit is connected with voltage-regulating circuit; After logical commutation circuit gating standard time clock circuit, voltage-regulating circuit adjustment standard time clock circuit is with the voltage amplitude of adjustment standard clock signal; And under the voltage amplitude that standard clock signal is adjusted to, chip to be measured is tested, and obtain test result.Wherein, the voltage amplitude that is adjusted to of standard clock signal mainly is meant higher limit or the lower limit that is adjusted to the voltage amplitude that chip to be measured limits.Based on this; Except can be all under the clock signal within the required scope of chip to be measured chip to be measured being tested at frequency and voltage amplitude, can also frequency within the required scope of chip to be measured and voltage amplitude be respectively under the clock signal of higher limit and lower limit of the voltage amplitude that chip to be measured limits chip to be measured carried out performance and functional test.
When the method for testing of present embodiment is carried out performance and functional test to chip to be measured under being implemented in limit clock condition; Can also under the normal clock condition, treat the side chip and test, have the advantage that test operation is simple, testing efficiency is high, testing cost is low.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can be accomplished through the relevant hardware of programmed instruction; Aforesaid program can be stored in the computer read/write memory medium; This program the step that comprises said method embodiment when carrying out; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
What should explain at last is: above embodiment is only in order to explaining technical scheme of the present invention, but not to its restriction; Although with reference to previous embodiment the present invention has been carried out detailed explanation, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these are revised or replacement, do not make the spirit and the scope of the essence disengaging various embodiments of the present invention technical scheme of relevant art scheme.
Claims (12)
1. a test clock device is characterized in that, comprising:
Last frequency deviation clock circuit is used to produce the upper limit clock signal that frequency values is the higher limit of the clock frequency that chip to be measured limited;
Following frequency deviation clock circuit is used to produce the lower limit clock signal that frequency values is the lower limit of the clock frequency that said chip to be measured limited;
Voltage-regulating circuit is connected with said frequency deviation clock circuit down with the said frequency deviation clock circuit of going up, and is used for adjusting respectively the voltage amplitude of said upper limit clock signal and said lower limit clock signal;
The gating commutation circuit is connected with said frequency deviation clock circuit down with the said frequency deviation clock circuit of going up, and is used for that one of them offers said chip to be measured with said upper limit clock signal and said lower limit clock signal, so that said chip to be measured is tested.
2. test clock device according to claim 1 is characterized in that, also comprises:
The standard time clock circuit is connected with said gating commutation circuit, is used to produce the standard clock signal of frequency values in the clock frequency normal range that said chip to be measured limited;
Said gating commutation circuit is used for also that one of them offers said chip to be measured with said upper limit clock signal, said lower limit clock signal and said standard clock signal, so that said chip to be measured is tested.
3. test clock device according to claim 1 and 2 is characterized in that, the said frequency deviation clock circuit of going up comprises: crystal oscillator frequency is last frequency deviation crystal oscillator chip, first pull-up resistor, the first filtering electronic circuit of the higher limit of said clock frequency;
The said frequency deviation crystal oscillator chip of going up comprises drawing pin on first, first power pins, the first clock output pin and the first ground pin; Said first pull-up resistor is connected on said first between the drawing pin and said first power pins; The said first filtering electronic circuit is connected between said first power pins and the said first ground pin; Said voltage-regulating circuit is connected with said first power pins; Said gating commutation circuit is connected with the said first clock output pin.
4. test clock device according to claim 1 and 2 is characterized in that, said frequency deviation clock circuit down comprises: crystal oscillator frequency is following frequency deviation crystal oscillator chip, second pull-up resistor, the second filtering electronic circuit of the lower limit of said clock frequency;
Said frequency deviation crystal oscillator chip down comprises drawing pin on second, second source pin, second clock output pin and the second ground pin; Said second pull-up resistor is connected on said second between the drawing pin and said second source pin; The said second filtering electronic circuit is connected between said second source pin and the said second ground pin; Said voltage-regulating circuit is connected with said second source pin; Said gating commutation circuit is connected with said second clock output pin.
5. test clock device according to claim 2 is characterized in that, said standard time clock circuit comprises: standard crystal oscillator chip, three pull-up resistor, the three filtering electronic circuit of crystal oscillator frequency in said clock frequency normal range;
Said standard crystal oscillator chip comprises drawing pin on the 3rd, the 3rd power pins, the 3rd clock output pin and three locations pin; Said the 3rd pull-up resistor is connected on the said the 3rd between the drawing pin and said the 3rd power pins; Said the 3rd filtering electronic circuit is connected between said the 3rd power pins and the said three locations pin; Said the 3rd power pins is used to receive external voltage signal; Said gating commutation circuit is connected with said the 3rd clock output pin.
6. test clock device according to claim 5 is characterized in that, said the 3rd power pins is connected with said voltage-regulating circuit.
7. according to claim 1 or 2 or 5 or 6 described test clock devices, it is characterized in that said gating commutation circuit is a gating switch.
8. according to claim 2 or 5 or 6 described test clock devices, it is characterized in that said gating commutation circuit comprises: first input end, second input end, the 3rd input end, first output terminal, second output terminal, the 3rd output terminal and selection control end;
Said first input end is connected with the said frequency deviation clock circuit of going up, and is connected with said first output terminal through said selection control end; Said second input end is connected with said frequency deviation clock circuit down, and is connected with said second output terminal through said selection control end; Said the 3rd input end is connected with said standard time clock circuit, and is connected with said the 3rd output terminal through said selection control end;
Said selection control end is used to control said first input end and said first output terminal, second input end and said second output terminal and said the 3rd input end and said one of them conducting of the 3rd output terminal.
9. the method for testing of each described test clock device of application rights requirement 1-8 is characterized in that, comprising:
Frequency deviation clock circuit or following frequency deviation clock circuit on the gating commutation circuit control gating; So that upper limit clock signal or lower limit clock signal to be provided to chip to be measured; The voltage-regulating circuit adjustment is by the clock circuit of said gating commutation circuit gating, to adjust the voltage amplitude of said upper limit clock signal or said lower limit clock signal;
Under the voltage amplitude that said upper limit clock signal or said lower limit clock signal are adjusted to, said chip to be measured is tested, and obtained test result.
10. method of testing according to claim 9; It is characterized in that; Frequency deviation clock circuit or following frequency deviation clock circuit on the said gating commutation circuit control gating; So that upper limit clock signal or lower limit clock signal to be provided to chip to be measured, voltage-regulating circuit is adjusted by the clock circuit of said gating commutation circuit gating, comprises with the voltage amplitude of adjusting said upper limit clock signal or said lower limit clock signal:
When said gating commutation circuit gating is said when going up the frequency deviation clock circuit; The said frequency deviation clock circuit of going up of said voltage-regulating circuit adjustment is adjusted to voltage amplitude higher limit or the voltage amplitude lower limit that said chip to be measured limits with the voltage amplitude of said upper limit clock signal;
When said time frequency deviation clock circuit of said gating commutation circuit gating; The said frequency deviation clock circuit down of said voltage-regulating circuit adjustment is adjusted to voltage amplitude higher limit or the voltage amplitude lower limit that said chip to be measured limits with the voltage amplitude of said lower limit clock signal.
11. according to claim 9 or 10 described method of testings, it is characterized in that, also comprise:
Said gating commutation circuit gating standard time clock circuit is to provide standard clock signal to said chip to be measured;
Under the condition of said standard clock signal, said chip to be measured is tested, and obtained test result.
12. according to claim 9 or 10 described method of testings, it is characterized in that, also comprise:
Said gating commutation circuit gating standard time clock circuit, to said chip to be measured standard clock signal to be provided, said voltage-regulating circuit is adjusted said standard time clock circuit, to adjust the voltage amplitude of said standard clock signal;
Under the voltage amplitude that said standard clock signal is adjusted to, said chip to be measured is tested, and obtained test result.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110138637.3A CN102323530B (en) | 2011-05-26 | 2011-05-26 | Device and method for testing clock |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110138637.3A CN102323530B (en) | 2011-05-26 | 2011-05-26 | Device and method for testing clock |
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| CN102323530B CN102323530B (en) | 2014-07-02 |
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| CN108120917A (en) * | 2016-11-29 | 2018-06-05 | 深圳市中兴微电子技术有限公司 | Test clock circuit determines method and device |
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| CN114895172A (en) * | 2022-05-10 | 2022-08-12 | 常超 | Chip testing method and system based on FPGA |
| CN115242192A (en) * | 2022-09-23 | 2022-10-25 | 深圳市磐鼎科技有限公司 | Frequency-adjustable multi-path differential clock output circuit and device |
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| CN108120917A (en) * | 2016-11-29 | 2018-06-05 | 深圳市中兴微电子技术有限公司 | Test clock circuit determines method and device |
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| CN111308330A (en) * | 2020-04-07 | 2020-06-19 | 华北水利水电大学 | FPGA DCM test system and method |
| CN114895172A (en) * | 2022-05-10 | 2022-08-12 | 常超 | Chip testing method and system based on FPGA |
| CN115242192A (en) * | 2022-09-23 | 2022-10-25 | 深圳市磐鼎科技有限公司 | Frequency-adjustable multi-path differential clock output circuit and device |
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| CN102323530B (en) | 2014-07-02 |
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