CN115242192A - Frequency-adjustable multi-path differential clock output circuit and device - Google Patents
Frequency-adjustable multi-path differential clock output circuit and device Download PDFInfo
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- CN115242192A CN115242192A CN202211161458.6A CN202211161458A CN115242192A CN 115242192 A CN115242192 A CN 115242192A CN 202211161458 A CN202211161458 A CN 202211161458A CN 115242192 A CN115242192 A CN 115242192A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
- H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
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Abstract
The invention discloses a frequency-adjustable multi-path differential clock output circuit and a device, wherein the circuit comprises: the clock output circuit generates a target differential clock signal according to the initial clock signal and the target frequency and outputs the target differential clock signal through a corresponding target output port. Compared with the prior art that the circuit can only output a single-path clock signal or a clock signal with nonadjustable clock frequency, the invention can not only provide multi-path differential clock signal output, but also adjust the clock frequency of each path of output clock signal according to the target frequency acquired by the frequency acquisition circuit, thereby simultaneously meeting the clock frequency requirements of different interfaces, not needing to configure a plurality of clock output circuits and reducing the hardware cost.
Description
Technical Field
The invention relates to the technical field of pulses, in particular to a frequency-adjustable multi-path differential clock output circuit and a frequency-adjustable multi-path differential clock output device.
Background
With the development of integrated circuits, the internal units of electronic devices have been increasingly developed to high precision and miniaturization, and thus microelectronic devices have been receiving more attention. The mainstream microelectronic device needs to realize function expansion through high-speed interfaces, and the functions of the high-speed interfaces need to be realized by means of differential clocks with different frequencies and different formats.
However, the existing differential clock output circuit generally only supports outputting a single clock signal, or the clock frequency of the output clock signal is not adjustable and has a single purpose, so in order to implement the function of each high-speed interface, a plurality of differential clock output circuits are required to be arranged in the microelectronic device in practical application, thereby causing the hardware expansion circuit of the microelectronic device to be generally complex and the hardware cost to be high.
The above is only for the purpose of assisting understanding of the technical aspects of the present invention, and does not represent an admission that the above is prior art.
Disclosure of Invention
The invention mainly aims to provide a frequency-adjustable multi-path differential clock output circuit and a frequency-adjustable multi-path differential clock output device, and aims to solve the technical problems that the existing clock output circuit can only provide single-path clock output or clock output with non-adjustable frequency, so that the existing microelectronic equipment hardware expansion circuit is complex in structure and high in hardware cost.
In order to achieve the above object, the present invention provides a frequency-adjustable multi-path differential clock output circuit, including: the device comprises an oscillating circuit, a frequency acquisition circuit and a clock output circuit;
the clock output circuit is respectively connected with the oscillating circuit and the frequency acquisition circuit;
the oscillating circuit is used for providing an initial clock signal for the clock output circuit;
the frequency acquisition circuit is used for acquiring a target frequency of a differential clock signal to be output and sending the target frequency to the clock output circuit;
and the clock output circuit is used for generating a target differential clock signal according to the initial clock signal and the target frequency and outputting the target differential clock signal through a corresponding target output port.
Optionally, the clock output circuit includes: the circuit comprises a main clock chip, a first resistor, a second resistor, a third resistor, a fourth resistor and an output port;
the main clock chip is respectively connected with the oscillating circuit and the frequency acquisition circuit;
a first end of the first resistor is connected with a first clock output pin of the master clock chip, and a second end of the first resistor is respectively connected with a first end of the third resistor and a first interface of the output port;
a first end of the second resistor is connected with a second clock output pin of the master clock chip, and a second end of the second resistor is respectively connected with a first end of the fourth resistor and a second interface of the output port;
the second end of the third resistor, the second end of the fourth resistor, the third interface of the output port, the fourth interface of the output port and the grounding pin of the master clock chip are all grounded.
Optionally, the oscillation circuit includes: the circuit comprises a crystal oscillator, a fifth resistor, a sixth resistor and a seventh resistor;
the first end of the crystal oscillator is respectively connected with the second end of the fifth resistor and the first end of the seventh resistor, and the first end of the fifth resistor is connected with a first crystal oscillator pin of the master clock chip;
the second end of the crystal oscillator is connected with a first crystal oscillator grounding pin of the master clock chip;
the third end of the crystal oscillator is respectively connected with the second end of the seventh resistor and the second end of the sixth resistor, and the first end of the sixth resistor is connected with a second crystal oscillator pin of the master clock chip;
and the fourth end of the crystal oscillator is connected with a second crystal oscillator grounding pin of the master clock chip.
Optionally, the frequency acquisition circuit includes: an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor and a data acquisition port;
the first end of the eighth resistor is connected with the first end of the data acquisition port, and the second end of the eighth resistor is respectively connected with the first end of the tenth resistor and a bus clock pin of a master clock chip;
and the first end of the ninth resistor is connected with the second end of the data acquisition port, and the second end of the ninth resistor is respectively connected with the first end of the eleventh resistor and a bus data pin of a master clock chip. (ii) a
Optionally, the multi-path differential clock output circuit further includes: a power supply circuit;
the power supply circuit is respectively connected with the frequency acquisition circuit and the clock output circuit;
and the power supply circuit is used for providing power supply voltage for the frequency acquisition circuit and the clock output circuit.
Optionally, the power supply circuit comprises: an overvoltage protection circuit and a power switching circuit;
the overvoltage protection circuit is respectively connected with a power supply and the power supply conversion circuit, and the power supply conversion circuit is respectively connected with the frequency acquisition circuit and the clock output circuit;
the overvoltage protection circuit is used for receiving power supply voltage and disconnecting the overvoltage protection circuit from the power supply conversion circuit when the power supply voltage exceeds a preset safety value;
the overvoltage protection circuit is also used for outputting the power supply voltage to the power supply conversion circuit when the power supply voltage does not exceed the preset safety value;
the power supply conversion circuit is used for converting the power supply voltage into a first voltage and a second voltage, transmitting the first voltage to the frequency acquisition circuit and the clock output circuit, and transmitting the second voltage to the clock output circuit.
Optionally, the overvoltage protection circuit comprises: twelfth to eighteenth resistors, first to second NMOS transistors, a first PMOS transistor and a first capacitor;
the grid electrode of the first NMOS tube is respectively connected with the first end of the twelfth resistor and the first end of the thirteenth resistor, the second end of the twelfth resistor is connected with the power supply circuit, and the second end of the thirteenth resistor and the source electrode of the first NMOS tube are both grounded;
a drain electrode of the first NMOS transistor is respectively connected to a first end of the fourteenth resistor, a first end of the fifteenth resistor, and a gate electrode of the second NMOS transistor, a second end of the fourteenth resistor is connected to the power circuit, and a second end of the fifteenth resistor and a source electrode of the second NMOS transistor are both grounded;
the drain electrode of the second NMOS tube is connected with the first end of the sixteenth resistor, the second end of the sixteenth resistor is respectively connected with the first end of the seventeenth resistor and the first end of the eighteenth resistor, and the second end of the seventeenth resistor is connected with the power circuit;
the second end of the eighteenth resistor is connected with the first end of the first capacitor and the grid electrode of the first PMOS tube respectively, the second end of the first capacitor and the source electrode of the first PMOS tube are connected with the power supply circuit, and the drain electrode of the first PMOS tube is connected with the power supply conversion circuit.
In addition, in order to achieve the above object, the present invention further provides a frequency-adjustable multi-way clock output device, which includes the frequency-adjustable multi-way differential clock output circuit as described above.
The invention discloses a frequency-adjustable multi-path differential clock output circuit and a device, wherein the circuit comprises: the clock output circuit is respectively connected with the oscillating circuit and the frequency acquisition circuit; the oscillation circuit provides an initial clock signal for the clock output circuit, the frequency acquisition circuit acquires the target frequency of the differential clock signal to be output and sends the target frequency to the clock output circuit, and the clock output circuit generates a target differential clock signal according to the initial clock signal and the target frequency and outputs the target differential clock signal through a corresponding target output port. Compared with the existing circuit which can only output a single-path clock signal or a clock signal with nonadjustable clock frequency, the invention can not only provide multi-path differential clock signal output, but also adjust the clock frequency of each path of output clock signal according to the target frequency acquired by the frequency acquisition circuit and output the clock frequency according to the corresponding target output port. Therefore, the invention can simultaneously meet the clock frequency requirements of different interfaces, does not need to arrange a plurality of clock output circuits, and effectively reduces the hardware cost.
Drawings
FIG. 1 is a functional block diagram of a first embodiment of a frequency adjustable multi-way differential clock output circuit according to the present invention;
FIG. 2 is a schematic circuit diagram of a clock output circuit in a first embodiment of a frequency-adjustable multi-way differential clock output circuit according to the present invention;
FIG. 3 is a schematic circuit diagram of an oscillating circuit in a first embodiment of the frequency-adjustable multi-way differential clock output circuit according to the present invention;
FIG. 4 is a schematic circuit diagram of a frequency acquisition circuit in a first embodiment of a frequency-adjustable multi-way differential clock output circuit according to the present invention;
FIG. 5 is a functional block diagram of a second embodiment of the multi-way differential clock output circuit of the present invention;
fig. 6 is a schematic circuit diagram of an overvoltage protection circuit in a second embodiment of the multi-channel differential clock output circuit according to the present invention.
The reference numbers illustrate:
the implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
The technical solutions of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments based on the embodiments of the present invention, and all embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that the descriptions relating to "first", "second", etc. in the embodiments of the present invention are only for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In addition, technical solutions between the embodiments may be combined with each other, but must be based on the realization of the technical solutions by a person skilled in the art, and when the technical solutions are contradictory to each other or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a functional block diagram of a first embodiment of a frequency-adjustable multi-way differential clock output circuit according to the present invention.
As shown in fig. 1, the frequency-adjustable multi-way differential clock output circuit of the present embodiment includes: an oscillation circuit 100, a frequency acquisition circuit 200, and a clock output circuit 300; the clock output circuit 300 is connected to the oscillation circuit 100 and the frequency acquisition circuit 200 respectively;
the clock output circuit 300 is configured to generate a target differential clock signal according to the initial clock signal and the target frequency, and output the target differential clock signal through a corresponding target output port.
It should be noted that the target frequency is an oscillation frequency of the output clock signal, which is usually 100MHz, and the target output port is a data output port that finally outputs the target frequency differential clock signal.
For ease of understanding, the description will be made with reference to fig. 2, but this solution is not limited thereto. Fig. 2 is a schematic circuit diagram of a clock output circuit 300 in a first embodiment of the frequency-adjustable multi-way differential clock output circuit of the present invention, wherein the clock output circuit 300 includes: the circuit comprises a main clock chip U1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and an output PORT PORT;
the master clock chip U1 is connected to the oscillation circuit 100 and the frequency acquisition circuit 200, respectively;
a first end of the first resistor R1 is connected to a first clock output pin OUTxP of the master clock chip U1, and a second end of the first resistor R1 is connected to a first end of the third resistor R3 and a first interface of the output PORT, respectively;
a first end of the second resistor R2 is connected to a second clock output pin OUTxN of the main clock chip U1, and a second end of the second resistor R2 is connected to a first end of the fourth resistor R4 and a second interface of the output PORT, respectively;
the second end of the third resistor R3, the second end of the fourth resistor R4, the third interface of the output PORT, the fourth interface of the output PORT, and the ground pin GND of the main clock chip U1 are all grounded.
It should be noted that the master clock chip U1 is connected to the oscillation circuit 100 through the first crystal oscillator pin X1, the second crystal oscillator pin X2, the first crystal oscillator ground pin X1G, and the second crystal oscillator ground pin X2G. The master clock chip U1 may copy a clock signal of one channel by frequency to generate a plurality of clock signals, and output the clock signals through corresponding output ports, and the master clock chip U1 may also implement frequency conversion to output clock signals of a plurality of different frequencies. In this embodiment, the first clock output pin OUTxP and the second clock output pin OUTxN correspond to one clock output, where x may be any integer from 1 to 10 and corresponds to the first to tenth clock outputs of the main clock chip U1. For example, if x is 3, the clock signal is output through the third path, and the corresponding output pins are OUT3P and OUT3N.
In addition, the voltage received by the power supply voltage pin VDD of the main clock chip U1 is the first voltage VDD _ AUCLK, the first voltage VDD _ AUCLK is a core voltage and is also a voltage of the input clock signal, the voltage received by the port power supply voltage pin VDDO of the main clock chip U1 is the second voltage VDD18_ IO, the second voltage VDD18_ IO corresponds to a voltage of the output clock signal, and the voltage value of the second voltage VDD18_ IO may be the same as or different from the voltage value of the first voltage VDD _ AUCLK, for example, the voltage value of the first voltage VDD _ AUCLK is 3.3V, and the voltage value of the second voltage VDD18_ IO may be selected from various voltages such as 3.3V, 2.5V, 1.8V, and the like for output.
The oscillation circuit 100 is configured to provide an initial clock signal for the clock output circuit 300.
It can be understood that the main clock chip U1 itself cannot generate a frequency source, and it can only copy, format convert, and level convert a clock signal, so that in this embodiment, a reference clock signal needs to be generated first, and the subsequent main clock chip U1 copies and converts the reference clock signal into multiple paths of differential clock signals with different frequencies, where the initial clock signal is the reference clock signal.
For ease of understanding, reference is made to fig. 3, which, however, does not limit the present solution. Fig. 3 is a schematic circuit diagram of an oscillating circuit 100 in a first embodiment of the frequency-adjustable multi-channel differential clock output circuit of the present invention, wherein the oscillating circuit 100 includes: crystal oscillator Y1, fifth resistor R5, sixth resistor R6 and seventh resistor R7.
As shown in fig. 3, the oscillation circuit 100 includes: the circuit comprises a crystal oscillator Y1, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7;
a first end of the crystal oscillator Y1 is connected to a second end of the fifth resistor R5 and a first end of the seventh resistor R7, respectively, and a first end of the fifth resistor R5 is connected to a first crystal oscillator pin X1 of the master clock chip U1;
the second end of the crystal oscillator Y1 is connected with a first crystal oscillator grounding pin X1G of the master clock chip U1;
a third end of the crystal oscillator Y1 is connected to a second end of the seventh resistor R7 and a second end of the sixth resistor R6, respectively, and a first end of the sixth resistor R6 is connected to a second crystal oscillator pin X2 of the master clock chip U1;
and the fourth end of the crystal oscillator Y1 is connected with a second crystal oscillator grounding pin X2G of the main clock chip U1.
It should be noted that the device for providing the initial clock signal in the oscillation circuit 100 of this embodiment may be a crystal oscillator Y1, and the crystal oscillator Y1 can generate an oscillation current in the circuit to generate an oscillation frequency, so that an accurate reference frequency or a highly stable clock signal can be provided, and the requirement of high precision of a high-speed interface can be met. Generally, the frequency generated by the crystal oscillator Y1 is not too high, the frequency of the initial clock signal in this embodiment may be 48MHz, and the initial clock signal may also be other frequencies in practical applications, which is not limited in this embodiment.
The frequency obtaining circuit 200 is configured to obtain a target frequency of a differential clock signal to be output, and send the target frequency to the clock output circuit 300;
it should be noted that the frequency obtaining circuit 200 communicates with the computing device through a data port, the computing device may be a device having functions of data processing, network communication, and circuit debugging program running, the data port is usually a USB interface or a DB-9 serial port, of course, other interfaces capable of transmitting data may also be used for communication, and the specific port type is not limited in this embodiment.
For convenience of understanding, the description is made with reference to fig. 4, but the present invention is not limited thereto. Fig. 4 is a schematic circuit diagram of a frequency acquisition circuit 200 in a first embodiment of the frequency-adjustable multi-channel differential clock output circuit of the present invention, where the frequency acquisition circuit 200 includes: an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and a DATA acquisition PORT DATA _ PORT;
a first end of the eighth resistor R8 is connected to a first end of the DATA acquisition PORT DATA _ PORT, and a second end of the eighth resistor R8 is connected to a first end of the tenth resistor R10 and a bus clock pin SCLK of the master clock chip U1, respectively;
a first end of the ninth resistor R9 is connected to a second end of the DATA obtaining PORT DATA _ PORT, and a second end of the ninth resistor R9 is connected to a first end of the eleventh resistor R11 and a bus clock pin SDAIO of the main clock chip U1, respectively.
It should be noted that, in the present embodiment, the clock configuration program of the computing device is obtained through the DATA obtaining PORT DATA _ PORT, the program DATA includes the target frequency and the target output PORT corresponding to the target frequency, and the target output PORT and the target frequency are transmitted to the clock output circuit 300.
In a specific implementation, after a target frequency and a target output port set in an operating program of the computing device are obtained through the USB interface, the target frequency and the target output port are transmitted to the clock output circuit 300, then the clock output circuit 300 multiplexes an initial differential clock signal generated by the crystal oscillator Y1 in the oscillation circuit 100 into multiple clock signals, and then adjusts one or more of the multiple clock signals into a differential clock signal having the same frequency as the target frequency, and outputs the differential clock signal through the target output port.
The embodiment discloses a frequency-adjustable multi-path differential clock output circuit, which comprises: the clock output circuit 300 is respectively connected with the oscillating circuit 100 and the frequency acquisition circuit 200; the oscillation circuit 100 provides an initial clock signal for the clock output circuit 300, the frequency obtaining circuit 200 obtains a target frequency of a differential clock signal to be output, and sends the target frequency to the clock output circuit 300, and the clock output circuit 300 generates a target differential clock signal according to the initial clock signal and the target frequency, and outputs the target differential clock signal through a corresponding target output port. Compared with the existing circuit that only can output a single-path clock signal or a clock signal with an unadjustable clock frequency, this embodiment can not only provide multi-path differential clock signal output, but also adjust the clock frequency of each path of output clock signal according to the target frequency obtained by the frequency obtaining circuit 200, and output the clock frequency according to the corresponding target output port. Therefore, the present embodiment can simultaneously meet the clock frequency requirements of different interfaces, and does not need to provide a plurality of clock output circuits 300, thereby effectively reducing the hardware cost.
Based on the first embodiment, a second embodiment of the frequency-adjustable multi-way differential clock output circuit of the present invention is provided.
Referring to fig. 5, fig. 5 is a functional block diagram of a second embodiment of the multi-way differential clock output circuit of the present invention.
As shown in fig. 5, the multi-way differential clock output circuit further includes: a power supply circuit 400; the power supply circuit 400 is connected to the frequency acquisition circuit 200 and the clock output circuit 300 respectively; the power supply circuit 400 is configured to provide a power supply voltage for the frequency acquisition circuit 200 and the clock output circuit 300.
It should be noted that, in general, the obtained power voltage is unstable in floating and easily exceeds the voltage input range of the chip, which is likely to cause chip failure or even burn out the chip, so that the power voltage needs to be processed and then transmitted to the frequency obtaining circuit 200 and the clock output circuit 300 in this embodiment.
Further, as an implementable manner, the power supply circuit 400 includes: an overvoltage protection circuit and a power switching circuit;
the overvoltage protection circuit is respectively connected with a power supply and the power supply conversion circuit, and the power supply conversion circuit is respectively connected with the frequency acquisition circuit 200 and the clock output circuit 300;
the overvoltage protection circuit is used for receiving a first power supply voltage AC _ IN and disconnecting the overvoltage protection circuit from the power supply conversion circuit when the first power supply voltage AC _ IN exceeds a preset safety value;
the overvoltage protection circuit is further used for outputting the second power supply voltage VDC to the power supply conversion circuit when the power supply voltage does not exceed the preset safety value;
it should be noted that, before converting the floating voltage value of the power voltage into a stable voltage value for the chip or device to work, the power voltage needs to be monitored first to prevent the voltage value of the power voltage from exceeding a preset safety value, which is an input safety voltage value of the chip or device in this embodiment, so as to avoid burning the chip or device.
For ease of understanding, the overvoltage protection circuit is described with reference to fig. 6, but this solution is not limited thereto. Fig. 6 is a schematic circuit structure diagram of an overvoltage protection circuit in a second embodiment of the multi-path differential clock output circuit of the present invention, where the overvoltage protection circuit includes: twelfth to eighteenth resistors R12 to 18, first to second NMOS transistors Q1 to Q2, a first PMOS transistor Q3, and a first capacitor C1;
a gate G of the first NMOS transistor Q1 is connected to a first end of the twelfth resistor R12 and a first end of the thirteenth resistor R13, respectively, a second end of the twelfth resistor R12 is connected to the power circuit 400, and a second end of the thirteenth resistor R13 and the source S of the first NMOS transistor Q1 are both grounded;
a drain D of the first NMOS transistor Q1 is respectively connected to a first end of the fourteenth resistor R14, a first end of the fifteenth resistor R15, and a gate G of the second NMOS transistor Q2, a second end of the fourteenth resistor R14 is connected to the power circuit 400, and a second end of the fifteenth resistor R15 and a source S of the second NMOS transistor Q2 are both grounded; a drain D of the second NMOS transistor Q2 is connected to a first end of the sixteenth resistor R16, a second end of the sixteenth resistor R16 is connected to a first end of the seventeenth resistor R17 and a first end of the eighteenth resistor R18, respectively, and a second end of the seventeenth resistor R17 is connected to the power circuit 400;
the second end of the eighteenth resistor R18 is connected to the first end of the first capacitor C1 and the gate G of the first PMOS transistor Q3, the second end of the first capacitor C1 and the source S of the first PMOS transistor Q3 are both connected to the power circuit 400, and the drain D of the first PMOS transistor Q3 is connected to the power conversion circuit.
IN a specific implementation, the resistance of the twelfth resistor R12 is much greater than the resistance of the thirteenth resistor R13, and the resistance of the fifteenth resistor R15 is much greater than the resistance of the fourteenth resistor R14, so when the first power voltage AC _ IN is a normal input voltage, the voltage divided by the twelfth resistor R12 and the thirteenth resistor R13 is not enough to turn on the first NMOS transistor Q1, but the second NMOS transistor Q2 can be turned on, so that the branch circuit: the first power voltage AC _ IN, the seventeenth resistor R17, the sixteenth resistor R16 and the second NMOS transistor Q2 can be conducted, so that the first PMOS transistor Q3 can be conducted, and the overvoltage protection circuit can output the second power voltage VDC to the power conversion circuit;
when the first power voltage AC _ IN is not the normal input voltage and the voltage value thereof exceeds the preset safety value, the voltage divided by the twelfth resistor R12 and the thirteenth resistor R13 is sufficient to turn on the first NMOS transistor Q1, so the gate voltage of the second NMOS transistor Q2 is pulled down to zero level, the second NMOS transistor Q2 cannot be turned on, and thus the branch circuit: the first power voltage AC _ IN-the seventeenth resistor R17-the sixteenth resistor R16-the second NMOS transistor Q2 cannot be turned on, and at this time, the source voltage of the first PMOS transistor Q3 is much greater than the gate voltage, and the first PMOS transistor Q3 cannot be turned on, so that the overvoltage protection circuit is disconnected from the power conversion circuit.
The power conversion circuit is configured to convert the second power voltage VDC into a first voltage VDD _ AUCLK and a second voltage VDD18_ IO, and to supply the first voltage VDD _ AUCLK to the frequency acquisition circuit and the clock output circuit 300, and to supply the second voltage VDD18_ IO to the clock output circuit 300.
It should be noted that the two different voltages are output by the power conversion circuit, so as to control the order of the input voltage and the output voltage, where the first voltage VDD _ AUCLK is used to provide voltage for the chip and the device, and the second voltage VDD18_ IO is used to provide voltage for the output clock signal, in this embodiment, the output of the first voltage VDD _ AUCLK needs to be faster than the output of the second voltage VDD18_ IO, so as to prevent the clock output circuit 300 from not converting the initial clock signal according to the data of the frequency acquisition circuit 200 and directly outputting the initial clock signal after the circuit is powered on. The prevention may be that a processing circuit is added to the input control terminal of the switching circuit outputting the second voltage VDD18_ IO, the processing circuit takes the first voltage VDD _ AUCLK and the second power voltage VDC as input, when the first power is not input, the input signal of the input control terminal is high level, and the input control terminal is active low level, so that the switching circuit of the second voltage VDD18_ IO does not output a signal; when the first voltage VDD _ AUCLK is input, the input signal of the input control terminal is lowered to a low level, and thus the input control terminal of the conversion circuit of the second voltage VDD18_ IO is enabled, thereby outputting the second voltage VDD18_ IO. Of course, the input control terminal is also active at high level, and the specific effective manner is not limited in this embodiment, and as long as the above process can be implemented, the specific structure of the processing circuit is also not limited in this embodiment.
IN the embodiment, the overvoltage protection circuit receives the input first power supply voltage AC _ IN, and when the first power supply voltage AC _ IN exceeds a preset safety value, the connection with the power supply conversion circuit is disconnected; when the power supply voltage does not exceed a preset safety value, outputting a second power supply voltage VDC to a power supply conversion circuit; then, the power conversion circuit converts the second power voltage VDC into the first voltage VDD _ AUCLK and the second voltage VDD18_ IO, supplies the first voltage VDD _ AUCLK to the frequency acquisition circuit and the clock output circuit 300, and supplies the second voltage VDD18_ IO to the clock output circuit 300. The output time of the second voltage VDD18_ IO is later than the output time of the first voltage VDD _ AUCLK, so that the embodiment avoids the failure that the initial clock signal is output without being processed by the main clock chip U1, and simultaneously avoids the failure that the chip or the device is burned due to the overhigh voltage value of the input power supply, thereby greatly improving the safety guarantee of the circuit.
In addition, in order to achieve the above object, an embodiment of the present invention further provides a frequency-adjustable multi-way differential clock output apparatus, which includes the frequency-adjustable multi-way differential clock output circuit in the above embodiment.
Other embodiments or specific implementations of the multi-path differential clock output apparatus of the present invention may refer to the above-mentioned embodiment of the frequency-adjustable multi-path differential clock output circuit, and are not described herein again.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (8)
1. A frequency adjustable multiple differential clock output circuit, comprising: the device comprises an oscillating circuit, a frequency acquisition circuit and a clock output circuit;
the clock output circuit is respectively connected with the oscillating circuit and the frequency acquisition circuit;
the oscillating circuit is used for providing an initial clock signal for the clock output circuit;
the frequency acquisition circuit is used for acquiring a target frequency of a differential clock signal to be output and sending the target frequency to the clock output circuit;
and the clock output circuit is used for generating a target differential clock signal according to the initial clock signal and the target frequency and outputting the target differential clock signal through a corresponding target output port.
2. The multi-way differential clock output circuit of claim 1, wherein the clock output circuit comprises: the circuit comprises a main clock chip, a first resistor, a second resistor, a third resistor, a fourth resistor and an output port;
the main clock chip is respectively connected with the oscillating circuit and the frequency acquisition circuit;
a first end of the first resistor is connected with a first clock output pin of the master clock chip, and a second end of the first resistor is respectively connected with a first end of the third resistor and a first interface of the output port;
a first end of the second resistor is connected with a second clock output pin of the master clock chip, and a second end of the second resistor is respectively connected with a first end of the fourth resistor and a second interface of the output port;
the second end of the third resistor, the second end of the fourth resistor, the third interface of the output port, the fourth interface of the output port, and the ground pin of the master clock chip are all grounded.
3. The multi-way differential clock output circuit of claim 1, wherein the oscillating circuit comprises: the circuit comprises a crystal oscillator, a fifth resistor, a sixth resistor and a seventh resistor;
the first end of the crystal oscillator is respectively connected with the second end of the fifth resistor and the first end of the seventh resistor, and the first end of the fifth resistor is connected with a first crystal oscillator pin of a master clock chip;
the second end of the crystal oscillator is connected with a first crystal oscillator grounding pin of the master clock chip;
the third end of the crystal oscillator is respectively connected with the second end of the seventh resistor and the second end of the sixth resistor, and the first end of the sixth resistor is connected with a second crystal oscillator pin of the master clock chip;
and the fourth end of the crystal oscillator is connected with a second crystal oscillator grounding pin of the master clock chip.
4. The multi-way differential clock output circuit of claim 1, wherein the frequency acquisition circuit comprises: an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor and a data acquisition port;
a first end of the eighth resistor is connected with a first end of the data acquisition port, and a second end of the eighth resistor is respectively connected with a first end of the tenth resistor and a bus clock pin of the master clock chip;
and the first end of the ninth resistor is connected with the second end of the data acquisition port, and the second end of the ninth resistor is respectively connected with the first end of the eleventh resistor and a bus data pin of a master clock chip.
5. The multi-way differential clock output circuit of any of claims 1-4, further comprising: a power supply circuit;
the power supply circuit is respectively connected with the frequency acquisition circuit and the clock output circuit;
and the power supply circuit is used for providing power supply voltage for the frequency acquisition circuit and the clock output circuit.
6. The multi-way differential clock output circuit of claim 5, wherein the power supply circuit comprises: an overvoltage protection circuit and a power switching circuit;
the overvoltage protection circuit is respectively connected with a power supply and the power supply conversion circuit, and the power supply conversion circuit is respectively connected with the frequency acquisition circuit and the clock output circuit;
the overvoltage protection circuit is used for receiving power supply voltage and disconnecting the overvoltage protection circuit from the power supply conversion circuit when the power supply voltage exceeds a preset safety value;
the overvoltage protection circuit is further used for outputting the power supply voltage to the power supply conversion circuit when the power supply voltage does not exceed the preset safety value;
the power supply conversion circuit is used for converting the power supply voltage into a first voltage and a second voltage, transmitting the first voltage to the frequency acquisition circuit and the clock output circuit, and transmitting the second voltage to the clock output circuit.
7. The multi-way differential clock output circuit of claim 6, wherein the overvoltage protection circuit comprises: twelfth to eighteenth resistors, first to second NMOS transistors, a first PMOS transistor, and a first capacitor;
the grid electrode of the first NMOS tube is respectively connected with the first end of the twelfth resistor and the first end of the thirteenth resistor, the second end of the twelfth resistor is connected with the power supply circuit, and the second end of the thirteenth resistor and the source electrode of the first NMOS tube are both grounded;
the drain electrode of the first NMOS tube is respectively connected with the first end of the fourteenth resistor, the first end of the fifteenth resistor and the grid electrode of the second NMOS tube, the second end of the fourteenth resistor is connected with the power circuit, and the second end of the fifteenth resistor and the source electrode of the second NMOS tube are both grounded;
a drain electrode of the second NMOS transistor is connected to a first end of the sixteenth resistor, a second end of the sixteenth resistor is connected to a first end of the seventeenth resistor and a first end of the eighteenth resistor, respectively, and a second end of the seventeenth resistor is connected to the power supply circuit;
the second end of the eighteenth resistor is connected with the first end of the first capacitor and the grid electrode of the first PMOS tube respectively, the second end of the first capacitor and the source electrode of the first PMOS tube are both connected with the power supply circuit, and the drain electrode of the first PMOS tube is connected with the power supply conversion circuit.
8. A frequency-adjustable multi-way differential clock output device, characterized in that the frequency-adjustable multi-way differential clock output device comprises the frequency-adjustable multi-way differential clock output circuit according to any one of claims 1 to 7.
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| CN202211161458.6A CN115242192B (en) | 2022-09-23 | 2022-09-23 | Frequency-adjustable multi-path differential clock output circuit and device |
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| CN115242192B CN115242192B (en) | 2022-12-23 |
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| US20200287552A1 (en) * | 2019-03-05 | 2020-09-10 | Seiko Epson Corporation | Oscillator, electronic apparatus and vehicle |
| CN216216900U (en) * | 2021-11-09 | 2022-04-05 | 天津聚芯光禾科技有限公司 | 25G error code instrument |
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| US20070290763A1 (en) * | 2006-06-14 | 2007-12-20 | Aaron Partridge | Microelectromechanical oscillator having temperature measurement system, and method of operating same |
| CN102323530A (en) * | 2011-05-26 | 2012-01-18 | 北京星网锐捷网络技术有限公司 | Device and method for testing clock |
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