CN210072599U

CN210072599U - Multichannel USB jointing equipment

Info

Publication number: CN210072599U
Application number: CN201920688758.7U
Authority: CN
Inventors: 苏世鹏; 周军; 姜建礼; 黄喜
Original assignee: Picture Shows Information Technology (shenzhen) Co Ltd
Current assignee: Picture Shows Information Technology (shenzhen) Co Ltd
Priority date: 2019-05-15
Filing date: 2019-05-15
Publication date: 2020-02-14
Anticipated expiration: 2029-05-15

Abstract

The utility model discloses a multi-path USB connecting device, which is an external platform, and comprises a shell, wherein a circuit board is arranged in the shell, and the multi-path USB connecting device is characterized in that a control module, a peripheral auxiliary module and a plurality of USB3.0 ports are integrated on the circuit board; the control module is connected with the peripheral auxiliary module and the plurality of USB3.0 ports; the peripheral auxiliary module converts the input voltage into power voltage and peripheral voltage to supply power to the control module, the peripheral auxiliary module performs USB communication protocol configuration on the control module according to the currently connected USB peripheral, the control module outputs USB3.0 data signals after performing packet interaction on data transmitted by the platform, and the data signals are output through corresponding USB3.0 ports after being distributed in real time. Because the transmission rate and the response speed of the USB3.0 are fast, the problem that the transmission of the existing USB2.0 external equipment is unstable can be solved.

Description

Multichannel USB jointing equipment

Technical Field

The utility model relates to a USB technical field, in particular to multichannel USB jointing equipment.

Background

In practical application, especially in the fields of inspection robots, unmanned merchant super face-brushing payment, industrial automation control and the like, the equipment needs to be simultaneously accessed to external equipment such as a multi-channel high-definition USB3.0 camera, a U disk, an expansion card and the like. However, the number of USB ports that can simultaneously connect external devices to the device is small, usually only 1-2, and many functions cannot be completed by running the device at the same time, so that there is a strong need for the device to simultaneously access multiple paths of external devices of high definition USB to meet the practical application requirements of the client.

Meanwhile, the transmission speed of the traditional external equipment is low, for example, the theoretical highest transmission data of the USB2.0 is only 480M per second, when high-definition image data with large data volume is transmitted, the USB2.0 cannot meet the requirement of high-speed application at all, and particularly, the transmission speed is obviously insufficient in the aspect of image capture of population intelligent data. And the phenomenon that the USB2.0 loses the data packet is particularly serious, so that the accuracy and the real-time performance of the data are greatly influenced.

In addition, the external device of the USB2.0 is affected by slow transmission rate, the transmission is unstable, especially when transmitting high-definition big data, the system is easy to be jammed, the data packet is lost, and the phenomenon that the system is directly halted can be caused seriously,

therefore, there is a need for improvements in the prior art.

SUMMERY OF THE UTILITY MODEL

To the technical problem, the embodiment of the utility model provides a multichannel USB jointing equipment to solve the current unstable problem of USB 2.0's external equipment transmission.

The embodiment of the utility model provides a multichannel USB jointing equipment, external platform, be provided with CPU and Yingweida module on the platform, multichannel USB jointing equipment includes a casing, set up a circuit board in the casing, its characterized in that, integrated control module, peripheral auxiliary module and a plurality of USB3.0 ports on the circuit board; the control module is connected with the peripheral auxiliary module and the plurality of USB3.0 ports;

the peripheral auxiliary module converts the input voltage into power voltage and peripheral voltage to supply power to the control module, the peripheral auxiliary module performs USB communication protocol configuration on the control module according to the currently connected USB peripheral, the control module outputs USB3.0 data signals after performing packet interaction on data transmitted by the platform, and the data signals are output through corresponding USB3.0 ports after being distributed in real time.

Optionally, in the multi-USB connection device, the peripheral auxiliary module includes a power control and protection circuit, a power management circuit, a management protocol control circuit, a data register circuit, and a phase-locked loop control circuit; the power supply control and protection circuit is connected with the power supply management circuit and the management protocol control circuit, and the management protocol control circuit is connected with the data register circuit and the phase-locked loop control circuit;

the power supply control and protection circuit outputs and supplies power to the input voltage and converts the input voltage into power supply voltage to supply power; the power supply management circuit converts power supply voltage into a plurality of preset peripheral voltages according to an input I2C signal, and outputs and supplies power after voltage stabilization; the management protocol control circuit establishes handshake connection with the system according to the USB standard protocol corresponding to the current connected USB peripheral configuration; the data register circuit is used for storing protocol data during USB communication, and the phase-locked loop control circuit is used for generating a clock signal required by the management protocol control circuit.

Optionally, in the multi-channel USB connection device, the control module includes a USB3.0 expansion processing chip and a filter port circuit; the USB3.0 expansion processing chip is connected with a filter port circuit, and the filter port circuit is connected with a power management circuit;

the USB3.0 expansion processing chip outputs USB3.0 data signals after carrying out bus node control and grouping interaction control on data transmitted by the platform, and the filtering port circuit carries out EMI filtering on the USB3.0 data signals and then outputs the data signals from the corresponding USB3.0 port.

Optionally, in the multi-channel USB connection device, the power control and protection circuit includes a first interface, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, a first triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a first capacitor, a second capacitor, and a third capacitor;

the DC pin of the first interface is connected with the drain electrode of the first MOS tube, the input voltage end, one end of the first resistor and one end of the third resistor; the other end of the first resistor is connected with one end of the second resistor and the No. 2 pin of the third MOS tube, the No. 6 pin of the third MOS tube is connected with the CPU, and the No. 1 pin of the third MOS tube and the other end of the second resistor are both grounded; the other end of the third resistor is connected with one end of the fourth resistor, the base of the first triode and the 3 rd pin of the third MOS tube; the other end of the fourth resistor, the emitting electrode of the first triode and the 4 th pin of the third MOS tube are all grounded; the 5 th pin of the third MOS tube is connected with the CPU; a collector of the first triode is connected with a grid of the second MOS tube, one end of the first capacitor, one end of the fifth resistor and the grid of the first MOS tube; the source electrode of the first MOS tube is connected with the other end of the fifth resistor, the other end of the first capacitor and the source electrode of the second MOS tube; the drain electrode of the second MOS tube is connected with the source electrode of the fourth MOS tube, one end of the third capacitor, one end of the ninth resistor and the modulation voltage end; the grid electrode of the fourth MOS tube is connected with the other end of the third capacitor, the other end of the ninth resistor and one end of the tenth resistor; the drain electrode of the fourth MOS tube is connected with one end of the second capacitor, the drain electrode of the sixth MOS tube and the power supply voltage end; the other end of the second capacitor is grounded through an eighth resistor, the other end of the second capacitor is also connected with one end of a sixth resistor and the grid electrode of a fifth MOS (metal oxide semiconductor) tube through a seventh resistor, the drain electrode of the fifth MOS tube is connected with the CPU, the grid electrode of the sixth MOS tube is connected with the drain electrode of the seventh MOS tube and the other end of the tenth resistor, and the grid electrode of the seventh MOS tube is connected with the CPU; and the source electrode of the fifth MOS tube, the source electrode of the sixth MOS tube, the source electrode of the seventh MOS tube and the other end of the sixth resistor are all grounded.

Optionally, in the multi-channel USB connection device, the power management circuit includes a power management chip, a first inductor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, and a tenth capacitor;

the 9 th pin and the 10 th pin of the power management chip are both connected with the CPU, the 6 th pin and the 4 th pin of the power management chip are both connected with a power voltage end, the 5 th pin of the power management chip is connected with the 1 st drain electrode of the eighth MOS tube, and the 32 th pin of the power management chip is connected with one end of a seventh capacitor through a fourteenth resistor; the 1 st pin of the power management chip is connected with the 1 st grid electrode of the eighth MOS tube; a 31 st pin of the power management chip is connected with the other end of the seventh capacitor, a1 st source electrode, a 2 nd drain electrode and one end of the first inductor of the eighth MOS tube; a 2 nd source electrode of the eighth MOS tube is grounded, a 2 nd pin of the power management chip is connected with a 2 nd grid electrode of the eighth MOS tube, and a 21 st pin of the power management chip is connected with one end of a twelfth resistor, one end of a fourth capacitor, one end of an eleventh resistor and one end of a sixth capacitor; a 20 th pin of the power management chip is connected with one end of a thirteenth resistor, the other end of a fourth capacitor, the other end of an eleventh resistor and one end of a fifth capacitor; a 25 th pin of the power management chip is connected with one end of the eighth capacitor through a fifteenth resistor, and a 24 th pin of the power management chip is connected with a1 st grid electrode of the ninth MOS tube; a 26 th pin of the power management chip is connected with the other end of the eighth capacitor, a1 st source electrode, a 2 nd drain electrode of the ninth MOS tube and the other end of the first inductor; a 23 rd pin of the power management chip is connected with a 2 nd grid electrode of the ninth MOS tube, and a 2 nd source electrode of the ninth MOS tube is grounded; a1 st drain electrode of the ninth MOS transistor is connected with one end of a tenth capacitor, the other end of a twelfth resistor, the other end of a thirteenth resistor and a 5V power supply end; one end of the tenth capacitor is connected with one end of the sixteenth resistor and the source electrode of the tenth MOS tube; the other end of the sixteenth resistor is connected with a grid electrode of the tenth MOS tube, a grid electrode of the eleventh MOS tube and a drain electrode of the twelfth MOS tube; the drain electrode of the tenth MOS tube is connected with the drain electrode of the eleventh MOS tube, one end of the ninth capacitor and the first peripheral voltage end; the grid electrode of the twelfth MOS tube is connected with the CPU; and the source electrode of the eleventh MOS tube, the source electrode of the twelfth MOS tube and the other end of the ninth capacitor are all grounded.

Optionally, in the multi-channel USB connection device, the management protocol control circuit includes a control chip, a first clock chip, an eleventh capacitor, and a twelfth capacitor;

the 15 th pin to the 17 th pin of the control chip are connected with a USB3.0 expansion processing chip in the control module, the 38 th pin of the control chip is connected with one end of a twelfth capacitor and an HOT2 pin of the first clock chip, the 39 th pin of the control chip is connected with one end of an eleventh capacitor C11 and the HOT pin of the first clock chip, the other end of the twelfth capacitor is grounded, and a GND pin of the first clock chip is connected with the other end of the eleventh capacitor and the ground.

Optionally, in the multi-channel USB connection device, the peripheral circuit of the USB3.0 expansion processing chip includes a seventeenth resistor, a thirteenth capacitor, a fourteenth capacitor, a fifteenth capacitor, and a second clock chip;

the PERST # pin, the PCICECKP pin, the PCICECCKM pin, the PCICEXXP pin and the PCICEXXM pin of the USB3.0 extended processing chip are all connected with the Invitta module; a PCIEREXT pin of the USB3.0 expansion processing chip is connected with one end of a seventeenth resistor, a PCICCAP pin of the USB3.0 expansion processing chip is connected with one end of a thirteenth capacitor, and the other end of the seventeenth resistor is connected with the other end of the thirteenth capacitor and the ground; u2DP 0-U2 DP3 pin, U2DM 0-U2 DM3 pin, SSTP 0-SSTP 3 pin, SSTP 0-SSTP XM3 pin, SSRXP 0-SSRXP 3 pin and SSRXM 0-SSRXM 3 pin of the USB3.0 expansion processing chip are all connected with a filter port circuit; an XSCO pin of the USB3.0 extended processing chip is connected with an HOT pin of the second clock chip and one end of a fifteenth capacitor, and an XSCI pin of the USB3.0 extended processing chip is connected with an HOT2 pin of the second clock chip and one end of a fourteenth capacitor; the other end of the fifteenth capacitor is connected with the other end of the fourteenth capacitor, a GND pin of the second clock chip and the ground; the ROMSDA pin, the ROMSCL pin and the ROMPRES pin of the USB3.0 extended processing chip are correspondingly connected with the 16 th pin, the 17 th pin and the 15 th pin of the control chip.

Optionally, in the multi-USB connection device, the filter port circuit includes a first filter, a second filter, a third filter, a fourth filter, a fifth filter, a sixth filter, a first USB input/output port, and a second USB input/output port;

the 1 st pin, the 2 nd pin, the 4 th pin and the 5 th pin of the first filter are correspondingly connected with an SSRXP0 pin, an SSRXM0 pin, a U2DP0 pin and a U2DM0 pin of a USB3.0 expansion processing chip; the 6 th pin, the 7 th pin, the 9 th pin and the 10 th pin of the first filter are correspondingly connected with a DN pin, a DP pin, an SSRXN pin and an SSRXP pin of the first USB input/output port; the 1 st pin, the 2 nd pin, the 4 th pin and the 5 th pin of the second filter are correspondingly connected with an SSTP 0 pin, an SSTX 0 pin, an SSTX 1 pin and an SSTX 1 pin of the USB3.0 expansion processing chip; the 6 th pin, the 7 th pin, the 9 th pin and the 10 th pin of the second filter are correspondingly connected with the SSTX 2 pin, the SSTX 2 pin, the SSTX pin and the SSTX pin of the first USB input/output port; the 1 st pin, the 2 nd pin, the 4 th pin and the 5 th pin of the third filter are correspondingly connected with an SSRXM1 pin, an SSRXP1 pin, a U2DP1 pin and a U2DM1 pin of the USB3.0 expansion processing chip; the 6 th pin, the 7 th pin, the 9 th pin and the 10 th pin of the third filter are correspondingly connected with a DN2 pin, a DP2 pin, an SSRXP2 pin and an SSRXN2 pin of the first USB input/output port; the 1 st pin, the 2 nd pin, the 4 th pin and the 5 th pin of the fourth filter are correspondingly connected with an SSRXP2 pin, an SSRXM2 pin, a U2DP2 pin and a U2DM2 pin of the USB3.0 expansion processing chip; the 6 th pin, the 7 th pin, the 9 th pin and the 10 th pin of the fourth filter are correspondingly connected with a DN pin, a DP pin, an SSRXN pin and an SSRXP pin of the second USB input/output port; the 1 st pin, the 2 nd pin, the 4 th pin and the 5 th pin of the fifth filter are correspondingly connected with a U2DP3 pin, a U2DM3 pin, an SSTP 2 pin and an SSTX 2 pin of the USB3.0 expansion processing chip; the 6 th pin, the 7 th pin, the 9 th pin and the 10 th pin of the fifth filter are correspondingly connected with the SSTX pin, the DN2 pin and the DP2 pin of the second USB input/output port; the 1 st pin, the 2 nd pin, the 4 th pin and the 5 th pin of the sixth filter are correspondingly connected with the SSTP 3 pin, the SSTP 3 pin, the SSTP 3 pin and the SSTP 3 pin of the USB3.0 expansion processing chip; the 6 th pin, the 7 th pin, the 9 th pin and the 10 th pin of the sixth filter are correspondingly connected with the SSRXN2 pin, the SSRXP2P pin, the SSTXN2 pin and the SSTXP2 pin of the second USB input/output port.

Optionally, in the multi-channel USB connection device, the model of the power management chip is NCP81239, the model of the control chip is CYPD4226-40LQXIT, and the model of the USB3.0 expansion processing chip is FL 1100.

Compared with the prior art, the utility model provides a multichannel USB connecting device, multichannel USB connecting device external platform and CPU, including a casing, set up a circuit board in the casing, its characterized in that, integrated control module, peripheral auxiliary module and a plurality of USB3.0 ports on the circuit board; the control module is connected with the peripheral auxiliary module and the plurality of USB3.0 ports; the peripheral auxiliary module converts the input voltage into power voltage and peripheral voltage to supply power to the control module, the peripheral auxiliary module performs USB communication protocol configuration on the control module according to the currently connected USB peripheral, the control module outputs USB3.0 data signals after performing packet interaction on data transmitted by the platform, and the data signals are output through corresponding USB3.0 ports after being distributed in real time. Because the transmission rate and the response speed of the USB3.0 are fast, the problem that the transmission of the existing USB2.0 external equipment is unstable can be solved.

Drawings

Fig. 1 is a block diagram of a multi-path USB connection device according to an embodiment of the present invention.

Fig. 2 is a circuit diagram of a power control and protection circuit in the multi-path USB connection device according to an embodiment of the present invention.

Fig. 3 is a circuit diagram of a power management circuit in a multi-channel USB connection device according to an embodiment of the present invention.

Fig. 4 is a circuit diagram of a management protocol control circuit in the multi-path USB connection device according to an embodiment of the present invention.

Fig. 5 is a circuit diagram of a USB3.0 expansion processing chip in the multi-path USB connection device according to an embodiment of the present invention.

Fig. 6 is a circuit diagram of a filter port circuit in the multi-path USB connection device according to an embodiment of the present invention.

Fig. 7 is a flowchart of a data control method for a multi-channel USB connection device according to an embodiment of the present invention.

Detailed Description

The utility model provides a multichannel USB jointing equipment and data control method thereof adopts the USB3.0 technique, and its transmission rate and response speed are all very fast, can solve the current unstable problem of USB2.0 transmission. In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the following description of the present invention will refer to the accompanying drawings and illustrate embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.

Referring to fig. 1, the present invention provides a multi-channel USB connection device, which includes a housing, a circuit board disposed in the housing, and a control module 10, a peripheral auxiliary module 20, and a plurality of USB3.0 ports integrated on the circuit board; the control module 10 is connected with a peripheral auxiliary module 20 and a plurality of USB3.0 ports; the peripheral auxiliary module 20 converts the input voltage into a power voltage and a peripheral voltage to supply power to the control module 10, the peripheral auxiliary module 20 configures a corresponding USB standard protocol for the control module 10 according to the currently connected USB peripheral, and the control module 10 outputs a USB3.0 data signal after performing packet interaction on data transmitted by the platform, and outputs the data signal through a corresponding USB3.0 port after real-time distribution.

In this embodiment, the control module 10 includes a USB3.0 expansion processing chip 11 and a filtering port circuit 12; the USB3.0 expansion processing chip 11 is connected with a filter port circuit, and the filter port circuit is connected with a power management circuit. The USB3.0 expansion processing chip 11 outputs USB3.0 data signals after performing bus transceiving, bus node control, and packet interaction control on data transmitted by the platform, and the filtering port circuit 12 outputs the USB3.0 data signals from the corresponding USB3.0 port after performing EMI filtering on the USB3.0 data signals. The NVIDIA (NVIDIA Jetson) module outputs a pcie X2 bus interface to the USB3.0 expansion processing chip, data transmitted by the pcie X2 bus is transmitted and received by the USB3.0 expansion processing chip 11 via the bus, controlled by the bus node, distributed in real time in the data bus (i.e., controlled by the packet interaction X), and finally output in parallel to 4 groups of ports (ports 0 to 3, Root ports 0 to 3), the channels of each group of ports respectively transmit, exchange, and control the USB data, and then reach the terminal Port devices (Connector ports 0 to 3) of the USB through the USB3.0 ports (USB3.0 ports 0 to 3), and the bandwidths of each group of 4 groups of USB3.0 channels are the same and are all parallel outputs, and the transmission rates are all 5G/S.

The peripheral auxiliary module 20 includes a power control and protection circuit 210, a power management circuit 220, a management protocol control circuit 230 (i.e. USB BIOS management protocol control), a data register circuit 240 and a phase-locked loop control circuit 250; the power control and protection circuit 210 is connected to the power management circuit 220 and the management protocol control circuit 230, and the management protocol control circuit 230 is connected to the data register circuit 240 and the pll control circuit 250.

The power control and protection circuit 210 outputs the input voltage VCC _ DCIN for power supply and converts the input voltage into the power voltage VCC _ SRC for power supply. The power management circuit 220 converts the power voltage into a plurality of preset peripheral voltages according to the input I2C signal, and outputs the regulated voltages for power supply. The management protocol control circuit 230 establishes a handshake connection with the system according to the USB standard protocol corresponding to the currently connected USB peripheral configuration. The data register circuit 240 is used for storing protocol data during USB communication, and the pll control circuit 250 is used for generating a clock signal required by the management protocol control circuit 230.

Referring to fig. 2, the power control and protection circuit 210 includes a first interface J1, a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3 (including Q3A and Q3B), a fourth MOS transistor Q4, a fifth MOS transistor Q5, a sixth MOS transistor Q6, a seventh MOS transistor Q7, a first transistor N1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

The DC pin of the first interface J1 is connected with the drain of the first MOS transistor Q1, an input voltage terminal (providing an input voltage VCC _ DCIN), one end of a first resistor R1 and one end of a third resistor R3; the other end of the first resistor R1 is connected to one end of the second resistor R2 and the 2 nd pin (i.e., the gate of the Q3A) of the third MOS transistor Q3, the 6 th pin (i.e., the drain of the Q3A) of the third MOS transistor Q3 is connected to an external CPU (the DC _ IN _ EC signal is at a high level and a low level for feeding back the operating state of the power supply to the CPU and informing the CPU of the operating state of the power supply), and the 1 st pin (i.e., the source of the Q3A) of the third MOS transistor Q3 and the other end of the second resistor R2 are both grounded; the other end of the third resistor R3 is connected to one end of the fourth resistor R4, the base of the first triode N1 and the 3 rd pin (drain of Q3B) of the third MOS transistor Q3; the other end of the fourth resistor R4, the emitter of the first triode N1 and the 4 th pin (the source of Q3B) of the third MOS transistor Q3 are all grounded; the 5 th pin (the gate of the Q3B) of the third MOS tube Q3 is connected with an external CPU; a collector of the first triode N1 is connected with a gate of the second MOS transistor Q2, one end of the first capacitor C1, one end of the fifth resistor R5 and a gate of the first MOS transistor Q1; the source electrode of the first MOS transistor Q1 is connected with the other end of the fifth resistor R5, the other end of the first capacitor C1 and the source electrode of the second MOS transistor Q2; the drain of the second MOS transistor Q2 is connected to the source of the fourth MOS transistor Q4, one end of the third capacitor C3, one end of the ninth resistor R9 and the modulation voltage terminal VDD _ MOD; the gate of the fourth MOS transistor Q4 is connected to the other end of the third capacitor C3, the other end of the ninth resistor R9 and one end of the tenth resistor R10; the drain electrode of the fourth MOS transistor Q4 is connected with one end of the second capacitor C2, the drain electrode of the sixth MOS transistor Q6 and a power supply voltage end; the other end of the second capacitor C2 is grounded through an eighth resistor R8, the other end of the second capacitor C2 is further connected with one end of a sixth resistor R6 and the gate of a fifth MOS transistor Q5 through a seventh resistor R7, the drain of the fifth MOS transistor Q5 is connected with an external CPU, the gate of the sixth MOS transistor Q6 is connected with the drain of the seventh MOS transistor Q7 and the other end of a tenth resistor R10, and the gate of the seventh MOS transistor Q7 is connected with the external CPU; the source electrode of the fifth MOS transistor Q5, the source electrode of the sixth MOS transistor Q6, the source electrode of the seventh MOS transistor Q7, and the other end of the sixth resistor R6 are all grounded.

The power control and protection circuit 210 is used to prevent short circuit caused by reverse voltage connection of the power supply and prevent damage to the IC and components due to excessive input power supply voltage. The input voltage VCC _ DCIN is input from the first interface J1, and the normal input voltage range is +13V to + 22V. When the input power voltage is normal, the MOS transistors Q1 and Q2 work normally, and a DC _ IN _ GATE _ CCG4 signal ON the 5 th pin (GATE of Q3B) of Q3 (output by the CPU, the CPU controls the ON and off of the power supply of the USB part by controlling the high and low levels of the DC _ IN _ GATE _ CCG4 signal) and a VIN _ PWR _ ON signal ON the 1 st pin of Q7 (output by the CPU, the CPU controls the ON and off of the power supply of the USB part by controlling the high and low levels of the VIN _ PWR _ ON signal) output high levels at the same time. The DC _ IN _ GATE _ CCG4 signal is used to control the Q3 to turn on and off, and when the DC _ IN _ GATE _ CCG4 signal is high, the MOS transistor Q3B turns on to control the first transistor N1 to turn on, so that Q1 and Q2 turn on, and the input voltage VCC _ DCIN is delivered to

pins

1, 2 and 3 of the fourth MOS transistor Q4. After the Q1 and the Q2 are normally turned on, the modulation voltage terminal VDD _ MOD outputs a modulation voltage. When the VIN _ PWR _ ON signal of the 1 st pin of Q7 is at a high level, the 5 th pin of Q4 outputs the power supply voltage VCC _ SRC to the power management circuit 220 through the detection of the sixth MOS transistor Q6 and the voltage dividing resistors (R1, R2). The VIN _ PWM _ BAD _ N signal is output by the CPU, and the CPU controls the power on and off of the USB part by controlling the high and low levels of the VIN _ PWM _ BAD _ N signal. The resistors R9 and R10 play a very key role in the circuit, and play a role in voltage division detection and voltage feedback for the starting of the power supply. The gates of the MOS transistors Q3B are further connected to the PD power supply terminal VDD _3V3_ PD through a resistor, respectively, and the gate of the MOS transistor Q3B is further grounded through a resistor.

Referring to fig. 3, the power management circuit 220 includes a power management chip U1, a first inductor L1, an eighth MOS transistor Q8, a ninth MOS transistor Q9, a tenth MOS transistor Q10, an eleventh MOS transistor Q11, a twelfth MOS transistor Q12, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, and a tenth capacitor C10.

The 9 th pin and the 10 th pin of the power management chip U1 are both connected with the CPU, the 6 th pin and the 4 th pin of the power management chip U1 are both connected with a power supply voltage end, the 5 th pin of the power management chip U1 is connected with the 1 st drain D1 of the eighth MOS tube Q8, and the 32 th pin of the power management chip U1 is connected with one end of a seventh capacitor C7 through a fourteenth resistor R14; the 1 st pin of the power management chip U1 is connected to the 1 st gate G1 of the eighth MOS transistor Q8; the 31 st pin of the power management chip U1 is connected to the other end of the seventh capacitor C7, the 1 st source S1, the 2 nd drain D2 of the eighth MOS transistor Q8, and one end of the first inductor L1; a 2 nd source S2 of the eighth MOS transistor Q8 is grounded, a 2 nd pin of the power management chip U1 is connected with a 2 nd gate G2 of the eighth MOS transistor Q8, a 21 nd pin of the power management chip U1 is connected with one end of a twelfth resistor R12, one end of a fourth capacitor C4, one end of an eleventh resistor R11 and one end of a sixth capacitor C6; the 20 th pin of the power management chip U1 is connected with one end of a thirteenth resistor R13, the other end of a fourth capacitor C4, the other end of an eleventh resistor R11 and one end of a fifth capacitor C5; a pin 25 of the power management chip U1 is connected to one end of the eighth capacitor C8 through a fifteenth resistor R15, and a pin 24 of the power management chip U1 is connected to a1 st gate G1 of the ninth MOS transistor Q9; a 26 th pin of the power management chip U1 is connected to the other end of the eighth capacitor C8, the 1 st source S1, the 2 nd drain D2 of the ninth MOS transistor Q9, and the other end of the first inductor L1; the 23 rd pin of the power management chip U1 is connected to the 2 nd gate G2 of the ninth MOS transistor Q9, and the 2 nd source S2 of the ninth MOS transistor Q9 is grounded; a1 st drain D1 of the ninth MOS transistor Q9 is connected to one end of a tenth capacitor C10, the other end of a twelfth resistor R12, the other end of a thirteenth resistor R13 and one end of a 5V power supply terminal 5V _ SYS _ CSP2_ R tenth capacitor C10, and is connected to one end of a sixteenth resistor R16 and the source of the tenth MOS transistor Q10; the other end of the sixteenth resistor R16 is connected with the gate of the tenth MOS transistor Q10, the gate of the eleventh MOS transistor Q11 and the drain of the twelfth MOS transistor Q12; the drain of the tenth MOS transistor Q10 is connected to the drain of the eleventh MOS transistor Q11, one end of the ninth capacitor C9 and the first peripheral voltage terminal VDD _5V0_ IO _ SYS _ 1; the grid electrode of the twelfth MOS tube Q12 is connected with an external CPU; the source of the eleventh MOS transistor Q11, the source of the twelfth MOS transistor Q12, and the other end of the ninth capacitor C9 are all grounded.

The power management circuit 220 is mainly used for providing stably-output voltage and current for normal operation of the whole USB portion of the control module 10, the power management chip U1 adopts NCP81239 of ON Semiconductor, and the power supply voltage VCC _ SRC is input from

pins

4 and 6 of the power management chip U1. The external CPU controls the 9 th and 10 th pins of U1 through I2C signals (I2C _ GP5_ CLK, I2C _ GP5_ DAT), and controls the voltage output of the +5V power supply voltage (output from 5V power supply terminal 5V _ SYS _ CSP2_ R) and other peripheral voltage networks in conjunction with the power management chips U1, Q8, Q9 and associated peripheral circuits. The resistors R11, C4, R12, R13, C5 and C6 form a positive feedback oscillation protection circuit in the circuit, when the circuit detects that the external power supply is reversely connected or the current is too large, the positive feedback oscillation protection circuit feeds back the current to the inside of the U1 through the 20 th pin and the 21 st pin of the U1, controls the 1 st pin and the 24 th pin of the U1 to output high level to the gates (G) of the Q8 and the Q9, and switches on the Q8 and the Q9 to rapidly cut off the external power supply. The 29 th, 30 th and 15 th legs of U1 primarily serve as decoupling. The 25 th and 32 th RC circuits (R14 and C7, R15 and C8) of U1 constitute an internal self-starting source, mainly functioning to balance internal voltages. The external MOS tubes of Q8 and Q9 are mainly used for outputting stable voltage during normal work, can bear the maximum large current of 20A output, and provide guarantee for peripheral equipment to use 4 paths of USB large-current equipment at the same time. When the USB3.0 transmits image and data signals at high speed, the peak current of each path can reach more than 5V/3A, if the 4 paths of USB simultaneously transmit and receive data, the rated working current is at least more than 12A.

Referring to fig. 4, the management protocol control circuit 230 includes a control chip U2, a first clock chip U3, an eleventh capacitor C11, and a twelfth capacitor C12; the 15 th pin to the 17 th pin of the control chip U2 are all connected to the USB3.0 expansion processing chip 11 in the control module 10, the 38 th pin of the control chip U2 is connected to one end of a twelfth capacitor C12 and the HOT2 pin of the first clock chip U3, the 39 th pin of the control chip U2 is connected to one end of an eleventh capacitor C11 and the HOT pin of the first clock chip U3, the other end of the twelfth capacitor C12 is grounded, and the GND pin of the first clock chip U3 is connected to the other end of the eleventh capacitor C11 and ground.

The USB management protocol in the control chip U2 uses the Serpula chip IC CYPD4226-40LQXIT, and the BIOS protocol of the USB is integrated in the control chip U2, mainly for compatible use of different USB external devices. The U2 communicates with the USB3.0 expansion processing chip 11 through I2C signals (I2C _ GP2_ CLK _ LVS, I2C _ GP2_ DAT _ LVS, GPIO10_ I2C _ INT _ CCG4) of the 15 th to 17 th pins, establishes handshake connection according to USB standard protocols corresponding to different peripheral configurations of the USB, and achieves the effect of being compatible with different USB peripheral devices.

The flash EEPROM (i.e. the data register circuit 240) for data register is integrated in the U2, and is mainly used for temporarily storing protocol data for USB communication, and when the system power is off, the data in the data register is automatically cleared. The phase-locked loop control of the phase-locked loop control circuit 250 mainly provides a precise clock for the USB, controls the frequency and phase of the oscillation signal inside the loop, such as U3 in fig. 4 provides a precise 25MHZ clock signal, and C11 and C12 are load capacitors and mainly filter external ripple interference signals.

Referring to fig. 5 and 6, the peripheral circuit of the USB3.0 expansion chip 11 includes a seventeenth resistor R17, a thirteenth capacitor C13, a fourteenth capacitor C14, a fifteenth capacitor C15, and a second clock chip U4.

The PERST # pin, the PCIEKP pin, the PCIEKM pin, the PCIEXP pin and the PCIEXM pin of the USB3.0 extended processing chip 11 are respectively connected with an Invitta (NVIDIA Jetson) module through a 0 omega resistor; the PCIETX pin and the PCIETX pin of the USB3.0 extended processing chip 11 are respectively connected with an Invitta (NVIDIA Jetson) module through a capacitor of 0.1 uF; the pcie next pin of the USB3.0 expansion processing chip 11 is connected to one end of the seventeenth resistor R17, the pcie cap pin of the USB3.0 expansion processing chip 11 is connected to one end of the thirteenth capacitor C13, and the other end of the seventeenth resistor R17 is connected to the other end of the thirteenth capacitor C13 and ground; u2DP0 foot-U2 DP3 foot, U2DM0 foot-U2 DM3 foot, SSTP 0 foot-SSTP 3 foot, SSTP 0 foot-SSTP XM3 foot, SSRXP0 foot-SSRXP 3 foot and SSRXM0 foot-SSRXM 3 foot of the USB3.0 expansion processing chip 11 are all connected with a filter port circuit; the XSCO pin of the USB3.0 extended processing chip 11 is connected with the HOT pin of the second clock chip U4 and one end of a fifteenth capacitor C15, and the XSCI pin of the USB3.0 extended processing chip 11 is connected with the HOT2 pin of the second clock chip U4 and one end of a fourteenth capacitor C14; the other end of the fifteenth capacitor C15 is connected with the other end of the fourteenth capacitor C14, the GND pin of the second clock chip U4 and the ground; the ROMSDA pin, the ROMSCL pin and the ROMPRES pin of the USB3.0 expansion processing chip 11 are correspondingly connected with the 16 th pin, the 17 th pin and the 15 th pin of the control chip U2.

The filter port circuit comprises a first filter E1, a second filter E2, a third filter E3, a fourth filter E4, a fifth filter E5, a sixth filter E6, a first USB input/output port CON1 and a second USB input/output port CON 2; the 1 st pin, the 2 nd pin, the 4 th pin and the 5 th pin of the first filter E1 are correspondingly connected with an SSRXP0 pin, an SSRXM0 pin, a U2DP0 pin and a U2DM0 pin of the USB3.0 expansion processing chip 11; the 6 th pin, the 7 th pin, the 9 th pin and the 10 th pin of the first filter E1 are correspondingly connected with the DN pin, the DP pin, the SSRXN pin and the SSRXP pin of the first USB input/output port CON 1; the 1 st pin, the 2 nd pin, the 4 th pin and the 5 th pin of the second filter E2 are correspondingly connected with the SSTP 0 pin, the SSTP 0 pin, the SSTP 1 pin and the SSTP 1 pin of the USB3.0 expansion processing chip 11; the 6 th pin, the 7 th pin, the 9 th pin and the 10 th pin of the second filter E2 are correspondingly connected with the SSTXP2 pin, the SSTXN2 pin, the SSTXN pin and the SSTXP pin of the first USB input/output port CON 1; the 1 st pin, the 2 nd pin, the 4 th pin and the 5 th pin of the third filter E3 are correspondingly connected with the SSRXM1 pin, the SSRXP1 pin, the U2DP1 pin and the U2DM1 pin of the USB3.0 expansion processing chip 11; the 6 th pin, the 7 th pin, the 9 th pin and the 10 th pin of the third filter E3 are correspondingly connected with the DN2 pin, the DP2 pin, the SSRXP2 pin and the SSRXN2 pin of the first USB input/output port CON 1; the 1 st pin, the 2 nd pin, the 4 th pin and the 5 th pin of the fourth filter E4 are correspondingly connected with the SSRXP2 pin, the SSRXM2 pin, the U2DP2 pin and the U2DM2 pin of the USB3.0 expansion processing chip 11; the 6 th pin, the 7 th pin, the 9 th pin and the 10 th pin of the fourth filter E4 are correspondingly connected with the DN pin, the DP pin, the SSRXN pin and the SSRXP pin of the second USB input/output port CON 2; the 1 st pin, the 2 nd pin, the 4 th pin and the 5 th pin of the fifth filter E5 are correspondingly connected with the U2DP3 pin, the U2DM3 pin, the SSTP 2 pin and the SSTX 2 pin of the USB3.0 expansion processing chip 11; the 6 th pin, the 7 th pin, the 9 th pin and the 10 th pin of the fifth filter E5 are correspondingly connected with the SSTXN pin, the SSTXP pin, the DN2 pin and the DP2 pin of the second USB input/output port CON 2; the 1 st pin, the 2 nd pin, the 4 th pin and the 5 th pin of the sixth filter E6 are correspondingly connected with the SSTP 3 pin, the SSTP XM3 pin, the SSTP 3 pin and the SSTP XM3 pin of the USB3.0 expansion processing chip 11; the pins 6, 7, 9 and 10 of the sixth filter E6 are connected to the pins SSRXN2, SSRXP2P, SSTXN2 and SSTXP2 of the second USB input/output port CON2, respectively.

The USB3.0 expansion processing chip 11 adopts FL1100IC of american ruesi electronics, and mainly functions to transmit and receive data, bus node control, and software algorithm processing in a data bus from a pcie x2 data interface signal output by an NVIDIA Jetson module in an IC, and cooperate with the peripheral auxiliary module 20 to expand and output 4 USB3.0 data signals. PCIE signals of the Yingwei Dai (NVIDIA Jetson) module are input into the USB3.0 expansion processing chip 11 from a PERST # pin, a PCIEKP pin, a PCIEKM pin, a PCIEXP pin, a PCIEXM pin and a PCIETXM pin, software algorithm processing is carried out inside, and data signals of the USB3.0 are output from U2DP 0-U2 DP03 pins, U2DM 0-U2 DM3 pins, SSTP 0-SSTP 3 pins, SSTP XM 0-SSTP 3 pins, SSRXP 0-SSRXP 3 pins and SSM 0-RXSM 3 pins of the USB3.0 expansion processing chip 11. The USB3.0 expansion processing chip 11 has four sets of such USB3.0 data signals in total, for example, the B2 pin, the a4 pin, the B4 pin, the B5 pin, the a7 pin, the a8 pin, the B8 pin, and the a10 pin are data output signal pins (corresponding to 0L) of the 1 st set of USB3.0, among other signals, the signal ending with 1L is the 2 nd set of USB3.0 data signal, the signal ending with 2L is the 3 rd set of USB3.0 data signal, and the signal ending with 3L is the 4 th set of USB3.0 data signal. Each group of output signals are subjected to ESD protection and EMI filtering respectively through E1-E6, and USB3.0 data signals are sent to the USB input/output ports (CON1 and CON 2). R17 and C13 act as decoupling and filtering. The pins a30, a32 and B26 of the USB3.0 expansion processing chip 11 correspond to data, clock and interrupt signals of I2C, and are mainly used for real-time communication with an external CPU and the 15 th, 16 th and 17 th pins U2 in fig. 4.

The SSTP 0 pin to the SSTP 3 pin and the SSTP XM0 pin to the SSTP 3 pin of the USB3.0 expansion processing chip 11 can be respectively connected with corresponding pins on the filter through a 0.1uF capacitor. Data is isolated and interference-free by the capacitors.

In specific implementation, CON1 and CON2 in fig. 6 are dual-layer USB3.0 ports, and can simultaneously access 4 USB3.0 external terminal devices, where the maximum transferable rate of each external terminal device is 5.0Gbps (500MB/s), and these 4 external terminal interfaces are simultaneously downward compatible with the access of USB2.0 terminal devices.

Based on above-mentioned multichannel USB jointing equipment, the utility model discloses still provide a multichannel USB jointing equipment's data control method, please refer to FIG. 7, the data control method includes:

s10, converting the input voltage into a power supply voltage and a peripheral voltage through the peripheral auxiliary module to supply power to the control module;

s20, the peripheral auxiliary module performs USB communication protocol configuration on the control module according to the currently connected USB peripheral;

and S30, performing packet interaction on the data transmitted by the platform through the control module, outputting a USB3.0 data signal, and outputting the data through the corresponding USB3.0 port after real-time distribution.

To sum up, the utility model provides a multichannel USB connecting device and data control method thereof, because USB 3.0's transmission rate and response speed are all very fast, and theoretical maximum transmission rate is up to 5G per second, therefore USB3.0 equipment can be fine solve the slow problem of USB2.0 transmission speed; meanwhile, the system can be externally connected with 4 paths of USB3.0 equipment and can be used for high-speed transmission of images and data, and can be applied to the artificial intelligence fields of inspection robots, unmanned merchant face-brushing payment, industrial automation control and the like; compared with the traditional USB2.0 external equipment, the hardware interface is richer, the transmission speed is high, the efficiency is high, the time delay is avoided, the data transmission is stable, and the data are not easy to lose.

It should be understood that equivalent alterations and modifications can be made by those skilled in the art according to the technical solution of the present invention and the inventive concept thereof, and all such alterations and modifications should fall within the scope of the appended claims.

Claims

1. A multi-path USB connection device is externally connected with a platform, a CPU and an English Wittia module are arranged on the platform, the multi-path USB connection device comprises a shell, a circuit board is arranged in the shell, and the multi-path USB connection device is characterized in that a control module, a peripheral auxiliary module and a plurality of USB3.0 ports are integrated on the circuit board; the control module is connected with the peripheral auxiliary module and the plurality of USB3.0 ports;

2. The multi-channel USB connection device of claim 1, wherein the peripheral auxiliary module comprises a power control and protection circuit, a power management circuit, a management protocol control circuit, a data register circuit and a phase-locked loop control circuit; the power supply control and protection circuit is connected with the power supply management circuit and the management protocol control circuit, and the management protocol control circuit is connected with the data register circuit and the phase-locked loop control circuit;

3. The multi-channel USB connection device of claim 2, wherein the control module comprises a USB3.0 expansion processing chip and a filter port circuit; the USB3.0 expansion processing chip is connected with a filter port circuit, and the filter port circuit is connected with a power management circuit;

4. The multi-channel USB connection device according to claim 3, wherein the power control and protection circuit includes a first interface, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, a first triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a first capacitor, a second capacitor, and a third capacitor;

5. The multi-channel USB connection device according to claim 4, wherein the power management circuit includes a power management chip, a first inductor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor and a tenth capacitor;

6. The multi-channel USB connection device of claim 5, wherein the management protocol control circuit comprises a control chip, a first clock chip, an eleventh capacitor and a twelfth capacitor;

7. The multi-channel USB connection device of claim 6, wherein the peripheral circuit of the USB3.0 expansion processing chip comprises a seventeenth resistor, a thirteenth capacitor, a fourteenth capacitor, a fifteenth capacitor and a second clock chip;

8. The multi-channel USB connection device of claim 5, wherein the filter port circuit comprises a first filter, a second filter, a third filter, a fourth filter, a fifth filter, a sixth filter, a first USB input/output port, and a second USB input/output port;

9. The multi-channel USB connection device of claim 8, wherein the power management chip has a model number of NCP81239, the control chip has a model number of CYPD4226-40LQXIT, and the USB3.0 extended processing chip has a model number of FL 1100.