CN110134620A - A kind of multichannel USB connection equipment and its data control method - Google Patents
A kind of multichannel USB connection equipment and its data control method Download PDFInfo
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- CN110134620A CN110134620A CN201910400773.1A CN201910400773A CN110134620A CN 110134620 A CN110134620 A CN 110134620A CN 201910400773 A CN201910400773 A CN 201910400773A CN 110134620 A CN110134620 A CN 110134620A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention discloses a kind of multichannel USB connection equipment and its data control methods, the external platform of multichannel USB connection equipment, including a shell, the shell is interior to be arranged a circuit board, it is characterized in that, being integrated with control module, peripheral supplementary module and several ports USB3.0 on the circuit board；Control module connects peripheral supplementary module and several ports USB3.0；The periphery supplementary module converts input voltage into supply voltage and peripheral voltage and powers to control module, peripheral supplementary module carries out the configuration of USB communications protocol to control module according to the USB peripheral currently connected, the data that control module transmits platform export USB3.0 data-signal after being grouped interaction, are exported after distribution by the corresponding port USB3.0 in real time.Due to USB3.0 transmission rate and response speed all quickly, the external equipment that existing USB2.0 can be solved transmits unstable problem.
Description
Technical field
The present invention relates to USB technical field, in particular to a kind of multichannel USB connection equipment and its data control method.
Background technique
In actual application, especially in crusing robot, the unmanned super brush face of quotient is paid, and industrial automatic control etc. is answered
The field, the external equipments such as equipment needs while the USB3.0 camera, USB flash disk, expansion card that access multi-path high-definition.But energy in equipment
The number of the USB port of external external equipment is less simultaneously, and usually only 1-2, many functions are had no idea same in equipment
Shi Yunhang is completed, and can access the external equipment of multi-path high-definition USB simultaneously there is an urgent need to equipment to meet the practical application need of client
It asks.
Meanwhile the transmission speed of traditional external equipment is slower, as the theoretical highest transmission data of USB2.0 only have 480M
Per second, when transmission high-resolution, the big image data of data volume, USB2.0 can not meet the requirement of rate applications at all, special
It is not obvious insufficient in terms of the image-capture of population intelligent data.And USB2.0 loses the phenomenon that data packet especially severe, greatly
The accuracy and real-time of data are affected greatly.
In addition, the external equipment of USB2.0 due to being influenced by transmission rate is slow, transmit it is unstable, it is especially high in transmission
When clear big data, often be easy to cause system card machine, data-bag lost, it is serious also will cause that system directly crashes show
As,
Therefore, it is necessary to be improved to the prior art.
Summary of the invention
In view of the above technical problems, the embodiment of the invention provides a kind of multichannel USB connection equipment and its data controlling parties
Method, to solve the problems, such as that it is unstable that the external equipment of existing USB2.0 transmits.
The embodiment of the present invention provides a kind of multichannel USB connection equipment, external platform, is provided with CPU and English on the platform
Big to reach module, the multichannel USB connection equipment includes a shell, a circuit board is arranged in the shell, which is characterized in that described
Control module, peripheral supplementary module and several ports USB3.0 are integrated on circuit board；Control module connection periphery auxiliary mould
Block and several ports USB3.0；
The periphery supplementary module converts input voltage into supply voltage and peripheral voltage and powers to control module, periphery
Supplementary module carries out the configuration of USB communications protocol to control module according to the USB peripheral currently connected, and control module transmits platform
Data be grouped interaction after export USB3.0 data-signal, in real time distribution after by the corresponding port USB3.0 export.
Optionally, in the multichannel USB connection equipment, the periphery supplementary module includes power supply control and protection electricity
Road, electric power management circuit, management agreement control circuit, data register circuit and phase-locked loop control circuit；Power supply control and
Protect circuit connection electric power management circuit and management agreement control circuit, management agreement control circuit connect data register circuit and
Phase-locked loop control circuit；
Input voltage is exported and is powered by the power supply control and protection circuit, and converts input voltage into supply voltage
Power supply；Supply voltage is converted to several preset peripheral voltages simultaneously according to the I2C signal of input by the electric power management circuit
Power supply is exported after carrying out pressure stabilizing；Management agreement control circuit configures corresponding protocol of USB standard according to the USB peripheral currently connected
It establishes to shake hands between system and connect；Data register circuit stores protocol data when communicating for USB, phase-locked loop control circuit is used
The clock signal needed for generating management agreement control circuit.
Optionally, in the multichannel USB connection equipment, the control module includes USB3.0 extension process chip and filter
Wave port circuit；The USB3.0 extension process chip connection filtering port circuit, filtering port circuit connection power management electricity
Road；
After the USB3.0 extension process chip carries out bus node control, grouping interactive controlling to the data that platform transmits
Export USB3.0 data-signal, filtering port circuit carries out after EMI filtering from the corresponding end USB3.0 USB3.0 data-signal
Mouth output.
Optionally, in the multichannel USB connection equipment, power supply control and protection circuit include first interface, the
One metal-oxide-semiconductor, the second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the one or three pole
Pipe, first resistor, second resistance, 3rd resistor, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance,
Nine resistance, the tenth resistance, first capacitor, the second capacitor and third capacitor；
The DC foot of the first interface connects drain electrode, Input voltage terminal, one end of first resistor and the third of the first metal-oxide-semiconductor
One end of resistance；One end of the other end connection second resistance of first resistor and the 2nd foot of third metal-oxide-semiconductor, the of third metal-oxide-semiconductor
6 feet connect CPU, and the 1st foot of third metal-oxide-semiconductor and the other end of second resistance are grounded；The other end connection the 4th of 3rd resistor
One end of resistance, the base stage of the first triode and third metal-oxide-semiconductor the 3rd foot；The hair of the other end of 4th resistance, the first triode
4th foot of emitter-base bandgap grading and third metal-oxide-semiconductor is grounded；5th foot of third metal-oxide-semiconductor connects CPU；The collector connection the of first triode
The grid of two metal-oxide-semiconductors, one end of first capacitor, one end of the 5th resistance and the grid of the first metal-oxide-semiconductor；The source electrode of first metal-oxide-semiconductor
Connect the source electrode of the other end of the 5th resistance, the other end of first capacitor and the second metal-oxide-semiconductor；The drain electrode connection the of second metal-oxide-semiconductor
The source electrode of four metal-oxide-semiconductors, one end of third capacitor, the 9th resistance one end and modulation voltage end；The grid connection the of 4th metal-oxide-semiconductor
One end of the other end of three capacitors, the other end of the 9th resistance and the tenth resistance；Drain electrode the second capacitor of connection of 4th metal-oxide-semiconductor
One end, the drain electrode of the 6th metal-oxide-semiconductor and power voltage terminal；The other end of second capacitor passes through the 8th resistance eutral grounding, the second capacitor
The other end also passes through the 7th resistance and connects one end of the 6th resistance and the grid of the 5th metal-oxide-semiconductor, the drain electrode connection of the 5th metal-oxide-semiconductor
CPU, the grid of the 6th metal-oxide-semiconductor connect drain electrode and the other end of the tenth resistance of the 7th metal-oxide-semiconductor, the grid connection of the 7th metal-oxide-semiconductor
CPU；The source electrode of 5th metal-oxide-semiconductor, source electrode, the source electrode of the 7th metal-oxide-semiconductor, the other end of the 6th resistance of the 6th metal-oxide-semiconductor are grounded.
Optionally, in the multichannel USB connection equipment, the electric power management circuit includes power management chip, first
Inductance, the 8th metal-oxide-semiconductor, the 9th metal-oxide-semiconductor, the tenth metal-oxide-semiconductor, the 11st metal-oxide-semiconductor, the 12nd metal-oxide-semiconductor, eleventh resistor, the 12nd
Resistance, thirteenth resistor, the 14th resistance, the 15th resistance, the 16th resistance, the 4th capacitor, the 5th capacitor, the 6th capacitor,
7th capacitor, the 8th capacitor, the 9th capacitor and the tenth capacitor；
9th foot of the power management chip and the 10th foot are all connected with CPU, and the 6th foot of power management chip and the 4th foot are equal
Power voltage terminal is connected, the 5th foot of power management chip connects the 1st drain electrode of the 8th metal-oxide-semiconductor, the 32nd foot of power management chip
One end of the 7th capacitor is connected by the 14th resistance；1st foot of power management chip connects the 1st grid of the 8th metal-oxide-semiconductor；Electricity
31st foot of source control chip connects the other end of the 7th capacitor, the 1st source electrode of the 8th metal-oxide-semiconductor, the 2nd drain electrode and the first inductance
One end；2nd source electrode of the 8th metal-oxide-semiconductor is grounded, and the 2nd foot of power management chip connects the 2nd grid of the 8th metal-oxide-semiconductor, power supply pipe
Manage the 21st foot connection one end of twelfth resistor, one end of the 4th capacitor, one end of eleventh resistor and the 6th capacitor of chip
One end；The 20th foot connection one end of thirteenth resistor of power management chip, the other end of the 4th capacitor, eleventh resistor
One end of the other end and the 5th capacitor；25th foot of power management chip connects one end of the 8th capacitor by the 15th resistance,
24th foot of power management chip connects the 1st grid of the 9th metal-oxide-semiconductor；26th foot of power management chip connects the 8th capacitor
The other end, the 1st source electrode of the 9th metal-oxide-semiconductor, the 2nd drain electrode and the first inductance the other end；23rd foot of power management chip connects
2nd grid of the 9th metal-oxide-semiconductor, the 2nd source electrode ground connection of the 9th metal-oxide-semiconductor；The one of 1st drain electrode the tenth capacitor of connection of the 9th metal-oxide-semiconductor
End, the other end of twelfth resistor, the other end of thirteenth resistor and 5V power end；The 16th electricity of one end connection of tenth capacitor
The source electrode of one end of resistance and the tenth metal-oxide-semiconductor；The other end of 16th resistance connects the grid of the tenth metal-oxide-semiconductor, the 11st metal-oxide-semiconductor
The drain electrode of grid and the 12nd metal-oxide-semiconductor；The drain electrode connection drain electrode of the 11st metal-oxide-semiconductor of tenth metal-oxide-semiconductor, one end of the 9th capacitor and
First peripheral voltage end；The grid of 12nd metal-oxide-semiconductor connects CPU；The source electrode of 11st metal-oxide-semiconductor, the source electrode of the 12nd metal-oxide-semiconductor and
The other end of 9th capacitor is grounded.
Optionally, in the multichannel USB connection equipment, the management agreement control circuit includes control chip, first
Clock chip, the 11st capacitor and the 12nd capacitor；
The 15th foot to the 17th foot of the control chip is all connected with the USB3.0 extension process chip in control module, controls
38th foot of chip connects one end of the 12nd capacitor and the HOT2 foot of the first clock chip, controls the 39th foot connection the of chip
The HOT foot of 11 one end capacitor C11 and the first clock chip, the other end ground connection of the 12nd capacitor, the GND of the first clock chip
Foot connects the other end and ground of the 11st capacitor.
Optionally, in the multichannel USB connection equipment, the peripheral circuit of the USB3.0 extension process chip includes the
17 resistance, the 13rd capacitor, the 14th capacitor, the 15th capacitor and second clock chip；
The PERST# foot of the USB3.0 extension process chip, PCIECKP foot, PCIECKM foot, PCIERXP foot,
PCIERXM foot is all connected with tall and handsome up to module；The PCIEREXT foot of USB3.0 extension process chip connects one end of the 17th resistance,
The PCIECAP foot of USB3.0 extension process chip connects one end of the 13rd capacitor, the other end connection the tenth of the 17th resistance
The other end and ground of three capacitors；U2DP0 foot~U2DP3 foot of USB3.0 extension process chip, U2DM0 foot~U2DM3 foot,
SSTXP0 foot~SSTXP3 foot, SSTXM0 foot~SSTXM3 foot, SSRXP0 foot~SSRXP3 foot, SSRXM0 foot~SSRXM3 foot are equal
Connection filtering port circuit；The HOT foot and the 15th electricity of the XSCO foot connection second clock chip of USB3.0 extension process chip
One end of appearance, USB3.0 extension process chip XSCI foot connection second clock chip HOT2 foot and the 14th capacitor one
End；The other end of 15th capacitor connects the GND foot and ground of the other end of the 14th capacitor, second clock chip；USB3.0 expands
ROMSDA foot, ROMSCL foot and the ROMPRES foot of exhibition processing chip are correspondingly connected with control the 16th foot of chip, the 17th foot, the
15 feet.
Optionally, in the multichannel USB connection equipment, the filtering port circuit includes first filter, the second filter
Wave device, third filter, the 4th filter, the 5th filter, the 6th filter, the first USB input and output port and the 2nd USB
Input/output port；
The 1st foot, the 2nd foot, the 4th foot, the 5th foot of the first filter are correspondingly connected with USB3.0 extension process chip
SSRXP0 foot, SSRXM0 foot, U2DP0 foot, U2DM0 foot；The 6th foot, the 7th foot, the 9th foot, the 10th foot of first filter are corresponding to be connected
Connect DN foot, DP foot, SSRXN foot, the SSRXP foot of the first USB input and output port；The 1st foot, the 2nd foot, the 4th of second filter
Foot, the 5th foot are correspondingly connected with SSTXP0 foot, SSTXM0 foot, SSTXM1 foot, the SSTXP1 foot of USB3.0 extension process chip；Second
The 6th foot, the 7th foot, the 9th foot, the 10th foot of filter are correspondingly connected with SSTXP2 foot, the SSTXN2 of the first USB input and output port
Foot, SSTXN foot, SSTXP foot；The 1st foot, the 2nd foot, the 4th foot, the 5th foot of third filter are correspondingly connected with USB3.0 extension process
SSRXM1 foot, SSRXP1 foot, U2DP1 foot, the U2DM1 foot of chip；The 6th foot, the 7th foot, the 9th foot, the 10th foot of third filter
It is correspondingly connected with DN2 foot, DP2 foot, SSRXP2 foot, the SSRXN2 foot of the first USB input and output port；1st foot of the 4th filter,
2nd foot, the 4th foot, the 5th foot are correspondingly connected with the SSRXP2 foot, SSRXM2 foot, U2DP2 foot, U2DM2 of USB3.0 extension process chip
Foot；The 6th foot, the 7th foot, the 9th foot, the 10th foot of 4th filter are correspondingly connected with DN foot, the DP of the second USB input and output port
Foot, SSRXN foot, SSRXP foot；The 1st foot, the 2nd foot, the 4th foot, the 5th foot of 5th filter are correspondingly connected with USB3.0 extension process
U2DP3 foot, U2DM3 foot, SSTXP2 foot, the SSTXM2 foot of chip；The 6th foot, the 7th foot, the 9th foot, the 10th foot of 5th filter
It is correspondingly connected with SSTXN foot, SSTXP foot, DN2 foot, the DP2 foot of the second USB input and output port；1st foot of the 6th filter,
2 feet, the 4th foot, the 5th foot are correspondingly connected with the SSTXP3 foot, SSTXM3 foot, SSTXP3 foot, SSTXM3 of USB3.0 extension process chip
Foot；The 6th foot, the 7th foot, the 9th foot, the 10th foot of 6th filter be correspondingly connected with the second USB input and output port SSRXN2 foot,
SSRXP2P foot, SSTXN2 foot, SSTXP2 foot.
Optionally, in the multichannel USB connection equipment, the model NCP81239 of the power management chip, control
The model FL1100 of model CYPD4226-40LQXIT, USB3.0 the extension process chip of chip.
Second aspect of the embodiment of the present invention provides a kind of data controlling party using the multichannel USB connection equipment
Method comprising:
Step A, supply voltage and peripheral voltage is converted input voltage by peripheral supplementary module to supply control module
Electricity；
Step B, peripheral supplementary module carries out the configuration of USB communications protocol to control module according to the USB peripheral currently connected；
Step C, it is grouped after interaction by the data that control module transmits platform and exports USB3.0 data-signal, it is real
When distribution after by the corresponding port USB3.0 export.
Compared to the prior art, multichannel USB connection equipment provided by the invention and its data control method, multichannel USB connect
The external platform of equipment and CPU, including a shell are met, a circuit board is set in the shell, which is characterized in that on the circuit board
It is integrated with control module, peripheral supplementary module and several ports USB3.0；Control module connects peripheral supplementary module and several
A port USB3.0；The periphery supplementary module converts input voltage into supply voltage and peripheral voltage and supplies control module
Electricity, peripheral supplementary module carry out the configuration of USB communications protocol, control module pair to control module according to the USB peripheral currently connected
The data of platform transmission export USB3.0 data-signal after being grouped interaction, pass through the corresponding port USB3.0 after distribution in real time
Output.Due to USB3.0 transmission rate and response speed all quickly, can be solved existing USB2.0 external equipment transmission not
Stable problem.
Detailed description of the invention
Fig. 1 is the structural block diagram of multichannel USB connection equipment provided in an embodiment of the present invention.
Fig. 2 is the circuit diagram of power supply control and protection circuit in multichannel USB connection equipment provided in an embodiment of the present invention.
Fig. 3 is the circuit diagram of electric power management circuit in multichannel USB connection equipment provided in an embodiment of the present invention.
Fig. 4 is the circuit diagram of management agreement control circuit in multichannel USB connection equipment provided in an embodiment of the present invention.
Fig. 5 is the circuit diagram of USB3.0 extension process chip in multichannel USB connection equipment provided in an embodiment of the present invention.
Fig. 6 is the circuit diagram that port circuit is filtered in multichannel USB connection equipment provided in an embodiment of the present invention.
Fig. 7 is the data control method flow chart of multichannel USB connection equipment provided in an embodiment of the present invention.
Specific embodiment
The present invention provides a kind of multichannel USB connection equipment and its data control method, using USB3.0 technology, transmission speed
Rate and response speed all quickly, can be solved existing USB2.0 and transmit unstable problem.To make the purpose of the present invention, technical side
Case and effect are clearer, clear, and the present invention is described in more detail as follows in conjunction with drawings and embodiments.It should be appreciated that
Described herein specific examples are only used to explain the present invention, is not intended to limit the present invention.
Referring to Fig. 1, a kind of multichannel USB connection equipment provided by the invention includes a shell, setting one in the shell
Circuit board is integrated with control module 10, peripheral supplementary module 20 and several ports USB3.0 on the circuit board；The control
Module 10 connects peripheral supplementary module 20 and several ports USB3.0；The periphery supplementary module 20 converts input voltage into
Supply voltage and peripheral voltage power to control module 10, and peripheral supplementary module 20 is according to the USB peripheral currently connected to control
Module 10 configures corresponding protocol of USB standard, and the data that control module 10 transmits platform export after being grouped interaction
USB3.0 data-signal is exported after distribution by the corresponding port USB3.0 in real time.
In the present embodiment, the control module 10 includes USB3.0 extension process chip 11 and filtering port circuit 12；Institute
The connection filtering port circuit of USB3.0 extension process chip 11 is stated, filtering port circuit connects electric power management circuit.It is described
After USB3.0 extension process chip 11 carries out bus transmitting-receiving, bus node control, grouping interactive controlling to the data that platform transmits
Export USB3.0 data-signal, filtering port circuit 12 carries out after EMI filtering from corresponding USB3.0 USB3.0 data-signal
Port output.It is tall and handsome to export PCIEX2 bus interface to USB3.0 extension process chip up to (NVIDIA Jetson) module,
The data of PCIEX2 bus transfer are total through bus transmitting-receiving, bus node control, data inside USB3.0 extension process chip 11
Real-time distribution (being grouped the control of interaction X machine) inside line, last parallel output to 4 groups of ports (port 0~3, Root Port0
~3), the channel of every group of port is carried out after the transmission, exchange, control of usb data respectively through the port the USB3.0 (port USB3.0
0~3) reach USB terminal prot equipment (Port0~3 Connector), the bandwidth in 4 groups of every group of channels USB3.0 all,
It is all to export in parallel, transmission rate is all 5G/S.
The periphery supplementary module 20 includes that power supply controls and protect circuit 210, electric power management circuit 220, management agreement
Control circuit 230 (i.e. USB BIOS management agreement controls), data register circuit 240 and phase-locked loop control circuit 250；The electricity
Source control and protection circuit 210 connect electric power management circuit 220 and management agreement control circuit 230, management agreement control circuit
230 connection data register circuits 240 and phase-locked loop control circuit 250.
Input voltage VCC_DCIN is exported and is powered by the power supply control and protection circuit 210, and input voltage is converted
It powers for supply voltage VCC_SRC.The electric power management circuit 220 is converted to supply voltage according to the I2C signal of input
Several preset peripheral voltages simultaneously carry out output power supply after pressure stabilizing.Management agreement control circuit 230 is according to the USB currently connected
Connection of shaking hands is established between the corresponding protocol of USB standard of peripheral configuration and system.When data register circuit 240 is communicated for USB
Protocol data is stored, phase-locked loop control circuit 250 is for clock signal needed for generating management agreement control circuit 230.
Referring to Figure 2 together, power supply control and protection circuit 210 include first interface J1, the first metal-oxide-semiconductor Q1, the
Two metal-oxide-semiconductor Q2, third metal-oxide-semiconductor Q3 (including Q3A and Q3B), the 4th metal-oxide-semiconductor Q4, the 5th metal-oxide-semiconductor Q5, the 6th metal-oxide-semiconductor Q6, the 7th
Metal-oxide-semiconductor Q7, the first triode N1, first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5,
6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 9th resistance R9, the tenth resistance R10, first capacitor C1, the second capacitor C2
With third capacitor C3.
The DC foot of the first interface J1 connects the drain electrode of the first metal-oxide-semiconductor Q1, Input voltage terminal (provides input voltage VCC_
DCIN), one end of one end of first resistor R1 and 3rd resistor R3；The one of the other end connection second resistance R2 of first resistor R1
End and third metal-oxide-semiconductor Q3 the 2nd foot (i.e. the grid of Q3A), third metal-oxide-semiconductor Q3 the 6th foot (i.e. the drain electrode of Q3A) connection outside
(DC_IN_EC signal is low and high level to CPU, and the working condition for fed power supplies informs power work in what shape to CPU
State) third metal-oxide-semiconductor Q3 the 1st foot (i.e. the source electrode of Q3A) and the other end of second resistance R2 be grounded；3rd resistor R3's is another
One end, the base stage of the first triode N1 and the 3rd foot (drain electrode of Q3B) of third metal-oxide-semiconductor Q3 of the 4th resistance R4 of end connection；4th
The 4th foot (source electrode of Q3B) of the other end of resistance R4, the emitter of the first triode N1 and third metal-oxide-semiconductor Q3 is grounded；Third
CPU outside the 5th foot (grid of the Q3B) connection of metal-oxide-semiconductor Q3；The collector of first triode N1 connects the second metal-oxide-semiconductor Q2's
Grid, one end of first capacitor C1, one end of the 5th resistance R5 and the first metal-oxide-semiconductor Q1 grid；The source electrode of first metal-oxide-semiconductor Q1 connects
Connect the source electrode of the other end of the 5th resistance R5, the other end of first capacitor C1 and the second metal-oxide-semiconductor Q2；The drain electrode of second metal-oxide-semiconductor Q2
Connect the source electrode of the 4th metal-oxide-semiconductor Q4, one end of third capacitor C3, one end of the 9th resistance R9 and modulation voltage end VDD_MOD；The
The other end, the other end of the 9th resistance R9 and one end of the tenth resistance R10 of the grid connection third capacitor C3 of four metal-oxide-semiconductor Q4；
One end of the second capacitor C2 of drain electrode connection, the drain electrode of the 6th metal-oxide-semiconductor Q6 and the power voltage terminal of 4th metal-oxide-semiconductor Q4；Second capacitor
The other end of C2 is grounded by the 8th resistance R8, and the other end of the second capacitor C2 also passes through the 6th resistance R6 of the 7th resistance R7 connection
One end and the 5th metal-oxide-semiconductor Q5 grid, the external CPU of the drain electrode connection of the 5th metal-oxide-semiconductor Q5, the grid company of the 6th metal-oxide-semiconductor Q6
Meet drain electrode and the other end of the tenth resistance R10 of the 7th metal-oxide-semiconductor Q7, the CPU outside the grid connection of the 7th metal-oxide-semiconductor Q7；5th
The source electrode of metal-oxide-semiconductor Q5, the source electrode of the 6th metal-oxide-semiconductor Q6, the source electrode of the 7th metal-oxide-semiconductor Q7, the other end of the 6th resistance R6 are grounded.
The power supply control and protection circuit 210 prevent input power electric for preventing supply voltage is reversed from causing short circuit
It presses through high and causes to damage IC and component.Input voltage VCC_DCIN is inputted from first interface J1, normal input voltage model
Enclose is between+13V to+22V.When the supply voltage of input is normal, metal-oxide-semiconductor Q1, Q2 are worked normally, and the 5th foot of Q3 be (Q3B's
Grid) on DC_IN_GATE_CCG4 signal (exported by CPU, CPU by control DC_IN_GATE_CCG4 signal height electricity
Put down reach control USB portion power supply opening and closing) and the 1st foot of Q7 on VIN_PWR_ON signal (exported by CPU,
CPU reaches the opening and closing of control USB portion power supply by controlling the low and high level of VIN_PWR_ON signal) while exporting
High level.DC_IN_GATE_CCG4 signal is used to control the opening and closing of Q3, when DC_IN_GATE_CCG4 signal is high electricity
Usually, metal-oxide-semiconductor Q3B conducting control the first triode N1 conducting conveys input voltage VCC_DCIN so that Q1 and Q2 be made to be connected
To the 4th metal-oxide-semiconductor Q4 the 1st, 2,3 feet.After Q1 and Q2 are normally-open, modulation voltage end VDD_MOD exports modulation voltage.Work as Q7
The 1st foot VIN_PWR_ON signal be high level when, the detection through the 6th metal-oxide-semiconductor Q6 and divider resistance (R1, R2) makes Q4's
5th foot output supply voltage VCC_SRC is to electric power management circuit 220.VIN_PWM_BAD_N signal is exported by CPU, and CPU passes through
The low and high level of VIN_PWM_BAD_N signal is controlled to control the opening and closing of USB portion power supply.Resistance R9, R10 are in circuit
In play a key role, for power supply unlatchings play a part of divide detect and feedback voltage.The grid of metal-oxide-semiconductor Q3B also divides
Not Tong Guo a resistance connect PD power end VDD_3V3_PD, the grid of metal-oxide-semiconductor Q3B also passes through a resistance eutral grounding.
Also referring to Fig. 3, the electric power management circuit 220 includes power management chip U1, the first inductance L1, the 8th
Metal-oxide-semiconductor Q8, the 9th metal-oxide-semiconductor Q9, the tenth metal-oxide-semiconductor Q10, the 11st metal-oxide-semiconductor Q11, the 12nd metal-oxide-semiconductor Q12, eleventh resistor R11,
Twelfth resistor R12, thirteenth resistor R13, the 14th resistance R14, the 15th resistance R15, the 16th resistance R16, the 4th electricity
Hold C4, the 5th capacitor C5, the 6th capacitor C6, the 7th capacitor C7, the 8th capacitor C8, the 9th capacitor C9 and the tenth capacitor C10.
The 9th foot and the 10th foot of the power management chip U1 is all connected with CPU, the 6th foot of power management chip U1 and the 4th
Foot is all connected with power voltage terminal, and the 5th foot of power management chip U1 connects the 1st drain D 1 of the 8th metal-oxide-semiconductor Q8, power management core
The 32nd foot of piece U1 passes through one end of the 7th capacitor C7 of the 14th resistance R14 connection；The 1st foot connection the of power management chip U1
The 1st grid G 1 of eight metal-oxide-semiconductor Q8；The 31st foot of power management chip U1 connects the other end, the 8th metal-oxide-semiconductor Q8 of the 7th capacitor C7
The 1st source S 1, the 2nd drain D 2 and the first inductance L1 one end；The 2nd source S 2 of 8th metal-oxide-semiconductor Q8 is grounded, power management core
The 2nd foot of piece U1 connects the 2nd grid G 2 of the 8th metal-oxide-semiconductor Q8, and the 21st foot of power management chip U1 connects twelfth resistor R12
One end, one end of the 4th capacitor C4, one end of eleventh resistor R11 and the 6th capacitor C6 one end；Power management chip U1
The 20th foot connection one end of thirteenth resistor R13, the other end of the 4th capacitor C4, the other end of eleventh resistor R11 and the
One end of five capacitor C5；The 25th foot of power management chip U1 passes through one end of the 8th capacitor C8 of the 15th resistance R15 connection, electricity
The 24th foot of source control chip U1 connects the 1st grid G 1 of the 9th metal-oxide-semiconductor Q9；The 26th foot connection the 8th of power management chip U1
The other end of the other end of capacitor C8, the 1st source S 1 of the 9th metal-oxide-semiconductor Q9, the 2nd drain D 2 and the first inductance L1；Power management
The 23rd foot of chip U1 connects the 2nd grid G 2 of the 9th metal-oxide-semiconductor Q9, the 2nd source S 2 ground connection of the 9th metal-oxide-semiconductor Q9；9th metal-oxide-semiconductor
Q9 the 1st drain D 1 connection one end of the tenth capacitor C10, the other end of twelfth resistor R12, thirteenth resistor R13 it is another
End connects one end and the tenth metal-oxide-semiconductor of the 16th resistance R16 with one end of the tenth capacitor C10 of 5V power end 5V_SYS_CSP2_R
The source electrode of Q10；The other end of 16th resistance R16 connect the grid of the tenth metal-oxide-semiconductor Q10, the 11st metal-oxide-semiconductor Q11 grid and
The drain electrode of 12nd metal-oxide-semiconductor Q12；The drain electrode, the 9th capacitor C9 for connecting the 11st metal-oxide-semiconductor Q11 that drain of tenth metal-oxide-semiconductor Q10
One end and the first peripheral voltage end VDD_5V0_IO_SYS_1；CPU outside the grid connection of 12nd metal-oxide-semiconductor Q12；11st
The other end of the source electrode of metal-oxide-semiconductor Q11, the source electrode of the 12nd metal-oxide-semiconductor Q12 and the 9th capacitor C9 is grounded.
The normal work that the electric power management circuit 220 is mainly used for the entire USB portion for control module 10 provides surely
Surely the voltage and current exported, NCP81239 of the power management chip U1 using ON Semiconductor, supply voltage
VCC_SRC is inputted from the 4th of power management chip U1,6 feet.External CPU passes through I2C signal (I2C_GP5_CLK, I2C_
GP5_DAT the 9th foot and the 10th foot for) controlling U1, controlled in conjunction with power management chip U1, Q8, Q9 and associated peripheral circuits+
The voltage output of 5V supply voltage (being exported from 5V power end 5V_SYS_CSP2_R) and other peripheral voltage networks.Resistance
R11, C4, R12, R13, C5, C6 form positive feedback oscillation protection circuit in circuit, when the circuit detects that external power supply is reversed
Or electric current it is excessive when, pass through the 20th foot of U1 and the 21st foot feedback to the 1st foot for inside U1, controlling U1 and 24 feet output high level
To the grid (G) of Q8, Q9, external power supply is cut off rapidly in Q8, Q9 conducting.The 29th foot, the 30th foot and the 15th foot of U1 mainly rises and moves back
The effect of coupling.The 25th foot of U1 and RC circuit (R14 and C7, R15 and C8) the composition internal bootstrap of the 32nd foot move source, and main rise is put down
The effect of weighing apparatus builtin voltage.The external metal-oxide-semiconductor of Q8, Q9 are mainly used for exporting in normal work stable voltage, and highest can be with
The high current of carrying output 20A, is provided safeguard using 4 road USB high-current equipments simultaneously for peripheral hardware.In USB3.0 high-speed transfer figure
When picture and data-signal, every road peak value maximum current can achieve 5V/3A or more, carry out the same of data simultaneously if it is 4 road USB
When transmitting-receiving transmission, rated operational current electric current at least wants 12A or more.
Referring to Figure 4 together, the management agreement control circuit 230 includes control chip U2, the first clock chip U3, the
11 capacitor C11 and the 12nd capacitor C12；The 15th foot to the 17th foot of the control chip U2 is all connected in control module 10
38th foot of USB3.0 extension process chip 11, control chip U2 connects one end and the first clock chip of the 12nd capacitor C12
39th foot of the HOT2 foot of U3, control chip U2 connects one end of the 11st capacitor C11 and the HOT foot of the first clock chip U3,
The other end of 12nd capacitor C12 is grounded, and the GND foot of the first clock chip U3 connects the other end and ground of the 11st capacitor C11.
USB management agreement in control chip U2 uses Sai Pula chip IC CYPD4226-40LQXIT, by USB
BIOS protocol integration inside control chip U2, primarily to compatible use different USB external equipments.U2 passes through the 15th
Foot to the 17th foot I2C signal (I2C_GP2_CLK_LVS, I2C_GP2_DAT_LVS, GPIO10_I2C_INT_CCG4) with
USB3.0 extension process chip 11 is communicated, and establishes the company of shaking hands according to the corresponding protocol of USB standard of the different peripheral configuration of USB
It connects, has the function that compatible different USB peripheral is standby.
Wherein, the flash memory EEPROM (i.e. data register circuit 240) of data register is integrated in inside U2, is mainly USB
Communication temporarily stores protocol data, data automatic clear after system power supply power-off, in data register.Phase lock control electricity
The phase lock control on road 250 mainly provides accurately clock for USB, the frequency and phase of control loop internal oscillation signal,
If the U3 in Fig. 4 provides accurately 25MHZ clock signal, C11 and C12 are load capacitance, and it is dry mainly to filter external ripple
Disturb letter.
Also referring to Fig. 5 and Fig. 6, the peripheral circuit of the USB3.0 extension process chip 11 includes the 17th resistance
R17, the 13rd capacitor C13, the 14th capacitor C14, the 15th capacitor C15 and second clock chip U4.
The PERST# foot of the USB3.0 extension process chip 11, PCIECKP foot, PCIECKM foot, PCIERXP foot,
The resistance connection that PCIERXM foot passes through one 0 Ω respectively is tall and handsome up to (NVIDIA Jetson) module；USB3.0 extension process chip
The capacitance connection that 11 PCIETXP foot, PCIETXM foot pass through a 0.1uF respectively is tall and handsome up to (NVIDIA Jetson) module；
The PCIEREXT foot of USB3.0 extension process chip 11 connects one end of the 17th resistance R17, USB3.0 extension process chip 11
PCIECAP foot connect one end of the 13rd capacitor C13, the other end of the 17th resistance R17 connects the another of the 13rd capacitor C13
One end and ground；U2DP0 foot~U2DP3 foot of USB3.0 extension process chip 11, U2DM0 foot~U2DM3 foot, SSTXP0 foot~
SSTXP3 foot, SSTXM0 foot~SSTXM3 foot, SSRXP0 foot~SSRXP3 foot, SSRXM0 foot~SSRXM3 foot are all connected with filtering end
Mouth circuit；The HOT foot and the 15th capacitor C15 of the XSCO foot connection second clock chip U4 of USB3.0 extension process chip 11
One end, the HOT2 foot and the 14th capacitor C14 of the XSCI foot connection second clock chip U4 of USB3.0 extension process chip 11
One end；The other end of 15th capacitor C15 connect the other end of the 14th capacitor C14, second clock chip U4 GND foot and
Ground；ROMSDA foot, ROMSCL foot and the ROMPRES foot of USB3.0 extension process chip 11 are correspondingly connected with the of control chip U2
16 feet, the 17th foot, the 15th foot.
The filtering port circuit includes first filter E1, second filter E2, third filter E3, the 4th filter
E4, the 5th filter E5, the 6th filter E6, the first USB input and output port CON1 and the second USB input and output port
CON2；The 1st foot, the 2nd foot, the 4th foot, the 5th foot of the first filter E1 is correspondingly connected with USB3.0 extension process chip 11
SSRXP0 foot, SSRXM0 foot, U2DP0 foot, U2DM0 foot；The 6th foot, the 7th foot, the 9th foot, the 10th foot of first filter E1 is corresponding
Connect DN foot, DP foot, SSRXN foot, the SSRXP foot of the first USB input and output port CON1；The 1st foot of second filter E2,
2 feet, the 4th foot, the 5th foot be correspondingly connected with the SSTXP0 foot of USB3.0 extension process chip 11, SSTXM0 foot, SSTXM1 foot,
SSTXP1 foot；The 6th foot, the 7th foot, the 9th foot, the 10th foot of second filter E2 is correspondingly connected with the first USB input and output port
SSTXP2 foot, SSTXN2 foot, SSTXN foot, the SSTXP foot of CON1；The 1st foot, the 2nd foot, the 4th foot, the 5th foot of third filter E3
It is correspondingly connected with SSRXM1 foot, SSRXP1 foot, U2DP1 foot, the U2DM1 foot of USB3.0 extension process chip 11；Third filter E3
The 6th foot, the 7th foot, the 9th foot, the 10th foot be correspondingly connected with the DN2 foot of the first USB input and output port CON1, DP2 foot, SSRXP2
Foot, SSRXN2 foot；The 1st foot, the 2nd foot, the 4th foot, the 5th foot of 4th filter E4 is correspondingly connected with USB3.0 extension process chip 11
SSRXP2 foot, SSRXM2 foot, U2DP2 foot, U2DM2 foot；The 6th foot, the 7th foot, the 9th foot, the 10th foot pair of 4th filter E4
DN foot, DP foot, SSRXN foot, the SSRXP foot of the second USB input and output port CON2 should be connected；The 1st foot of 5th filter E5,
2nd foot, the 4th foot, the 5th foot be correspondingly connected with the U2DP3 foot of USB3.0 extension process chip 11, U2DM3 foot, SSTXP2 foot,
SSTXM2 foot；The 6th foot, the 7th foot, the 9th foot, the 10th foot of 5th filter E5 is correspondingly connected with the second USB input and output port
SSTXN foot, SSTXP foot, DN2 foot, the DP2 foot of CON2；The 1st foot, the 2nd foot, the 4th foot, the 5th foot of 6th filter E6 is corresponding to be connected
Connect SSTXP3 foot, SSTXM3 foot, SSTXP3 foot, the SSTXM3 foot of USB3.0 extension process chip 11；The 6th of 6th filter E6
Foot, the 7th foot, the 9th foot, the 10th foot be correspondingly connected with the SSRXN2 foot of the second USB input and output port CON2, SSRXP2P foot,
SSTXN2 foot, SSTXP2 foot.
For the USB3.0 extension process chip 11 using the farsighted FL1100IC for thinking electronics in the U.S., main function is by English
The big PCIEX2 data-interface signal up to the output of (NVIDIA Jetson) module is inside IC through data transmit-receive, bus node control
It makes, the software algorithm processing inside data/address bus cooperates together with peripheral supplementary module 20, extension 4 road USB3.0 data of output
Signal.The tall and handsome PCIE signal up to (NVIDIA Jetson) module from mainly from PERST# foot, PCIECKP foot, PCIECKM foot,
PCIERXP foot, PCIERXM foot, PCIETXP foot, PCIETXM foot input USB3.0 extension process chip 11 inside, inside into
The algorithm process of row software, from U2DP0~U2DP03 foot of USB3.0 extension process chip 11, U2DM0~U2DM3 foot,
SSTXP0~SSTXP3 foot, SSTXM0~SSTXM3 foot, SSRXP0~SSRXP3 foot, SSRXM0~SSRXM3 foot export USB3.0
Data-signal.The inside of USB3.0 extension process chip 11 one share four groups as USB3.0 data-signal, such as B2 foot, A4
Foot, B4 foot, B5 foot, A7 foot, A8 foot, B8 foot, A10 foot are the data output signal foot (corresponding 0L) of the 1st group of USB3.0, other letters
In number, the 2nd group of USB3.0 data-signal is combined into the signal group that 1L ends up, the 3rd group of USB3.0 is combined into the signal group that 2L ends up
Data-signal is combined into the 4th group of USB3.0 data-signal with the signal group that 3L ends up.Every group of output signal is carried out through E1~E6 respectively
After ESD protection and EMI filtering, USB3.0 data-signal is sent in USB input and output port (CON1, CON2).R17 and C13
Play decoupling and filtering.A30 foot, A32 foot and the B26 foot of USB3.0 extension process chip 11 respectively correspond the number for I2C
According to clock signal and interrupt signal are mainly used for being communicated in real time with the 15th, 16,17 foot of U2 in outer CPU and Fig. 4.
SSTXP0 foot~SSTXP3 foot, the SSTXM0 foot~SSTXM3 foot of the USB3.0 extension process chip 11 can also divide
The corresponding pin on the capacitance connection filter of a 0.1uF Dui Ying not passed through.By these capacitors come to data received and dispatched every
From with it is anti-interference.
In the specific implementation, the CON1 in Fig. 6 and CON2 is double-deck port USB3.0, can access 4 tunnels simultaneously
USB3.0 exterior terminal equipment, the rate that every road exterior terminal equipment maximum can be transmitted are 5.0Gbps (500MB/s), this 4 outer
The access of portion's terminal interface while backward compatible USB2.0 terminal device.
Based on above-mentioned multichannel USB connection equipment, the present invention also provides a kind of data controlling parties of multichannel USB connection equipment
Method, referring to Fig. 7, the data control method includes:
S10, supply voltage and peripheral voltage are converted input voltage by peripheral supplementary module to control module power supply；
S20, peripheral supplementary module carry out the configuration of USB communications protocol to control module according to the USB peripheral currently connected；
S30, USB3.0 data-signal is exported after being grouped interaction by the data that control module transmits platform, in real time
It is exported after distribution by the corresponding port USB3.0.
In conclusion multichannel USB connection equipment provided by the invention and its data control method, due to the transmission of USB3.0
All quickly, it is per second that theoretical maximum transmission rate is up to 5G, therefore USB3.0 equipment can solve for rate and response speed
The slow problem of USB2.0 transmission speed；External 4 road USB3.0 equipment and high-speed transfer can be carried out to image and data simultaneously, can answered
Used in crusing robot, the unmanned super brush face payment of quotient, the artificial intelligence fields such as industrial automatic control；Outside than traditional USB2.0
Portion's device hardware interface is more abundant, and transmission speed is fast, high-efficient, will not generate delay, and data transmission is stable and not easy to lose.
It, can according to the technique and scheme of the present invention and its hair it is understood that for those of ordinary skills
Bright design is subject to equivalent substitution or change, and all these changes or replacement all should belong to the guarantor of appended claims of the invention
Protect range.
Claims (10)
1. a kind of multichannel USB connection equipment, external platform is provided with CPU on the platform and tall and handsome up to module, the multichannel
USB connection equipment includes a shell, a circuit board is arranged in the shell, which is characterized in that control is integrated on the circuit board
Molding block, peripheral supplementary module and several ports USB3.0；Control module connects peripheral supplementary module and several USB3.0
Port；
The periphery supplementary module converts input voltage into supply voltage and peripheral voltage and powers to control module, periphery auxiliary
Module carries out the configuration of USB communications protocol, the number that control module transmits platform to control module according to the USB peripheral currently connected
USB3.0 data-signal is exported according to being grouped after interaction, is exported after distribution by the corresponding port USB3.0 in real time.
2. multichannel USB connection equipment according to claim 1, which is characterized in that the periphery supplementary module includes power supply
Control and protection circuit, electric power management circuit, management agreement control circuit, data register circuit and phase-locked loop control circuit；Institute
State power supply control and protection circuit connection electric power management circuit and management agreement control circuit, management agreement control circuit connection number
According to register circuit and phase-locked loop control circuit；
Input voltage is exported and is powered by the power supply control and protection circuit, and converts input voltage into supply voltage to supply
Electricity；Supply voltage is converted to several preset peripheral voltages according to the I2C signal of input and gone forward side by side by the electric power management circuit
Power supply is exported after row pressure stabilizing；Management agreement control circuit according to the USB peripheral that currently connects configure corresponding protocol of USB standard with
Connection of shaking hands is established between system；Data register circuit stores protocol data when communicating for USB, and phase-locked loop control circuit is used for
Clock signal needed for generating management agreement control circuit.
3. multichannel USB connection equipment according to claim 2, which is characterized in that the control module includes that USB3.0 expands
Exhibition processing chip and filtering port circuit；The USB3.0 extension process chip connection filtering port circuit, filters port circuit
Connect electric power management circuit；
The USB3.0 extension process chip exports after carrying out bus node control, grouping interactive controlling to the data that platform transmits
USB3.0 data-signal, filtering port circuit is to defeated from the corresponding port USB3.0 after the progress EMI filtering of USB3.0 data-signal
Out.
4. multichannel USB connection equipment according to claim 3, which is characterized in that the power supply control and protection circuit packet
Include first interface, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th
Metal-oxide-semiconductor, the first triode, first resistor, second resistance, 3rd resistor, the 4th resistance, the 5th resistance, the 6th resistance, the 7th electricity
Resistance, the 8th resistance, the 9th resistance, the tenth resistance, first capacitor, the second capacitor and third capacitor；
The DC foot of the first interface connects drain electrode, Input voltage terminal, one end of first resistor and the 3rd resistor of the first metal-oxide-semiconductor
One end；One end of the other end connection second resistance of first resistor and the 2nd foot of third metal-oxide-semiconductor, the 6th foot of third metal-oxide-semiconductor
CPU is connected, the 1st foot of third metal-oxide-semiconductor and the other end of second resistance are grounded；The other end of 3rd resistor connects the 4th resistance
One end, the base stage of the first triode and the 3rd foot of third metal-oxide-semiconductor；The emitter of the other end of 4th resistance, the first triode
It is grounded with the 4th foot of third metal-oxide-semiconductor；5th foot of third metal-oxide-semiconductor connects CPU；The collector connection second of first triode
The grid of metal-oxide-semiconductor, one end of first capacitor, one end of the 5th resistance and the grid of the first metal-oxide-semiconductor；The source electrode of first metal-oxide-semiconductor connects
Connect the source electrode of the other end of the 5th resistance, the other end of first capacitor and the second metal-oxide-semiconductor；The drain electrode connection the 4th of second metal-oxide-semiconductor
The source electrode of metal-oxide-semiconductor, one end of third capacitor, the 9th resistance one end and modulation voltage end；The grid of 4th metal-oxide-semiconductor connects third
One end of the other end of capacitor, the other end of the 9th resistance and the tenth resistance；The one of drain electrode the second capacitor of connection of 4th metal-oxide-semiconductor
End, the drain electrode of the 6th metal-oxide-semiconductor and power voltage terminal；The other end of second capacitor by the 8th resistance eutral grounding, the second capacitor it is another
One end also passes through the 7th resistance and connects one end of the 6th resistance and the grid of the 5th metal-oxide-semiconductor, and the drain electrode of the 5th metal-oxide-semiconductor connects CPU,
The grid of 6th metal-oxide-semiconductor connects drain electrode and the other end of the tenth resistance of the 7th metal-oxide-semiconductor, and the grid of the 7th metal-oxide-semiconductor connects CPU；
The source electrode of 5th metal-oxide-semiconductor, source electrode, the source electrode of the 7th metal-oxide-semiconductor, the other end of the 6th resistance of the 6th metal-oxide-semiconductor are grounded.
5. multichannel USB connection equipment according to claim 4, which is characterized in that the electric power management circuit includes power supply
Managing chip, the first inductance, the 8th metal-oxide-semiconductor, the 9th metal-oxide-semiconductor, the tenth metal-oxide-semiconductor, the 11st metal-oxide-semiconductor, the 12nd metal-oxide-semiconductor, the tenth
One resistance, twelfth resistor, thirteenth resistor, the 14th resistance, the 15th resistance, the 16th resistance, the 4th capacitor, the 5th electricity
Appearance, the 6th capacitor, the 7th capacitor, the 8th capacitor, the 9th capacitor and the tenth capacitor；
9th foot of the power management chip and the 10th foot are all connected with CPU, and the 6th foot of power management chip and the 4th foot are all connected with
Power voltage terminal, the 5th foot of power management chip connect the 1st drain electrode of the 8th metal-oxide-semiconductor, and the 32nd foot of power management chip passes through
14th resistance connects one end of the 7th capacitor；1st foot of power management chip connects the 1st grid of the 8th metal-oxide-semiconductor；Power supply pipe
The 31st foot for managing chip connects the one of the other end of the 7th capacitor, the 1st source electrode of the 8th metal-oxide-semiconductor, the 2nd drain electrode and the first inductance
End；2nd source electrode of the 8th metal-oxide-semiconductor is grounded, and the 2nd foot of power management chip connects the 2nd grid of the 8th metal-oxide-semiconductor, power management
21st foot of chip connects one end of twelfth resistor, one end of the 4th capacitor, one end of eleventh resistor and the 6th capacitor
One end；Power management chip the 20th foot connection one end of thirteenth resistor, the other end of the 4th capacitor, eleventh resistor it is another
One end of one end and the 5th capacitor；25th foot of power management chip connects one end of the 8th capacitor, electricity by the 15th resistance
24th foot of source control chip connects the 1st grid of the 9th metal-oxide-semiconductor；26th foot of power management chip connects the another of the 8th capacitor
One end, the 1st source electrode of the 9th metal-oxide-semiconductor, the 2nd drain electrode and the first inductance the other end；The 23rd foot connection the of power management chip
2nd grid of nine metal-oxide-semiconductors, the 2nd source electrode ground connection of the 9th metal-oxide-semiconductor；One end of 1st drain electrode the tenth capacitor of connection of the 9th metal-oxide-semiconductor,
The other end of twelfth resistor, the other end of thirteenth resistor and 5V power end；One end of tenth capacitor connects the 16th resistance
One end and the tenth metal-oxide-semiconductor source electrode；The other end of 16th resistance connects the grid of the grid of the tenth metal-oxide-semiconductor, the 11st metal-oxide-semiconductor
The drain electrode of pole and the 12nd metal-oxide-semiconductor；The drain electrode connection drain electrode of the 11st metal-oxide-semiconductor of tenth metal-oxide-semiconductor, one end of the 9th capacitor and the
One peripheral voltage end；The grid of 12nd metal-oxide-semiconductor connects CPU；The source electrode of 11st metal-oxide-semiconductor, the source electrode of the 12nd metal-oxide-semiconductor and
The other end of nine capacitors is grounded.
6. multichannel USB connection equipment according to claim 5, which is characterized in that the management agreement control circuit includes
Control chip, the first clock chip, the 11st capacitor and the 12nd capacitor；
The 15th foot to the 17th foot of the control chip is all connected with the USB3.0 extension process chip in control module, controls chip
The 38th foot connect the 12nd capacitor one end and the first clock chip HOT2 foot, control chip the 39th foot connection the 11st
The HOT foot of the one end capacitor C11 and the first clock chip, the other end ground connection of the 12nd capacitor, the GND foot of the first clock chip connect
Connect the other end and ground of the 11st capacitor.
7. multichannel USB connection equipment according to claim 6, which is characterized in that the USB3.0 extension process chip
Peripheral circuit includes the 17th resistance, the 13rd capacitor, the 14th capacitor, the 15th capacitor and second clock chip；
PERST# foot, PCIECKP foot, PCIECKM foot, PCIERXP foot, the PCIERXM foot of the USB3.0 extension process chip
It is all connected with tall and handsome up to module；The PCIEREXT foot of USB3.0 extension process chip connects one end of the 17th resistance, and USB3.0 expands
The PCIECAP foot of exhibition processing chip connects one end of the 13rd capacitor, and the other end of the 17th resistance connects the 13rd capacitor
The other end and ground；U2DP0 foot~U2DP3 foot of USB3.0 extension process chip, U2DM0 foot~U2DM3 foot, SSTXP0 foot~
SSTXP3 foot, SSTXM0 foot~SSTXM3 foot, SSRXP0 foot~SSRXP3 foot, SSRXM0 foot~SSRXM3 foot are all connected with filtering end
Mouth circuit；The HOT foot of the XSCO foot connection second clock chip of USB3.0 extension process chip and one end of the 15th capacitor,
The HOT2 foot of the XSCI foot connection second clock chip of USB3.0 extension process chip and one end of the 14th capacitor；15th electricity
The other end of appearance connects the GND foot and ground of the other end of the 14th capacitor, second clock chip；USB3.0 extension process chip
ROMSDA foot, ROMSCL foot and ROMPRES foot are correspondingly connected with the 16th foot, the 17th foot, the 15th foot of control chip.
8. multichannel USB connection equipment according to claim 5, which is characterized in that the filtering port circuit includes first
Filter, second filter, third filter, the 4th filter, the 5th filter, the 6th filter, the first USB input and output
Port and the second USB input and output port；
The 1st foot, the 2nd foot, the 4th foot, the 5th foot of the first filter are correspondingly connected with the SSRXP0 of USB3.0 extension process chip
Foot, SSRXM0 foot, U2DP0 foot, U2DM0 foot；The 6th foot, the 7th foot, the 9th foot, the 10th foot of first filter are correspondingly connected with first
DN foot, DP foot, SSRXN foot, the SSRXP foot of USB input and output port；The 1st foot, the 2nd foot, the 4th foot, the 5th of second filter
Foot is correspondingly connected with SSTXP0 foot, SSTXM0 foot, SSTXM1 foot, the SSTXP1 foot of USB3.0 extension process chip；Second filter
The 6th foot, the 7th foot, the 9th foot, the 10th foot be correspondingly connected with the SSTXP2 foot of the first USB input and output port, SSTXN2 foot,
SSTXN foot, SSTXP foot；The 1st foot, the 2nd foot, the 4th foot, the 5th foot of third filter are correspondingly connected with USB3.0 extension process chip
SSRXM1 foot, SSRXP1 foot, U2DP1 foot, U2DM1 foot；The 6th foot, the 7th foot, the 9th foot, the 10th foot of third filter are corresponding
Connect DN2 foot, DP2 foot, SSRXP2 foot, the SSRXN2 foot of the first USB input and output port；1st foot of the 4th filter, the 2nd
Foot, the 4th foot, the 5th foot are correspondingly connected with SSRXP2 foot, SSRXM2 foot, U2DP2 foot, the U2DM2 foot of USB3.0 extension process chip；
The 6th foot, the 7th foot, the 9th foot, the 10th foot of 4th filter be correspondingly connected with the DN foot of the second USB input and output port, DP foot,
SSRXN foot, SSRXP foot；The 1st foot, the 2nd foot, the 4th foot, the 5th foot of 5th filter are correspondingly connected with USB3.0 extension process chip
U2DP3 foot, U2DM3 foot, SSTXP2 foot, SSTXM2 foot；The 6th foot, the 7th foot, the 9th foot, the 10th foot of 5th filter are corresponding
Connect SSTXN foot, SSTXP foot, DN2 foot, the DP2 foot of the second USB input and output port；1st foot of the 6th filter, the 2nd foot,
4th foot, the 5th foot are correspondingly connected with SSTXP3 foot, SSTXM3 foot, SSTXP3 foot, the SSTXM3 foot of USB3.0 extension process chip；The
The 6th foot, the 7th foot, the 9th foot, the 10th foot of six filters be correspondingly connected with the second USB input and output port SSRXN2 foot,
SSRXP2P foot, SSTXN2 foot, SSTXP2 foot.
9. multichannel USB connection equipment according to claim 8, which is characterized in that the model of the power management chip
NCP81239 controls the model FL1100 of model CYPD4226-40LQXIT, USB3.0 the extension process chip of chip.
10. a kind of data control method using multichannel USB connection equipment described in claim 1 characterized by comprising
Step A, supply voltage and peripheral voltage is converted input voltage by peripheral supplementary module to power to control module；
Step B, peripheral supplementary module carries out the configuration of USB communications protocol to control module according to the USB peripheral currently connected；
Step C, it is grouped after interaction by the data that control module transmits platform and exports USB3.0 data-signal, divided in real time
It is exported after matching by the corresponding port USB3.0.
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| CN111930083A (en) * | 2020-08-05 | 2020-11-13 | 浙江智昌机器人科技有限公司 | Method and device for collecting industrial equipment data |
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| CN111930083A (en) * | 2020-08-05 | 2020-11-13 | 浙江智昌机器人科技有限公司 | Method and device for collecting industrial equipment data |
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