CN215072470U

CN215072470U - Digital program controlled exchanger with multi-interface access

Info

Publication number: CN215072470U
Application number: CN202121353238.4U
Authority: CN
Inventors: 陈宣林; 余清华; 吴益伟; 郑晓; 凌秋立; 郑文强
Original assignee: Zhejiang Hengjie Communication Technology Co ltd
Current assignee: Zhejiang Hengjie Communication Technology Co ltd
Priority date: 2021-06-17
Filing date: 2021-06-17
Publication date: 2021-12-07
Anticipated expiration: 2031-06-17

Abstract

The utility model discloses a digital stored program control switch of many interfaces access, it is including main control unit, signal acquisition unit, signal processing unit and ethernet unit. The main control unit is respectively connected to the Ethernet unit and the signal processing unit and is used for exchanging signals between the Ethernet unit and the signal processing unit. The signal acquisition unit is connected to the signal processing unit for the signal transmission who will gather handles for signal processing unit. The signal acquisition unit comprises a plurality of signal acquisition temporary storage devices and dial switch groups which are correspondingly connected with the signal acquisition temporary storage devices one by one, and each signal acquisition temporary storage device is sequentially connected to the signal processing unit. Digital signals are input through the signal processing unit, the main control unit transmits the digital signals to the Ethernet unit to be converted into optical signals and then carries out remote transmission, the signal acquisition unit is used for acquiring multi-channel digital signals, the signal acquisition temporary storage is used for temporarily storing the acquired digital signals, and the on-off is controlled by the dial switch group connected with the signal acquisition temporary storage.

Description

Digital program controlled exchanger with multi-interface access

Technical Field

The utility model relates to a switch, more specifically say, it relates to a digital stored program control switch that many interfaces insert.

Background

The digital program controlled switch is widely applied to occasions such as hotels, enterprises and the like needing to pay attention to enterprise images, needs to play company messages by voice and needs to provide broadcast-level voice, so that the enterprise images are improved, and the purposes of broadcast-level broadcasting and quick connection of user ports are achieved. The call connection part uses the digital exchange network in the exchanger to realize digital exchange by PCM mode, and the control part is realized by computer through software. The existing digital program control exchanger has the problems that the number of external ports is limited, and each port cannot be independently controlled.

SUMMERY OF THE UTILITY MODEL

Aiming at the defects in the prior art, on one hand, the digital program controlled switch with the multi-interface access is provided, and each port of the digital program controlled switch with the multi-interface access can be independently controlled.

In order to achieve the above object, on one hand, the following technical solutions are provided:

a multi-interface access digital program control exchanger comprises a main control unit, a signal acquisition unit, a signal processing unit and an Ethernet unit.

The main control unit is respectively connected to the Ethernet unit and the signal processing unit and is used for exchanging signals between the Ethernet unit and the signal processing unit.

The signal acquisition unit is connected to the signal processing unit for the signal transmission who will gather handles for signal processing unit.

The signal acquisition unit comprises a plurality of signal acquisition temporary storage devices and dial switch groups which are correspondingly connected with the signal acquisition temporary storage devices one by one, and each signal acquisition temporary storage device is sequentially connected to the signal processing unit.

To sum up, the following beneficial effects are achieved in the technical scheme: digital signals are input through the signal processing unit, the main control unit transmits the digital signals to the Ethernet unit to be converted into optical signals and then carries out remote transmission, the signal acquisition unit is used for acquiring multi-channel digital signals, the signal acquisition temporary storage is used for temporarily storing the acquired digital signals, and the on-off is controlled by the dial switch group connected with the signal acquisition temporary storage.

Drawings

Fig. 1 is a schematic block diagram of a multi-interface access digital SPC exchange;

fig. 2 is a schematic circuit diagram of a signal acquisition unit of a multi-interface access digital SPC exchange;

FIG. 3 is a schematic circuit diagram of a phase-locking unit of a multi-interface accessed digital SPC exchange;

fig. 4 is a schematic diagram of an external housing of a multi-interface access digital SPC exchange.

Reference numerals: 10. a main control unit; 20. a signal acquisition unit; 21. a signal acquisition temporary storage; 22. a dial switch group; 23. a version acquisition temporary memory; 30. a signal processing unit; 31. a digital signal processor; 32. a logic signal processing circuit; 40. an Ethernet unit; 41. an Ethernet switch chip; 42. an Ethernet PHY interface chip; 43. a memory card; 44. an RS232 interface; 50. a phase lock unit; 60. an outer housing.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. In which like parts are designated by like reference numerals. It should be noted that the terms "front," "back," "left," "right," "upper" and "lower" used in the following description refer to directions in the drawings, and the terms "bottom" and "top," "inner" and "outer" refer to directions toward and away from, respectively, the geometric center of a particular component.

As shown in fig. 1, a multi-interface accessed digital program controlled switch includes a main control unit 10, a signal acquisition unit 20, a signal processing unit 30 and an ethernet unit 40; the main control unit 10 is respectively connected to the ethernet unit 40 and the signal processing unit 30, and is configured to exchange signals between the ethernet unit 40 and the signal processing unit 30; the signal acquisition unit 20 is connected to the signal processing unit 30, and is used for transmitting the acquired signals to the signal processing unit 30 for processing; the signal acquisition unit 20 includes a plurality of signal acquisition temporary storage devices 21 and dial switch sets 22 correspondingly connected with the signal acquisition temporary storage devices one by one, and each signal acquisition temporary storage device 21 is sequentially connected to the signal processing unit 30. Digital signals are input through the signal processing unit 30, the main control unit 10 transmits the digital signals to the Ethernet unit 40 to be converted into optical signals, and then the optical signals are transmitted in a long distance, the signal acquisition unit 20 is used for acquiring multi-path digital signals, the signal acquisition temporary storage 21 is used for temporarily storing the acquired digital signals, and the on-off of the signal acquisition temporary storage is controlled by the dial switch group 22 connected with the signal acquisition temporary storage.

As shown in fig. 2, the pin Q8 of the first signal acquisition register 21 in the signal acquisition registers 21 is connected to the signal processing unit 30, the pin Q8 of each of the other signal acquisition registers 21 is sequentially connected to the pin DS of the next adjacent signal acquisition register 21, the pin +3.3V of the signal acquisition register 21 is connected to the VCC power supply terminal, the pin DS is connected to the VCC power supply terminal through a resistor R231, the pin GND is grounded, the pin P1, the pin P2, the pin P3, the pin P4, the pin P5, the pin P6, the pin P7, and the pin P8 are connected to the eighth, seventh, sixth, fifth, fourth, third, tenth, and first terminals of the dial switch respectively, and are connected to the VCC power supply terminal through a power supply load resistor, and the ninth, tenth, thirteenth, tenth, and twelfth terminals of the dial switch, and eleventh terminals of the dial switch respectively, The fifteenth terminal and the sixteenth terminal are connected to the ground through a grounded load resistor.

The signal acquisition unit 20 further includes a version acquisition temporary memory 23, a pin Q8 of a first signal acquirer in the signal acquisition temporary memory 21 is connected to a pin DS of the version acquisition temporary memory 23, the pin DS of the version acquisition temporary memory 23 is further connected to a VCC power supply terminal through a resistor R164, a pin P1, a pin P2, a pin P3 and a pin P4 are respectively grounded, a pin P6 and a pin P7 are respectively connected to the VCC power supply terminal through a resistor R194 and a resistor R193, and a pin Q7 is connected to the signal processing unit 30. The signal acquisition temporary memory 21 is integrated on an acquisition circuit board, and the version acquisition temporary memory 23 is used for acquiring version signals of the circuit board.

The signal processing unit 30 includes a digital signal processor 31 and a logic signal processing circuit 32; the digital signal processor 31 is respectively connected to the signal acquisition unit 20 and the logic signal processing circuit 32, and the logic signal processing circuit 32 is connected to the main control unit 10 and is configured to transmit the logically processed signal to the main control unit 10.

The digital signal processor 31 is provided in plurality and connected to the logic signal processing circuits 32, respectively. The logic signal processing circuit 32 can process the digital signal input from the digital signal processor 31 quickly by editing in advance the basic logic structure of the flow of the signal processing algorithm.

The ethernet unit 40 includes an ethernet switch chip 41, an ethernet PHY interface chip 42, a memory card 43, and an RS232 interface 44; the ethernet switch chip 41 is connected to the main control unit 10 and the ethernet PHY interface chip 42, respectively, and the ethernet PHY interface chip 42 is connected to the memory card 43 and the RS232 interface 44, respectively.

A phase locking unit 50 connected to the main control unit 10 is further included, and the frequency and phase of the internal oscillation signal of the main control unit 10 are controlled by an externally input reference signal.

As shown in fig. 3, the phase-locked unit 50 includes a driving chip U23 and a phase-locked loop chip U24, a pin a0 and a pin a1 of the driving chip U23 are respectively used for accessing an externally input reference signal, a VCC pin of the driving chip U23 is connected to a VCC power supply terminal, a VCC pin of the driving chip U23 is further grounded through a capacitor C60, a GND pin of the driving chip U23 is grounded, a pin B0 and a pin B1 of the driving chip U23 are respectively connected to an AIN pin and a BIN pin of the phase-locked loop chip U24, and a pin B0 of the driving chip U23 is further connected to the VCC power supply terminal through a resistor R98; the VCIN pin of the phase-locked loop chip U24 is connected to the first end of the resistor R99, the INH pin of the phase-locked loop chip U24 is grounded, the CA pin of the phase-locked loop chip U24 is connected to one end of the capacitor C87 and one end of the capacitor C59 respectively, the CB pin of the phase-locked loop chip U24 is connected to the other end of the capacitor C87 and the other end of the capacitor C59 respectively, one end of the capacitor C87 and one end of the capacitor C59, the R1 pin and the R2 pin are grounded through the resistor R104 and the resistor R106 respectively, the PCP pin, the PC1 pin, the PC2 pin and the PC3 pin of the phase-locked loop chip U24 are connected to the resistor R100 and the resistor R101 respectively, the VCOUT pin of the phase-locked loop chip U24 is connected to the main control unit 10 through a resistor R103, second ends of the resistor R99, the resistor R100, the resistor R101, the resistor R102 and the resistor R107 are connected to one end of a resistor R108, the other end of the resistor R108 is connected to one end of a capacitor C61, and the other end of the capacitor C61 is grounded. The phase-locked loop chip U24 controls the frequency and phase of the internal oscillation signal of the loop by using the externally input reference signal, and realizes the automatic tracking of the frequency of the input signal by the frequency of the output signal.

As shown in fig. 4, the main control unit 10, the signal acquisition unit 20, the signal processing unit 30, the ethernet unit 40, and the phase locking unit 50 are respectively disposed in the external housing 60, a power supply unit respectively connected to the main control unit 10, the signal acquisition unit 20, the signal processing unit 30, the ethernet unit 40, and the phase locking unit 50 is further disposed in the external housing 60, the external device adopts a modular redundancy design, and both the main control unit 10 and the power supply unit have a hot backup function. The multi-interface access digital program control exchange can provide a plurality of E1 interfaces, and can provide multi-path extension and loop relay mixed insertion. The device has strong calling processing and accounting, centralized network management and other capabilities, and the main control unit 10 adopts redundancy backup to ensure smooth communication time. The system supports interfaces of China NO.1, R2, NO.7, PRI signaling, SIP, loop relay, magnet and the like, and supports a tandem function. The interface outside the outer shell 60 is visual, and the operation is visual, simple and convenient by adopting a WINDOWS graphical interface. The main control unit 10, the signal acquisition unit 20, the signal processing unit 30, the ethernet unit 40 and the phase locking unit 50 in the interior adopt a modular structural design, the capacity of the whole machine can be flexibly configured according to the requirements of customers, the acquisition circuit board can be expanded to be used for installing more signal acquisition temporary storage devices 21, the accessed E1 interface can be expanded at will, and the number of doors can be expanded to any door. The one-machine double-number function is supported, and a perfect solution is provided for access of multiple operators. And the three-stage lightning protection device is adopted, so that the normal work of the equipment in a severe environment can be effectively ensured.

Above only the utility model discloses an it is preferred embodiment, the utility model discloses a scope of protection not only limits in above-mentioned embodiment, and the all belongs to the utility model discloses a technical scheme under the thinking all belongs to the utility model discloses a scope of protection. It should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A multi-interface access digital stored program control exchanger is characterized in that the exchanger comprises a main control unit (10), a signal acquisition unit (20), a signal processing unit (30) and an Ethernet unit (40);

the main control unit (10) is respectively connected to the Ethernet unit (40) and the signal processing unit (30) and is used for exchanging signals between the Ethernet unit (40) and the signal processing unit (30);

the signal acquisition unit (20) is connected to the signal processing unit (30) and is used for transmitting acquired signals to the signal processing unit (30) for processing;

the signal acquisition unit (20) comprises a plurality of signal acquisition temporary storage devices (21) and dial switch groups (22) which are correspondingly connected with the signal acquisition temporary storage devices one by one, and each signal acquisition temporary storage device (21) is sequentially connected to the signal processing unit (30).

2. The multi-interface accessed digital program controlled switch according to claim 1, wherein the pin Q8 of the first signal acquisition temporary memory (21) in the signal acquisition temporary memory (21) is connected to the signal processing unit (30), the pin Q8 of each of the other signal acquisition temporary memories (21) is connected to the pin DS of the next adjacent signal acquisition temporary memory (21), the pin +3.3V of the signal acquisition temporary memory (21) is connected to the VCC power supply terminal, the pin DS is connected to the VCC power supply terminal through a resistor R231, the pin GND is grounded, the pin P1, the pin P2, the pin P3, the pin P4, the pin P5, the pin P6, the pin P7 and the pin P8 are connected to the eighth, the seventh, the sixth, the fifth, the fourth, the third, the second and the first terminals of the code dialing switch corresponding thereto, and are further connected to the VCC power supply load resistor, and the ninth end, the tenth end, the twelfth end, the thirteenth end, the fourteenth end, the fifteenth end and the sixteenth end of the dial switch are respectively connected to the ground through a grounding load resistor.

3. The multi-interface access digital SPC switch according to claim 1, wherein said signal acquisition unit (20) further comprises a version acquisition register (23), the pin Q8 of the first signal collector in said signal acquisition register (21) is connected to the pin DS of the version acquisition register (23), the pin DS of the version acquisition register (23) is further connected to VCC power supply through a resistor R164, the pin P1, the pin P2, the pin P3 and the pin P4 are respectively grounded, the pin P6 and the pin P7 are respectively connected to VCC power supply through a resistor R194 and a resistor R193, and the pin Q7 is connected to the signal processing unit (30).

4. A multi-interface accessed digital SPC exchange according to claim 1, characterized in that, the signal processing unit (30) comprises a digital signal processor (31) and a logic signal processing circuit (32);

the digital signal processor (31) is respectively connected to the signal acquisition unit (20) and the logic signal processing circuit (32), and the logic signal processing circuit (32) is connected to the main control unit (10) and is used for transmitting the signals subjected to logic processing to the main control unit (10).

5. A multi-interface accessed digital SPC exchange according to claim 4, characterized in that, the digital signal processor (31) is provided with a plurality and is respectively connected to the logic signal processing circuit (32).

6. A multi-interface accessed digital SPC exchange according to claim 1, characterized in that, the Ethernet unit (40) comprises an Ethernet switch chip (41), an Ethernet PHY interface chip (42), a memory card (43) and an RS232 interface (44);

the Ethernet switch chip (41) is respectively connected to the main control unit (10) and the Ethernet PHY interface chip (42), and the Ethernet PHY interface chip (42) is respectively connected to the memory card (43) and the RS232 interface (44).

7. The digital SPC exchange with multiple interfaces as claimed in claim 1, further comprising a phase locking unit (50) connected to the master control unit (10), wherein the frequency and phase of the internal oscillation signal of the master control unit (10) are controlled by an externally inputted reference signal.

8. The multi-interface accessed digital program controlled switch according to claim 7, wherein the phase-locked unit (50) comprises a driving chip U23 and a phase-locked loop chip U24, the A0 pin and the A1 pin of the driving chip U23 are respectively used for accessing an externally input reference signal, the VCC pin of the driving chip U23 is connected to a VCC power supply terminal, the VCC pin of the driving chip U23 is further connected to ground through a capacitor C60, the GND pin of the driving chip U23 is connected to ground, the B0 pin and the B1 pin of the driving chip U23 are respectively connected to the AIN pin and the BIN pin of the phase-locked loop chip U24, and the B0 pin of the driving chip U23 is further connected to the VCC power supply terminal through a resistor R98;

a VCIN pin of a phase-locked loop chip U24 is connected to a first end of a resistor R99, an INH pin of the phase-locked loop chip U24 is grounded, a CA pin of the phase-locked loop chip U24 is connected to one end of a capacitor C87 and one end of a capacitor C59, a CB pin of the phase-locked loop chip U24 is connected to the other end of a capacitor C87 and the other end of a capacitor C59, one end of a capacitor C87 and one end R1 and R2 pins of a capacitor C59 are grounded through a resistor R104 and a resistor R106, respectively, a PCP pin, a PC1 pin, a PC2 pin and a PC3 pin of the phase-locked loop chip U24 are connected to first ends of a resistor R100, a resistor R101, a resistor R102 and a resistor R107, a VCOUT pin of the phase-locked loop chip U42 is connected to a main control unit (10) through a resistor R103, second ends of the resistor R99, the resistor R100, the resistor R101, the second end of the resistor R102 and the second end of the capacitor R3529 are connected to one end of a resistor R108, the other terminal of the capacitor C61 is connected to ground.