CN107562970B

CN107562970B - Mixed signal circuit system simulation method and electronic device

Info

Publication number: CN107562970B
Application number: CN201610510277.8A
Authority: CN
Inventors: 陈英杰; 余美俪; 王鼎雄; 罗幼岚; 高淑怡
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2016-06-30
Filing date: 2016-06-30
Publication date: 2021-07-13
Anticipated expiration: 2036-06-30
Also published as: CN107562970A

Abstract

The invention discloses a mixed signal circuit system simulation method and an electronic device, wherein the method comprises the steps of detecting the positions of a plurality of temporary registers and a clock signal in a circuit system, wherein the circuit system is a mixed signal circuit system; performing a timing analysis conversion operation on a circuit block coupled between any two of the registers to obtain a converted circuit system; and performing a static timing analysis operation on the converted circuit system; when the circuit block can be converted into a combinational circuit block, the timing analysis conversion operation comprises converting the circuit block into the combinational circuit block, wherein the combinational circuit block is a logic gate level. The simulation method of the mixed signal circuit system performs time sequence analysis conversion operation on the circuit blocks among the plurality of temporary registers in the circuit system, so that the simulation result is more accurate.

Description

Mixed signal circuit system simulation method and electronic device

Technical Field

The present disclosure relates to analog methods, and particularly to a mixed signal circuit system and an electronic device using the same.

Background

Static Timing Analysis (STA) is a work flow for calculating and predicting the Timing of a digital circuit in electronic engineering, plays an important role in rapid and accurate measurement of the circuit Timing, is a main technical method in related design fields in recent decades, and a mature digital circuit Timing engine can directly perform Static Timing Analysis on a standard element of the digital circuit. However, there is no analysis tool for directly performing static timing analysis on analog circuitry (i.e., mixed signal circuitry) having digital circuit blocks such as registers or flip-flops. In the prior art, to perform timing analysis on a mixed signal circuit system, the whole circuit system is directly simulated, an input value is directly given to a register or a trigger, and whether the system has a static timing analysis violation (partitioning) is observed, however, the method takes a lot of time; or, in the prior art, a circuit path between two registers in the mixed signal circuit system is captured and subjected to simulation analysis, but the load on the other paths or other circuit effects that may cause influence cannot be considered, the electrical drift effect in the advanced process cannot be considered, and the simulation result is not accurate.

Disclosure of Invention

An objective of the present invention is to provide an analog method for mixed signal circuit system and related electronic device to solve the above problems.

According to one embodiment of the present invention, a method for simulating mixed-signal (mixed-signal) circuitry is disclosed, wherein the method comprises detecting locations of a plurality of registers included in the circuitry and a clock signal, wherein the circuitry is mixed-signal circuitry; performing a timing analysis conversion operation on a circuit block coupled between any two adjacent registers to obtain a converted circuit system; and performing a Static Timing Analysis (STA) operation on the converted circuitry; wherein when the circuit block is convertible to a combined circuit (combinatorial circuit) block, the timing analysis conversion operation comprises converting the circuit block to the combined circuit block, wherein the combined circuit block is a gate level.

According to an embodiment of the present invention, an electronic device is disclosed, wherein the electronic device comprises a processor; and a storage device storing a program code, wherein when the processor loads and executes the program code, the following operations are performed: detecting positions of a plurality of temporary registers and a clock signal contained in a circuit system, wherein the circuit system is a mixed signal circuit system; performing a timing analysis conversion operation on a circuit block coupled between any two adjacent registers to obtain a converted circuit system; and performing a Static Timing Analysis (STA) operation on the converted circuitry; wherein when the circuit block is convertible to a combined circuit (combinatorial circuit) block, the timing analysis conversion operation comprises converting the circuit block to the combined circuit block, wherein the combined circuit block is a gate level.

The simulation method of the mixed signal circuit system performs time sequence analysis conversion operation on the circuit blocks among the plurality of temporary registers in the circuit system, so that the simulation result is more accurate.

Drawings

Fig. 1 is a schematic diagram of an analog device for applying an analog method to a mixed signal circuit system according to an embodiment of the invention.

Fig. 2 is a schematic diagram of a mixed signal circuitry according to an embodiment of the invention.

FIG. 3 is a diagram of a converted circuit system obtained by applying the simulation method according to an embodiment of the present invention.

Fig. 4 is a flow diagram of a mixed signal circuitry simulation method according to an embodiment of the invention.

Fig. 5 is a schematic diagram of an electronic device according to an embodiment of the invention.

Description of reference numerals:

100 analog device

110 detection module

120 conversion module

130 analysis module

101. 200 circuit system

201-204, 301, 302, 304 circuit block

303 timing value

CK clock signal

400. 402, 406, 408, 410

500 electronic device

501 processor

502 storage device

PROG program code

Detailed Description

Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. The present specification and claims do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Furthermore, the term "coupled" is used herein to encompass any direct and indirect electrical connection, such that if a first device is coupled to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

Fig. 1 is a schematic diagram of an analog device 100 for applying an analog method to a circuit system 101 according to an embodiment of the present invention, wherein the circuit system 101 is a Mixed-signal (Mixed-signal) circuit system. As shown in fig. 1, the simulation apparatus 100 includes a detection module 110, a conversion module 120 and an analysis module 130, wherein the detection module 110 is used for detecting the positions of the registers R1 to Rn and the clock signal CK included in the mixed signal circuitry 101, and in one embodiment, the detection module 110 can search the positions of the registers R1 to Rn and the clock signal CK included in the mixed signal circuitry 101 by searching a netlist (netlist) of the mixed signal circuitry 101; the conversion module 120 is used for performing a timing analysis conversion operation on all circuit blocks coupled between any two registers (e.g., between R1 and R2 or between R1 and Rn) in the mixed signal circuit system 101 to obtain a converted circuit system; the Analysis module 130 is used to perform a Static Timing Analysis (STA) on the converted circuit system, and in one embodiment, the Analysis module 130 can directly perform the STA on the converted circuit system by using a digital circuit Timing Analysis tool.

Fig. 2 is a schematic diagram of a mixed-signal circuit system 200 according to an embodiment of the invention, and as shown in fig. 2, the mixed-signal circuit system 200 includes a clock signal CK, registers R1 and R2, and

circuit blocks

201, 202, 203 and 204. it should be noted that the mixed-signal circuit system 200 does not limit the number of registers included therein, i.e., the mixed-signal circuit system 200 may include one or more registers R1-Rn, the registers R1 and R2 in fig. 2 are merely exemplary, and the mixed-signal circuit system 200 does not limit the number of circuit blocks included therein, i.e., the mixed-signal circuit system 200 may include one or more circuit blocks, and the

circuit block

201 and 204 in fig. 2 are also merely exemplary. The circuit blocks 201-204 in the mixed signal circuit system 200 are analog circuits at a transistor level (transistor level), for example, the circuit blocks 201-204 may be an amplifier, a multiplexer, etc., and the actual circuit architecture and functions of the circuit blocks 201-204 are not a limitation of the present invention. In the mixed signal circuit system simulation method of the present invention, the detection module 110 included in the simulation apparatus 100 shown in fig. 1 detects the positions of the registers R1 and R2 and the clock signal CK in the mixed signal circuit system 200, and in practice, the detection module 110 can find the positions of the registers R1 and R2 and the clock signal CK by searching the netlist of the mixed signal circuit system 200; then, the conversion module 120 first detects whether the circuit block 201-204 coupled between the registers R1 and R2 can be directly converted into a combinational circuit (combinational circuit) of a logic gate level (gate level) and performs a timing analysis conversion operation on the circuit block 201-204, for example, the system can determine whether the circuit block has a convertible logic gate level circuit function by inputting a logic value 0 or 1 to the circuit block 201 and observing the output result of the circuit block 201, for example, according to the output result, the circuit block 201 can be converted into a buffer, an inverter, an and gate, or a gate or a load, etc., if the conversion module 120 detects that the circuit block can be converted into a combinational circuit of a logic gate level, the timing analysis conversion operation performed at this time directly converts the circuit block into a corresponding combinational circuit; if the converting module 120 detects that the circuit block cannot be converted into any combinational circuit of logic gate level, the timing analysis converting operation includes directly setting the timing value of the circuit block by a user through user input, for example, if the circuit block 203 is an amplifier, the time elapsed when a signal is input from the input terminal to the output terminal can be input by the user. In detail, if the conversion module 120 detects that only the circuit block 203 in the

circuit blocks

201 and 204 cannot be converted into the corresponding combinational circuit of the logic gate hierarchy, the conversion module 120 converts the

circuit blocks

201, 202 and 204 into the corresponding combinational circuits respectively, for example, the circuit block 201 may be converted into a buffer, the circuit block 202 may be converted into an and gate, the input of the and gate is a signal S1, the circuit block 204 may be equivalent to a load, and the timing value of the circuit block 203 is set by the user input, and a converted circuit system can be obtained after the timing analysis conversion operation is performed on all the circuit blocks. Referring to fig. 3, fig. 3 is a schematic diagram of a converted circuit system 300 obtained by applying the simulation method according to an embodiment of the invention, wherein the

circuit blocks

301, 302, 304 are the circuit blocks of the logic gate hierarchy obtained by converting the

circuit blocks

201, 202, 204, respectively, as described above, the converted circuit block 301 may be equivalent to a buffer, the circuit block 302 may be an and gate, the input of the and gate is the signal S1, and the circuit block 304 may be a load, which is only an example, however, the converted result of each circuit block is not a limitation of the invention. And the circuit block 203 is directly set 303 the timing value by the user. As shown in fig. 3, since the

circuit blocks

301, 302 and 304, the registers R1-R2 and a timing value are included in the logic gate hierarchy, the converted circuit system 300 can be regarded as a digital circuit system, and finally, the analysis module 130 can directly utilize an existing digital circuit timing analysis engine to perform static timing analysis on the converted circuit system 300.

Fig. 4 is a flowchart of a mixed signal circuitry simulation method according to an embodiment of the invention, which is briefly summarized as follows, provided that substantially the same result is achieved, and that the sequence of steps in the flowchart shown in fig. 4 is not necessarily required.

Step 400, detect the register and clock signal locations in the mixed signal circuitry.

Step 402, checking whether a circuit block coupled between any two registers is a combinational circuit capable of being converted into a logic gate hierarchy, if yes, entering step 404; otherwise step 406 is entered.

In step 404, the circuit block is converted into a corresponding combinational circuit.

In step 406, the timing value of the circuit block is set by a user input.

Step 408, a converted circuit system is obtained.

Step 410, performing static timing analysis on the converted circuit system.

It is noted that step 400 is performed by the detection module 110,

steps

402, 404, 406 are performed by the transformation module 120, and step 410 is performed by the analysis module 130. The details of the steps shown in FIG. 4 can be easily understood by those skilled in the art after reading the above paragraphs, and thus the detailed description is omitted here for brevity.

Fig. 5 is a schematic diagram of an electronic device 500 according to an embodiment of the invention, in which the electronic device 500 includes a processor 501 and a storage device 502 storing a program code PROG, and when the program code PROG is loaded into and executed by the processor 501, the processor 501 executes the steps of the flowchart shown in fig. 4, and further description is omitted for brevity since it should be easily understood by those skilled in the art after reading the above paragraphs.

The above-mentioned embodiments are merely preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.

Claims

1. A mixed signal circuitry simulation method, comprising:

detecting positions of a plurality of temporary registers and a clock signal contained in a circuit system, wherein the circuit system is a mixed signal circuit system;

performing a timing analysis conversion operation on a circuit block coupled between any two adjacent registers to obtain a converted circuit system, wherein the circuit block is an analog circuit and the circuit block is a transistor level; and

performing a static timing analysis operation on the converted circuit system;

wherein when the circuit block can be converted into a combined circuit block, the timing analysis conversion operation comprises:

converting the circuit block into the combinational circuit block, wherein the combinational circuit block is a logic gate level.

2. The mixed-signal circuitry simulation method of claim 1, wherein when the circuit block cannot be converted to the combinational circuit block, the timing analysis conversion operation comprises:

a timing value of the circuit block is set through a user input.

3. The mixed-signal circuitry simulation method of claim 1, wherein the combinatorial circuit block comprises a buffer.

4. The mixed-signal circuitry simulation method of claim 1, wherein the combinatorial circuit block comprises an inverter.

5. The mixed-signal circuitry simulation method of claim 1, wherein the combinatorial circuit block comprises a load.

6. An electronic device, comprising:

a processor; and

a storage device storing a program code, wherein when the processor loads and executes the program code, the following operations are performed:

performing a static timing analysis operation on the converted circuit system;

7. The electronic device of claim 6, wherein when the circuit block cannot be converted into the combinational circuit block, the timing analysis conversion operation comprises:

a timing value of the circuit block is set through a user input.

8. The electronic device of claim 6, wherein the combinational circuit block comprises a buffer, an inverter, or a load.