JP2001235522A - Test vector forming device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a required time for formation of a test vector used in a test device for executing a test of a semiconductor integrated circuit. SOLUTION: In a test vector formation support part 13, a test cycle time, a delay time of an input signal value and an expected value checking time are extracted from a pseudo peripheral circuit model, and a file for specifying extraction timing of test data is formed based thereon. And, static timing analysis is executed based on a net list of the pseudo peripheral circuit model and the semiconductor integrated circuit, to obtain the maximum and the minimum delay times of an output signal, and the delay time obtained by giving offset processing thereto is used as the expected value checking time, and a file for specifying input and output timings of the test vector is formed based on the expected value checking time and the delay time of an input signal value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a test vector generating apparatus for generating a test vector used in a test apparatus for performing a test at the time of manufacturing a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, a test vector used in a test apparatus for testing a semiconductor integrated circuit such as an LSI is considered, for example, in consideration of the specifications of the test apparatus.
It is created by manually inputting a signal value consisting of "1" and "0" using a test pattern editor.

In recent years, instead of test vectors composed of signal values of “1” and “0”, for example, Veril
og etc.-Connect to the semiconductor integrated circuit to be tested using HDL (hardware description language) such as HDL or C language or the like, for example, an arithmetic processing unit (CPU) or a peripheral circuit such as a memory or a standard bus A pseudo model is created, a logic simulation is performed using the pseudo peripheral circuit model and source code representing the operation of the semiconductor integrated circuit, and test data such as an input signal to the semiconductor integrated circuit and its expected output value are converted into a vector format. A method for automatically creating a test vector based on the extracted test data and timing information in consideration of the specifications of the test apparatus is known.

FIG. 16 is an explanatory diagram showing an outline of a test vector creating system for automatically creating a test vector using HDL, in which a peripheral circuit of a semiconductor integrated circuit to be tested is modeled. Pseudo peripheral circuit model 1
1, HDL source code 12 indicating the operation of a logic circuit realized by the semiconductor integrated circuit, and test data for designating a timing for extracting test data such as an input signal to the semiconductor integrated circuit and an expected output thereof. A logic simulation is performed in the logic simulation unit 20a based on the extraction timing designation file 16.
In the logic simulation performed by the logic simulation unit 20a, the test data 21 extracted at the timing specified by the test data extraction timing specification file 16 and the test vector timing specification file 17 that specifies the input and output timings of the test vector. The test vector generation program 22 for the test apparatus is executed based on the above, and a predetermined test vector 23 is generated.

Then, based on a netlist 15 obtained as a result of performing a logic synthesis process in a logic synthesis unit 14 based on the HDL source code 12 and the test vector 23,
The logic simulation is performed again in the logic simulation unit 20b. If the obtained test vector is not appropriate, the timing of the test data extraction timing designation file 16 is adjusted, the logic simulation is performed again by the logic simulation unit 20a, and the test data 21 is obtained. And the process is repeated until an appropriate test vector is obtained.

[0006]

In recent years, since many semiconductor integrated circuits have a large circuit scale, a method of manually creating a test vector using a conventional test pattern editor requires a great deal of time and effort. As a result, it is no longer being used. In the method of automatically creating a test vector by the test vector generation program for a test apparatus, a pseudo model of a peripheral circuit can be created relatively easily.

However, the logic simulation unit 2
Since the specifications of the logic simulation and the test conditions thereof at 0a and 20b are different from the specifications of the test apparatus and the test conditions thereof, a test for the timing of the logic simulation is performed to match the specification of the test apparatus with the test. The timing of extracting data and the timing of a test vector are manually specified, and the test vector is evaluated by performing a logic simulation based on these. For this reason, until the appropriate test vector can be obtained, the process of adjusting the timing of extracting the test data and the timing of the test vector, performing a logic simulation and evaluating the test vector is repeatedly performed. And require a lot of time.

Therefore, the present invention has been made in view of the above-mentioned conventional unsolved problems, and it is an object of the present invention to apply a test vector creating apparatus capable of reducing the time required for creating a test vector. It is an object.

[0009]

According to a first aspect of the present invention, there is provided a test vector generating apparatus, comprising:
In a test vector creating apparatus for creating a test vector used for a test apparatus for testing a semiconductor integrated circuit based on designated timing information,
And a timing information generating means for generating the timing information based on a pseudo peripheral circuit model representing a peripheral circuit of the semiconductor integrated circuit and circuit information of the semiconductor integrated circuit.

According to the first aspect of the present invention, a timing information generating means is provided based on a pseudo peripheral circuit model for simulating the operation of a peripheral circuit of a semiconductor integrated circuit and circuit information such as a netlist of the semiconductor integrated circuit. Timing information required to generate a test vector is generated. Therefore, unlike the related art, there is no need to manually set the timing information, and the time required for setting the timing information can be reduced.

According to a second aspect of the present invention, there is provided a test vector generating apparatus for performing a logic simulation based on the pseudo peripheral circuit model and circuit information of the semiconductor integrated circuit to extract test data at a predetermined extraction timing. A test vector generating apparatus configured to generate the test vector based on the test data and predetermined input / output timing information, wherein the timing information generating unit includes:
Data extraction timing specifying means for specifying the timing of extracting the test data based on the pseudo peripheral circuit model; and performing static analysis based on the pseudo peripheral circuit model and the circuit information. Test vector timing specifying means for specifying input / output timing of the test vector based on a peripheral circuit model,
It is characterized by having.

According to the second aspect of the present invention, the data extraction timing specifying means specifies the test data extraction timing required for generating the test vector, and the data extraction timing specifying means includes a pseudo peripheral circuit. The timing of extracting the test data is specified based on the model. The test vector timing specifying means specifies the input / output timing of the test vector. The test vector timing specifying means performs a static analysis based on the pseudo peripheral circuit model and circuit information such as a netlist. The output timing of the test vector is specified based on the result, and the input timing of the test vector is specified based on time information such as the output timing of the signal value to the semiconductor integrated circuit of the pseudo peripheral circuit model.

According to a third aspect of the present invention, in the test vector generating device, the data extraction timing specifying unit extracts predetermined time information from the pseudo peripheral circuit model, and performs offset adjustment on the extracted time information. It is characterized by that. According to the third aspect of the present invention, the data extraction timing specifying unit extracts time information from the pseudo peripheral circuit model, and performs offset adjustment on the extracted time information.

Here, when the input signal to the semiconductor integrated circuit is extracted based on the time information of the pseudo peripheral circuit model,
Since the output timing of the input signal value of the pseudo peripheral circuit model and the extraction timing of the input signal to be used as test data overlap, in some cases, an incorrect signal value before the input signal value is determined may be extracted. is there. However, by shifting the extraction timing so that these timings do not overlap by offset adjustment, it is possible to reliably extract a desired signal value.

Further, the test vector generating apparatus according to a fourth aspect is characterized in that the test vector timing specifying means performs offset adjustment on time information based on the static analysis. In the invention according to claim 4, the test vector timing specifying means performs offset adjustment on time information based on static analysis.

Here, when a test vector is generated based on time information based on static analysis, or when there is a variation in performance in the manufacturing process of a semiconductor integrated circuit, when the test is performed by a test apparatus, the performance of the test vector is reduced. An error due to the variation may occur. However,
In consideration of the performance variation, time information based on static analysis is offset, and timing information of a test vector is specified based on the time information after the offset, thereby avoiding a test error caused by the performance variation. It becomes possible.

[0017]

Embodiments of the present invention will be described below. FIG. 1 is a functional configuration diagram showing an example of a test vector creation device to which the present invention is applied. In FIG. 1, 11 is
H that models the peripheral circuit of the semiconductor integrated circuit to be inspected
A pseudo-peripheral circuit model 12 composed of DL data is used for controlling the operation of a logic circuit formed by a semiconductor integrated circuit to be inspected.
The HDL source code 13 described in L is test vector generation support as timing information generation means for generating test data required for generating a test vector and timing information for specifying the timing of the test vector. The unit 14 is a logic synthesis unit that performs a logic synthesis process based on the HDL source code 12 and generates a net list 15 representing connection information of a logic circuit of the semiconductor integrated circuit.

The test vector creation support unit 13 includes a netlist 15 generated by the logic synthesis unit 14 and the pseudo peripheral circuit model 11, which are circuit information of a semiconductor integrated circuit.
Based on the above, in a test apparatus for performing a manufacturing test of a semiconductor integrated circuit, a test which is input data to a semiconductor integrated circuit to be inspected and an expected output value when the input data is input to the semiconductor integrated circuit A test data extraction timing specification file 16 for specifying the timing for extracting the test data and a test vector timing specification file 17 for specifying the test vector input / output timing are generated.

The test data extraction timing designation file 16 and the pseudo peripheral circuit model 11,
A logic simulation is performed in the logic simulation unit 20 based on the HDL source code, and predetermined data is extracted at the timing specified by the test data extraction timing specification file 16 and stored as test data 21. .

Based on the test data 21 and the test vector timing specification file 17, a test vector generation program 22 for test equipment
A test vector 23 is generated. The test vector creation support unit 13, for example, as shown in FIG. 2, is configured by a computer such as a personal computer or a workstation capable of processing input data.
A display device 2 such as an RT display and an input device 3 such as a keyboard and a mouse are provided, and a storage device such as a memory or a hard disk (not shown) for temporarily storing processing data is provided. Then, predetermined time information is extracted from the pseudo peripheral circuit model 11 and the netlist 15, and a static analysis is performed based on the extracted time information.
6 and the test vector timing specification file 17 are generated.

Next, the operation of the above embodiment will be described with reference to the flowchart of FIG. Now, as shown in FIG. 4, a test vector for inputting the signals I1 and I2 and the clock signal CK and outputting the signal Q for executing a test of a semiconductor integrated circuit for realizing a logic circuit in a test apparatus is generated. It shall be.

First, a pseudo peripheral circuit model 11 described in HDL shown in FIG. 5, for example, representing a peripheral circuit of the semiconductor integrated circuit, and an HD representing the logical operation of the semiconductor integrated circuit
An L source code 12 is generated. Next, logic synthesis is performed in the logic synthesis unit 14 based on the HDL source code 12 to obtain, for example, a netlist 15 shown in FIG.

In the test vector creation support unit 13, the test data extraction timing specification file 1 based on the netlist 15 and the pseudo peripheral circuit model 11
6 and a test vector timing specification file 17 are generated. This is as shown in FIG.
Then, the clock cycle time of the clock generator (in this case, $ 10) is read from the clock generation circuit portion described in the pseudo peripheral circuit model 11 of FIG. Then, this is set as a test cycle time, and for example, as shown in FIG. 7, a signal name “CK”, an event name “pos”, and a cycle “20” are stored in a predetermined storage area.

Here, as shown in FIG.
Since the signal value of K is inverted every 10 times, the cycle is “2”.
In addition, in order to identify the clock cycle time of the clock generator from the pseudo peripheral circuit model 11, for example, the description of the signal name "CK" is recognized, or the description of "// clock generator" is recognized. And so on.

When there are a plurality of clocks in the pseudo peripheral circuit model 11, of the clock cycle time,
The fastest test cycle time is set and the value is stored. Next, the process proceeds to step S2, in which the pseudo peripheral circuit model 11 selects "{/
(Possedge CK) "is recognized and recognized as a trigger condition for changing the input signal, and" $ 5 "described subsequently is extracted as a delay time until the input signal is changed. For example, as shown in FIG. 8, a signal name, an event name, and a delay time are stored in association with each signal.

Next, the process proceeds to step S3, where it is determined whether or not the delay time extracted in step S2 falls within the test cycle time extracted in step S1, and the delay time is adjusted based on the result. In this case, the delay time is "5" as shown in FIG. 8, the test cycle time is "20" as shown in FIG. 7, and the delay time falls within the test cycle time. Therefore, the designer adds the offset time input from the input device 3 of the test vector creation support unit 13 to the delay time, and stores this as the input signal value extraction time.

For example, as shown in FIG. 9, the test cycle time Tcyc is "20", and the delay time T
If put is "5" and the offset time Toff input by the designer is "5", the delay time Tput falls within the test cycle time Tcyc, and thus the delay time Tpu
"10", which is the sum of t and the offset time Toff, is defined as the input signal value extraction time (corresponding to the time point indicated by に お い て in FIG. 9).

Conversely, if the test cycle time Tcyc is “2”
0, the signal value input delay time Tput is “25”, and the offset time Toff input by the designer is “5”.
In this case, the remainder "5" obtained by dividing the delay time Tput by the test cycle time Tcyc and the offset time Toff are added, and the result "10" is used as the input signal value extraction time.

Next, the process proceeds to step S4, where "$ (possed CK)" is identified from "// expected value collation" described in the pseudo peripheral circuit model 11, and this is compared with the expected value collation. Recognition is performed as a trigger condition for performing, and subsequently, “$ 15” is recognized as a delay time from when an event occurs until expected value comparison is performed, and this is extracted. Then, as shown in FIG. 10, for example, the signal name “Q”, the event name “pos CK”, and the delay time until the comparison (CMPARE) “15” are stored in a predetermined storage area.

Next, the process proceeds to step S5, where the data stored in the predetermined storage area in steps S1, S3 and S4 is as shown in FIG.
11, the offset time (# 5) shown in FIG. 11 is extracted based on the test cycle time information, the delay time of the input signal value offset-adjusted in the process of step S3, and the extracted data of the expected value comparison time in FIG. A test data extraction timing specification file 16 for performing the test is created. And
The processes in steps S1 to S5 correspond to data extraction timing specifying means.

Then, the process proceeds to step S6, where the test cycle time shown in FIG. 7 extracted in step S1 and the delay time of the input signal value before offset processing shown in FIG. 12, an input test vector timing specification file 17 for specifying the input timing of the test vector is created. Then, the process proceeds to step S7, where the static timing for performing the static timing analysis is determined based on the test cycle time shown in FIG. 7 extracted in step S1 and the delay time of the input signal value shown in FIG. 8 extracted in step S2. Create data for analysis. The static timing analysis data includes, for example, information specifying a test cycle time, an input signal, and information specifying a delay time thereof, as shown in FIG.

Next, the process proceeds to step S8, where a static analysis is performed based on the static timing analysis data and the netlist 15 generated in step S7.
The minimum delay time and the maximum delay time of the output signal are extracted and stored in a predetermined storage area as information including the maximum and minimum delay times, for example, as shown in FIG. Next, the process proceeds to step S9, and the designer adds the offset time to the output signal, which is input from the input device 3 such as the keyboard of the test vector creation support unit 13, to the maximum and minimum delay times extracted in step S8. The calculation result is added to the minimum delay time and subtracted from the maximum delay time, and the calculation result is stored in a predetermined storage area as the delay time of the output signal.

For example, when the offset time is “1”, the maximum delay time is added to “5” +
“1” = “6” and the minimum delay time are subtracted, and “2” − “1” = “1” are stored as expected value comparison times. Next, the process proceeds to step S10, and based on the expected value comparison time stored in step S9, for example, an output test vector timing specification file 17 for specifying the test vector output timing shown in FIG. 15 is created.

Thus, the test vector creation support unit 1
3, a test data extraction timing specification file 16 and a test vector timing specification file 17 are generated. The processing of steps S7 to S10 corresponds to the test vector timing specifying means. Then, based on the test data extraction timing designation file 16, the pseudo peripheral circuit model 11, and the HDL source code 12 generated as described above, a logic simulation is performed in the logic simulation unit 20 to extract the test data extraction timing. Timing specification file 1
6, the input data and the expected output value thereof are extracted to form test data 21. Based on the test data 21 and the test vector timing specification file 17, a test vector generation program for a test apparatus is generated. At 22, a predetermined process is performed to generate a test vector 23.

As described above, based on the predetermined time information of the pseudo peripheral circuit model 11, the test vector creation support unit 13 causes the test data extraction timing designation file 16
Is generated, the test data extraction timing designation file 16 can be generated without requiring much human labor. Therefore, the time required for creating a test vector can be significantly reduced as compared with the related art, and an input error or the like by a human can be prevented.

At this time, with respect to the delay time of the input signal extracted in the processing of step S2 in FIG.
Since the offset is performed in the processing of step 3, the input timing of the input signal to the logic circuit realized by the semiconductor integrated circuit and the timing of extracting the input signal specified by the test data extraction timing overlap. However, after the input signal to the logic circuit is determined, this signal is extracted as test data, and the desired input signal to the logic circuit can be reliably extracted.

Further, the maximum and minimum delay times of the output signal of the semiconductor integrated circuit obtained as a result of the static timing analysis are offset so that the time difference between the maximum delay time and the minimum delay time becomes longer, and this is set to the expected value. Since it is used as the collation time, it is possible to prevent a test error from occurring at the time of a test using a test apparatus due to a variation in device characteristics in manufacturing a semiconductor integrated circuit.

As described above, a fixed input signal to the logic circuit can be extracted as described above, and the occurrence of a test error due to manufacturing variations of the semiconductor integrated circuit can be avoided. Therefore, it is not necessary to repeatedly perform the logic simulation while finely adjusting each timing as in the related art, and it is also necessary to confirm the occurrence of a test error due to manufacturing variations of the semiconductor integrated circuit. There is no need to perform a logic simulation corresponding to the logic simulation unit 20b in FIG.

Therefore, not only the time required for creating a test vector, but also the processing steps for creating a test vector can be reduced. In addition, the pseudo peripheral circuit model 11
The HDL source code 12 is information used in a logic design stage of a semiconductor integrated circuit or in a test apparatus, and generates a test data extraction timing specification file 16 and a test vector timing specification file 17 based on existing information. Thus, the present invention can be realized without preparing new information.

Although the above embodiment has been described with reference to the case where the present invention is applied to a semiconductor integrated circuit that implements the logic circuit shown in FIG. 4, a timing designation file is generated by performing similar processing for other logic circuits. can do. Further, in the above-described embodiment, a case has been described where the test vector creation support unit 13 is constituted solely by a personal computer or the like as shown in FIG. 2, but a personal computer or the like constituting the test vector creation apparatus is described. The processing of FIG. 3 may be performed in the arithmetic processing unit.

[0041]

As described above, according to the first aspect of the present invention,
According to the test vector generating device according to the first and second aspects, the timing information generating means generates the timing information based on the pseudo peripheral circuit model and the circuit information of the semiconductor integrated circuit. The time required for setting information can be significantly reduced.

Further, according to the test vector generating apparatus of the second aspect, the data extraction timing specifying means can
The extraction timing of the test data is specified based on the pseudo peripheral circuit model, static analysis is performed by the test vector timing specifying means based on the pseudo peripheral circuit model and the circuit information, and the analysis result and the pseudo peripheral circuit model are analyzed. Since the input / output timing of the test vector is specified based on the time information, the timing information can be easily specified.

According to the test vector generating device of the third aspect, the data extraction timing specifying means adjusts the offset with respect to the time information extracted from the pseudo peripheral circuit model, so that the desired value can be surely obtained. The signal value can be extracted. Furthermore, according to the test vector generation device of the present invention, the test vector timing specifying means adjusts the offset with respect to the time information based on the static analysis. Thus, it is possible to prevent an error from occurring at the time of testing with the test device.

[Brief description of the drawings]

FIG. 1 is a functional configuration diagram of a test vector creation device to which the present invention is applied.

FIG. 2 is a block diagram illustrating a schematic configuration of a test vector creation support unit.

FIG. 3 is a flowchart illustrating an example of a processing procedure of a test vector creation support unit.

FIG. 4 is an example of a logic circuit realized by a semiconductor integrated circuit.

FIG. 5 is an example of a pseudo peripheral circuit model.

FIG. 6 is an example of a net list.

FIG. 7 is an example of extracted test cycle time data.

FIG. 8 is an example of extracted data of a delay time of an input signal.

FIG. 9 is an explanatory diagram illustrating a method of offsetting a delay time of an input signal.

FIG. 10 is an example of extracted data of a matching time of an expected value signal.

FIG. 11 is an example of a test data extraction timing designation file.

FIG. 12 is an example of an input test vector timing specification file.

FIG. 13 is an example of static timing analysis data.

FIG. 14 is an example of extracted data of minimum and maximum delay times of an output signal obtained by static timing analysis.

FIG. 15 is an example of a test vector timing specification file for output.

FIG. 16 is a block diagram showing a functional configuration of a conventional test vector creation device.

[Explanation of symbols]

 Reference Signs List 1 arithmetic processing unit 2 display device 3 input device 11 pseudo peripheral circuit model 12 HDL source code 13 test vector creation support unit 14 logic synthesis unit 15 netlist 16 test data extraction timing specification file 17 test vector timing specification file 20 logic simulation unit 21 Test data 23 Test vector

Claims (4)

[Claims] 1. A test vector creation device for creating a test vector used for a test device for testing a semiconductor integrated circuit based on designated timing information, wherein the test vector represents a peripheral circuit of the semiconductor integrated circuit. A test vector generating apparatus, comprising: timing information generating means for generating the timing information based on a pseudo peripheral circuit model and circuit information of the semiconductor integrated circuit. 2. A logic simulation is performed based on the pseudo peripheral circuit model and circuit information of the semiconductor integrated circuit to extract test data at a predetermined extraction timing.
A test vector generating apparatus for generating the test vector based on the test data and predetermined input / output timing information, wherein the timing information generating means performs the test based on the pseudo peripheral circuit model. Data extraction timing specifying means for specifying the extraction timing of the test data, static analysis is performed based on the pseudo peripheral circuit model and the circuit information, and the test vector of the test vector is determined based on the analysis result and the pseudo peripheral circuit model. 2. The test vector generating apparatus according to claim 1, further comprising: a test vector timing specifying unit that specifies input / output timing. 3. The data extraction timing specifying means,
Extracting predetermined time information from the pseudo peripheral circuit model,
3. The test vector creating apparatus according to claim 2, wherein offset adjustment is performed on the extracted time information. 4. The test vector generating apparatus according to claim 2, wherein said test vector timing specifying means performs offset adjustment on time information based on said static analysis.