WO2007000806A1

WO2007000806A1 - Semiconductor integrated circuit development support system

Info

Publication number: WO2007000806A1
Application number: PCT/JP2005/011798
Authority: WO
Inventors: Masayuki Satoh
Original assignee: Genesis Technology Inc.
Priority date: 2005-06-28
Filing date: 2005-06-28
Publication date: 2007-01-04
Also published as: TWI363257B; WO2007000953A1; TW200712810A

Abstract

A semiconductor integrated circuit development support system includes a control device of a fiduciary of a test of a semiconductor integrated circuit by using a tester and a terminal device of a client of the test connected to the control device via a network. When the control device receives a test program of a semiconductor integrated circuit from the terminal device, the control device analyzes an arbitrary part of the test program to extract tester operation data and compares the operation data to specification of each tester stored in advance, thereby extracting a usable tester. The control device transmits it to the terminal device.

Description

Specification

Semiconductor integrated circuit development support system

Technical field

[0001] The present invention relates to a support system for developing a semiconductor integrated circuit.

Background art

In recent years, along with the development of semiconductor technology, semiconductor integrated circuits such as LSI (Large Scale Integration) have become more sophisticated and diverse, and the development efficiency has become important.

The procedure for developing a semiconductor integrated circuit, that is, the procedure for producing a design capability, is generally as follows. When developing a semiconductor integrated circuit, we first design a system that is an operation-level design centered on functional operation. Next, logic design at the logic gate level and circuit design that expresses it at the element level are performed. Then, a mask is manufactured, and a wafer manufacturing process called a pre-process for forming a semiconductor integrated circuit on the wafer using the mask is started.

[0003] After that, the wafer manufactured in the previous process is tested by a probe test to determine pass / fail, the wafer is divided into chips (semiconductor integrated circuits), and the non-defective chips that are determined to be good by the probe test are selected. And then assemble it into a package.

This assembly is debugged by characterization, and if the characteristics are found to satisfy the desired value, it is transferred to mass production after final testing with a test program based on the final test specifications.

[0004] For each of these tests, a device called a tester is used. Testers are expensive devices that cost tens of millions to hundreds of millions of dollars per unit, and selecting testers with high usage costs is an important issue for users.

The tester is composed of a test head, a tester body, a controller, and the like. The test head is connected to the input / output terminals of the semiconductor integrated circuit to be tested and incorporates a plurality of interface boards called pin electronics that input / output signals to / from the semiconductor integrated circuit. [0005] The tester architecture includes a shared resource method in which a timing generator circuit and a pattern generator circuit are shared by a plurality of pins, a per-pin method in which each pin has a timing generator circuit and shares a pattern generator circuit, There is a method that has a timing generation circuit and a pattern generation circuit for each pin (hereinafter referred to as “full per-pin method”).

[0006] In the past, the power that shared-resource type testers were often used Recently, per-pin type testers have begun to be used frequently. In the future, it is estimated that many full-per-pin testers will be used. Each tester includes a power supply that supplies power to the semiconductor integrated circuit, a DC measurement system that evaluates the DC (Direct Current) characteristics of the input and output terminals of the semiconductor integrated circuit, and a DAC (Digital to Analog Convert)).

[0007] These testers are controlled by a test program that runs under the OS (operating system) of the CPU. This test program is described in a so-called tester language. The tester language is generally different for different tester architectures. This tester language initially had an assembler-style language called machine's word to directly control the hardware. On the other hand, tester control languages have been devised as having high programmability, and FORTRAN and BASIC formats have been used. Furthermore, the power that PASCAL, which is a structural language, was also used for a while. Currently, the C language is becoming mainstream.

[0008] In recent years, in the field of semiconductor integrated circuits, a circuit design company called a fabless company and a tool for evaluating functions of a semiconductor integrated circuit designed by a circuit design company on a computer such as a workstation. A company called EDA (Engineering 'Design Automation) Vendor, a test company that converts test programs related to semiconductor integrated circuits designed by circuit design companies into programs that testers can execute' It is manufactured by a mask manufacturing company that manufactures masks based on circuit design data designed by the company, and a wafer manufacturing company called test company that manufactures (manufactures) semiconductor integrated circuits using the manufactured masks. Test with your own tester Such as appeared only owe test 'Fuabu and call Bareru company, the horizontal component of the development of the semiconductor integrated circuit by these professional company Work is progressing.

[0009] Therefore, in Patent Document 1, first, a test company proposes a tester language to an EDA vendor, a circuit design company, and a wafer production company, and then the EDA vendor provides a semiconductor integrated circuit to the circuit design company. After that, a circuit design company designs a semiconductor integrated circuit with a desired logic function and verifies the logic function with a virtual tester (a tester is represented on the computer). After that, the test program produced in the tester language is transmitted to the test company via the Internet, and the test company selects the available tester based on the test program. It is disclosed.

Patent Document 1: Japanese Patent Laid-Open No. 2003-270305 (paragraphs 0033 to 0035, 06)

Disclosure of the invention

Problems to be solved by the invention

[0010] However, the technique of Patent Document 1 has a problem in that many specialized companies intervene before selecting a tester, which makes the work complicated or inefficient, and thus expensive. It was.

Accordingly, the present invention has been made in view of the above problems, and an object thereof is to provide an efficient support system for the development of a semiconductor integrated circuit including selection of a tester.

Means for solving the problem

In order to solve the above problems, a semiconductor integrated circuit development support system according to the present invention includes a control device held by a tester of a test of a semiconductor integrated circuit by a tester, and a control device held by the requester of the test. A semiconductor integrated circuit development support system comprising a terminal device connected to a device via a network, wherein the control device has a storage unit and a processing unit, and the storage unit is necessary for the test A tester language program that specifies and converts parameters to be used for the tester, and tester data that includes an allowable range of operation data of the tester that includes the parameters required for testing with respect to the plurality of testers. The processing unit transmits the tester language program to the terminal device in response to a request from the terminal device, and the tester language program. Test that was created in Te based ヽ When the program is received by the terminal device, an arbitrary part of the test program is analyzed to extract operation data of the tester, and the operation data and the tester data stored in the storage unit are obtained. A usable tester is extracted by comparison. The invention's effect

According to the present invention, an efficient support system can be realized for the development of a semiconductor integrated circuit including the selection of a tester.

Brief Description of Drawings

FIG. 1 is an overall configuration diagram of a semiconductor integrated circuit development support system.

[FIG. 2] A screen display example of the display unit 21 in the terminal device 20 of the circuit design company 2

[Fig. 3] A table showing an example of specifications for each tester.

[FIG. 4] A diagram showing a basic configuration common to each type of tester.

FIG. 5 is a diagram showing an example of a tester language TL.

[FIG. 6] (a) is a schematic diagram showing an RTL-type semiconductor integrated circuit. (B) is a schematic diagram showing a state where a multiplexer (MUX) 62 is attached to each flip-flop 61 when the SCAN method is used for the semiconductor integrated circuit L shown in (a).

FIG. 7 is a diagram showing a configuration of a shuttle service chip.

FIG. 8 is a flowchart showing the overall operation flow of the semiconductor integrated circuit development support system 1000.

FIG. 9 is a flowchart showing processing when extracting tester resources.

FIG. 10 is a flowchart showing processing when performing tester search and test cost calculation in step S808 of FIG.

FIG. 11 is a flowchart showing a process for calculating a chip area increase rate when using DFT by the SCAN method.

[Fig. 12] Flow chart showing the test cost calculation process when using the shuttle service.

FIG. 13 is a flowchart showing a process for calculating the test cost of the entire shuttle S in step S 1204 of FIG.

FIG. 14 is a flowchart showing a process for creating a defective gate map. Explanation of symbols

[0015] 1 testing company

2 Circuit design company

3 woo production company

4 network

10 Control unit

14 Memory

15 Processing section

20 Terminal equipment

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a semiconductor integrated circuit development support system of the present invention will be described with reference to the drawings. First, the configuration of the semiconductor integrated circuit development support system will be described with reference to FIGS.

FIG. 1 is an overall configuration diagram of a semiconductor integrated circuit development support system. The semiconductor integrated circuit development support system 1000 is composed of a test company (a test contractor) 1, a circuit design company (a test client) 2 and a wafer production company 3. Each of these devices has an Internet connection with each other. Connected with network 4 of.

Note that only one circuit design company 2 and one wafer manufacturing company 3 are shown in the figure, but there may be a plurality of them.

Although not specifically shown, a mask manufacturing company or a test jig manufacturing company may be involved in the development of a semiconductor integrated circuit.

[0018] The test company 1 is provided with a control device 10 for testing a semiconductor integrated circuit, and owns a plurality of types of testers (not shown). The control device 10 is a computer device such as a computer, a communication unit 11 for communicating with an external device, a force input such as a keyboard, an input unit 12 for inputting data, and a force input such as a display unit for data output. An output unit 13 for storing various data, a storage unit 14 for storing various data, a processing unit 15 configured to perform various arithmetic processing such as a CPU (Central Processing Unit), and a memory 16 which is a calculation area of the processing unit 15 /! The circuit design company 2 is specialized in circuit design of semiconductor integrated circuits and includes a terminal device 20. The terminal device 20 is a computer device such as a personal computer, and includes a display unit 21 that displays a screen.

Wafer manufacturing company 3 is to manufacture a wafer that is the basis of a semiconductor integrated circuit, and includes a terminal device 30 that is a computer device such as a personal computer.

FIG. 2 is a screen display example of the display unit 21 in the terminal device 20 of the circuit design company 2 (see FIG. 1 as appropriate). Here, the outline of each screen (window) will be explained, and details will be described later. In FIG. 2, each screen (window) is displayed at the same time, but may be displayed separately. Even if not specifically shown, the communication device of the terminal device 20 is all the control device 10.

The authentication window 22 is a screen on which the user of the terminal device 20 inputs a user name and password for authentication for communication.

Interactive editor window 23 is an interactive editor (tester language program: an editor that creates a test program in tester language) disclosed by test company 1

) Is used to input parameters (applied voltage, etc.) necessary for testing a semiconductor integrated circuit and create a test program.

[0022] For example, if the interactive editor uses a C language function description,

By preparing a C language function definition on the tester side for a tester operating in C language, it can be used in that tester without conversion. The interactive editor is stored in the storage unit 14 of the control device 10.

[0023] Further, since the necessary parameters are described in the test program created by the interactive editor, it is easy to convert the program even for testers that operate in languages other than C. It has the characteristics.

Therefore, by using this interactive editor, even a person with little knowledge about the tester can create an appropriate test program.

The test pattern window 24 is a screen on which the circuit design company 2 inputs a test pattern used for verifying the semiconductor integrated circuit. Here, the test pattern expresses the setting values of each parameter along the time series when simulating to verify the semiconductor integrated circuit. It is a thing.

[0025] Normally, the circuit design company 2 creates a test pattern by a method called a time-driven method in which a test pattern is described by extracting the timing information and logic value of the change point by monitoring the logic change point. However, the time-driven method is useful at the design stage, but there is a problem that the tester cannot be read as it is. For this reason, it is necessary to divide the test pattern at a fixed period and convert it to a method called the rate method that describes the test pattern as 1ZO information for the test pattern 'step, and make it readable by the tester.

Therefore, in this application, the circuit design company 2 is configured to input a test pattern in a time-driven manner and convert the test pattern into a late method in the test company 1. As a result, test company 1 performs a virtual test on the computer by combining the test pattern of the rate method and the RTL-format semiconductor integrated circuit data described later, and the result is sent to circuit design company 2 via the Internet. Thus, an efficient support system can be realized for the development of semiconductor integrated circuits.

In the following description, test patterns expressed in a time-driven manner are sometimes simply referred to as “patterns”.

[0027] Returning to the description of FIG. 2, the test pattern window 24 is displayed when the circuit design company 2 inputs the pattern file name, and the pattern format (text, VCD (Value Change Dump), WGL (Waveform veneration Language) This is a screen to select a pattern and input a pattern in a time-driven manner.

The navigation window 25 displays a list of available testers and the test costs when using each tester based on the data sent from the control device 10 of the test company 1, and selects a finance (payment) item. This is a screen for selecting the tester to be actually used.

[0028] In the virtual test window 26, when it is desired to execute a virtual test (virtual test performed on a computer device), a semiconductor integrated circuit is described in an RTL (Register Transister Logi Directly Connected Transistor Logic Circuit) format. This is a screen for inputting the RTL file name of the semiconductor integrated circuit and instructing it. Here, the semiconductor integrated circuit It is assumed that the road is in RTL format, but when other formats are used, the screen display is adjusted accordingly.

[0029] Design window 27 shows the rate of increase in the area of the semiconductor integrated circuit when DFT (Design for Testability) is adopted for the semiconductor integrated circuit based on the data received from the control device 10 of the test company 1. If you wish to use DFT, it is a screen that gives instructions along with the input of the RTL file name.

[0030] Shuttle window 28 is a screen for instructing calculation of a test cost when each shuttle service is used.

The defective gate map window 29 is a screen for displaying defective portions (positions of defective gates) on the wafer.

FIG. 3 is a table showing an example of specifications for each tester. This table is stored in the storage unit 14 (see Fig. 1), and shows the specifications for each tester, such as the maximum operating frequency and the number of pins.

FIG. 4 is a diagram showing a basic configuration common to testers of each method. As shown in FIG. 4, the tester 300 includes a power supply 301 that supplies a power supply voltage to the semiconductor integrated circuit L to be tested, a driver 302 that inputs a signal to an input terminal of the semiconductor integrated circuit L, a semiconductor Output terminal force of integrated circuit L Comparator 303 that compares the output signal with the expected value signal, pattern generator 304 that generates test data and expected value to be input to semiconductor integrated circuit L, and semiconductor integrated circuit L Input power of input signal! A timing generator 305 for generating timing, a controller 306 for performing each control by a test program, and a DC test circuit 307 for performing a DC test such as voltage level detection of an output pin.

[0033] The power supply unit 301 and the DC test circuit 307 are not different for each tester as in the test program, and the technique for measuring the semiconductor integrated circuit L does not need to be changed. can do.

FIG. 5 is a diagram showing an example of the tester language TL. In this tester language TL, tester description 5

Each tester resource at 0 (tester operation data including parameters necessary for tester operation) corresponds to each C language function form 52. For example, if the tester resource is the device power supply 51, the C function type 52 is “VS {number of mute, applied voltage, voltage range, measurement current range, upper limit clamp current, lower limit clamp current}”. In this case, to enter parameters for test by the tester using this tester language TL, enter each parameter such as the number of units (unit number of power supply) at the displayed position! ,. If it is not entered, the default parameters specified by the semiconductor integrated circuit development support system 1000 are entered, so that the producer who creates the test program does not need to understand all parameters. The same applies to other tester resources! / ヽ.

FIG. 6A is a schematic diagram showing a semiconductor integrated circuit in the RTL format. In the semiconductor integrated circuit L, a combinational circuit 67 and a plurality of flip-flops (FF) 61 that perform a predetermined logic operation are alternately arranged between an input terminal 68 and an output terminal 69. All other flip-flops 61 are connected by a clock line 66.

With this configuration, in the semiconductor integrated circuit L, the flip-flop 61 can be synchronized, signals input from the input terminal 68 can be processed in order, and signals can be output from the output terminal 69.

[0036] FIG. 6 (b) shows a case where a multiplexer (MUX) 62 is attached to each flip-flop 61 when the SCAN method is used for the semiconductor integrated circuit L shown in FIG. 6 (a). It is a schematic diagram showing the state of.

One multiplexer 62 is attached to one flip-flop 61. The multiplexer 62 is composed of three gates of AND gates 621 and 622 and an OR gate 623, and the test circuit line 63, the SCAN circuit line 64 and the combinational circuit line 65 are connected as shown in the figure.

In this way, in the semiconductor integrated circuit L of FIG. 6A, the flip-flops 61 can be linked in a chained manner, and the position of the defective gate can be specified during the test. Details of this SCAN method are described in Japanese Patent Laid-Open No. 2003-149300.

FIG. 7 is a diagram showing a configuration of the shuttle service chip. Enlarged view 71 shows wafer 70 It is an enlarged part. In enlarged view 71, there are three types of chips: 10mm X 10mm (A chip, etc.), 5mm X 10mm (B chip, D chip, etc.), and 5mm X 5mm (C chip, etc.).

In recent years, the fabrication of semiconductor integrated circuits has become very expensive due to the development of miniaturization processes and the use of sophisticated devices and multilayer wiring. Therefore, the shuttle service that manufactures multiple types of semiconductor integrated circuits on the same wafer is effective in reducing the manufacturing costs of semiconductor integrated circuits.

The configuration of the semiconductor integrated circuit development support system 1000 has been described above, and the operation will be described with reference to FIGS. 8 to 14 (see FIG. 1 as appropriate).

[0039] First, the test company 1 publishes a homepage (HP) about introduction of a tester used for testing a semiconductor integrated circuit using the control device 10 (step S801).

Circuit design company 2 uses the terminal device 20 to create circuit design data related to the semiconductor integrated circuit to be manufactured (step S802). Based on the circuit design data, circuit design company 2 manufactures wafers to Ueno and manufacturing company 3. The request, that is, information to that effect is transmitted to the terminal device 30 of the wafer production company 3 (step S803).

[0040] Next, the circuit design company 2 uses the terminal device 20 to search the Internet to find a tester for testing the semiconductor integrated circuit to be manufactured, and the test company 1's home page. You can access and use an interactive editor through the Internet. An interactive editor can also be downloaded from the control device 10 and used. (Step S804). Even if you are not an interactive editor, you can download another test program creation tool.

Also, when accessing the test company 1's website, authentication is required, and the circuit design company 2 enters the user name and password in the authentication window 22 (see Fig. 2) of the display unit 21 and enters this environment. Can be used. As a result, the security level of information communication can be increased.

Subsequently, the circuit design company 2 uses the terminal device 20 while referring to the display unit 21 to Create a test program that describes the test items of the semiconductor integrated circuit based on the circuit design data while using the interactive editor in the Tharatative Editor Window 23 (see Figure 2). Also, text, VCD, WGL, A pattern is created in one of the STIL formats (step S805), and the test program and pattern are sent to the control device 10 of the test company 1 (step S806). In step S806, the test pattern window 24 (see Fig. 2) is used, and the format of the no-turn file and four intermediate forces are selected and transmitted.

Note that the test program created using the interactive editor is a statement method description based on the electrical measurement method, and has the characteristic that the meaning of the command statement can be easily recognized from the description content.

In step S807, the test company 1 extracts the test program power tester resource received from the circuit design company 2 by the processing unit 15 of the control device 10 (details will be described later in FIG. 9). The processing unit 15 of the control device 10 also generates a late test pattern for the pattern force received from the circuit design company 2. This test pattern force is also stored in the control device in advance so that hardware capable of generating a timing signal at the speed or specification required for the test (hereinafter referred to as timing resource) is used. Extract medium power. In addition, the length of each pattern required for the test is extracted by the hardware used by the pattern generator.

[0043] When extracting timing resources, the processing unit 15 extracts necessary data by analyzing the whole test pattern or an arbitrary part (for example, about 10%). With recent test patterns related to circuit design data based on RTL synchronization, it is possible to guarantee acquisition of necessary information by analysis of several to several tens of percent. Analyzing the entire test pattern is time consuming and expensive. However, if only a few prayers are completed, the labor savings for test company 1 can be realized.

Next, the test company 1 uses the control device 10 to search (extract) usable testers and calculate a test cost for each tester (step S808: details will be described later in FIG. 10).

[0044] If DFT is used in step S808, it is possible to lower the test cost by extracting a cheaper tester, and at the same time, calculate the chip area increase rate by using DFT. The information can be presented to the circuit design company 2, but its details Is described later in FIG.

In step S808, the calculation of the test cost when the shuttle service is used will be described later with reference to FIGS.

Subsequently, the test company 1 uses the control device 10 to transmit the usable tester and the test cost for each tester to the terminal device 20 of the circuit design company 2 (step S809).

In response to this, the circuit design company 2 displays the received usable tester and each test cost on the display unit 21 by the terminal device 20 (see the navigation window 25 in FIG. 2).

[0046] When circuit design company 2 wishes to execute a virtual test, it designates the circuit design data (RTL file) name in virtual test window 26 of display unit 21 using terminal device 20, and performs virtual test. By checking the item and sending it to the control device 10, the test company 1 is requested to execute the virtual test (step S810).

[0047] The test company 1 uses the control device 10 to execute a virtual test by the processing unit 15 based on the test program, test pattern, and circuit design data, and the result is the terminal device 20 of the circuit design company 2. (Step S811).

By executing this virtual test, it is possible to find test patterns and timings that are not suitable for each tester. Based on the results, circuit design company 2 can modify the test programs and test patterns as appropriate. it can.

[0048] When a virtual test is performed based on the logic function of the semiconductor integrated circuit, it is desirable that the verification be performed by a rate method. Here, the rate method means a pattern generation method opposite to a pattern generation method called a time driven method or a time event method. Specifically, while the time event method monitors the logic change point and extracts the timing information and logic value of the change point to generate the pattern, the rate method delimits the pattern at a fixed period. The test pattern is generated as I / O information for Noturn 'step.

Also, here, even if the test pattern used is not all, it can be an arbitrary part (several percent to several tens of percent) as long as it is within a range where defects can be found sufficiently. Thus, each work can be shortened and efficiency improved.

[0049] Next, the circuit design company 2 uses the terminal device 20 to install a tester used for the actual test. A test is requested by selecting and transmitting to the control device 10 of the test company 1 (step S8 12).

Then, as necessary, the test company 1 prepares for the test work such as converting the test program into a tester operation program or preparing a tool (step S813).

[0050] Wafer manufacturing company 3 receives a wafer creation request from circuit design company 2 (step S8 03), creates a wafer (step S814), and delivers the wafer to test company 1. (Step S815).

Test company 1 then performs wafer tests using control device 10, tester, test program (converted to operation program if necessary), test pattern, circuit design data, jigs and tools ( In step S816, the wafer and test results are transferred to the circuit design company 2 (step S817). The test result may be transmitted from the control device 10 to the terminal device 20.

Finally, the control device 10 registers various information such as tester resources and test results in the storage unit 14 (step S818). By using this information, test company 1 can grasp the trends in circuit design company 2's demands regarding the tester's frequency, pin count, pattern length, timing resources, etc. Cost testers can be properly developed.

FIG. 9 is a flowchart showing processing when extracting tester resources in step S807 of FIG.

In the control device 10, the processing unit 15 inputs the test program, that is, stores the test program (see the interactive editor window 23 in FIG. 2) received from the terminal device 20 of the circuit design company 2 in the storage unit 14 ( Step S901).

[0053] The processing unit 15 starts from the line number n = 0 of the test program (step S902), and searches for the first line by n = n + 1 (step S903). It is determined whether the program is related to the number of pins (step S904).

If the line is a Pin statement (Yes in step S904), the processing unit 15 extracts the value of the number of pins from the Pin statement and stores it in the storage unit 14 (step S905).

[0054] If the processing unit 15 does not have the power Pin statement (No in step S904), the processing unit 15 proceeds to step S90. Proceed to step 6 to determine whether the line is VS sentence power or not, that is, whether or not the program power related to the device power supply.

If the line is a VS sentence (Yes in step S906), the processing unit 15 extracts the value of the number of power sources in the VS sentence and stores it in the storage unit 14 (step S907).

Note that here, the power to extract and store values only for the number of pins and the number of power supplies in the tester resources. Actually, the values for other tester resources are also extracted and stored in the same manner. .

[0055] The processing unit 15 determines whether or not the line is the last line (step S908), and if it is not the last line (No), returns to step S903 and repeats the process, and if it is the last line (Yes), End processing.

In this way, the control device 10 can also extract tester resources by the test program power.

In the control device 10, the processing unit 15 inputs tester resources and the like, that is, stores the tester resources and timing resources extracted in step S807 of FIG. 8 in the storage unit 14 (step S1001).

[0057] Next, the processing unit 15 acquires tester information from the storage unit 14, that is, acquires data relating to the tester specifications (see FIG. 3) (step S1002).

The processing unit 15 starts from the tester model n = 0 (step S1003), searches for the specification of the first tester by n = n + l (step S1004), and each value of the tester resource is the tester's tester. Judgment is made as to whether or not the power of the model resource (tester data) is satisfied (step S 1005).

[0058] If the condition is satisfied in step S1005 (Yes), the processing unit 15 displays the tester (available tester) on the output unit 13 (step S1006), and satisfies the condition. If (No), go to Step S1007.

In step S1007, the processing unit 15 determines whether or not the processing has been completed for all models of the tester. If not, (No) returns to step S1004 and repeats the processing. If it has been completed (Yes), the test cost of each available tester is calculated and displayed on the output unit 13 (step S 1008).

When calculating the test cost, first, the time required for the test is obtained. The time required for the test can be obtained by considering the type of tester language describing the test program, and does not depend much on the type of tester used. The test cost can be obtained by multiplying the calculated test time by the time unit cost for each tester (such as 3 yen Z seconds). The time unit usage cost of the tester may be appropriately calculated by the processing unit 15 from the purchase price, usage time, depreciation period, labor cost, etc. of the tester stored in the table of the storage unit 14 (see Fig. 1).

In this way, the available testers can be searched (selected) and the test cost of each tester can be calculated.

FIG. 11 is a flowchart showing a process for calculating the chip area increase rate when the DFT using the SCAN method described in FIG. 6B is used.

First, in the control device 10, the processing unit 15 inputs RTL, that is, stores circuit design data in the RTL format in the storage unit 14 (step S1101).

Next, the processing unit 15 performs logic synthesis, that is, converts circuit design data in the RTL format into a logic circuit (step S 1102).

Subsequently, the processing unit 15 counts up the total number N of gates including flip-flops in the logic circuit (step S1103), and counts the number n of the flip-flops (step S1104).

The processing unit 15 calculates the number of gates m used in the multiplexer (MUX) by m = 3 × n (step S 1105). As explained in Fig. 6 (b), when DFT using the SCAN method is used, three multiplexers are added to one flip-flop, so the number of gates m can be obtained from m = 3 X n.

Finally, the processing unit 15 calculates the area increase rate (%) of the chip by DFT using mZN ′ 100 (step S 1106).

In this manner, the control device 10 can calculate the chip area increase rate when the DFT is used. If DFT based on the SCAN method is used, the chip manufacturing cost increases due to the increase in chip area, but the number of pins required for testing can be reduced and the test frequency can be reduced. S808 can search (extract) an inexpensive tester as an available tester, thereby reducing the test cost.

[0064] Therefore, even if circuit design company 2 has insufficient knowledge of DFT in step S812 of FIG. 8, each cost situation such as an increase in chip manufacturing cost due to an increase in the chip area and a decrease in test cost is considered. Based on this, it is possible to more appropriately determine the power or inability to use DFT. If circuit design company 2 wishes to use DFT, it can input DFT use via design window 27 (see Figure 2) of display 21 and send it to control device 10 of test company 1. .

FIG. 12 is a flowchart showing a test cost calculation process when using the shuttle service. In the following, the number of samples refers to the target chip divided by the unit area. For example, in Fig. 7, if the unit area is 5 mm square (25 mm ² ), A chip, B chip, C chip And D chip sample numbers are 4, 2, 1 and 2, respectively. In addition, the test cost calculation process when using the shuttle service shown in Fig. 12 corresponds to the test cost calculation in step S808 in Fig. 8. In this case, the wafer is manufactured from the circuit design company 2 in Fig. 8. The wafer production request to company 3 (step S803) will be made after step S808.

First, the circuit design company 2 uses the terminal device 20 to select a shuttle (see shuttle window 28 in FIG. 2), and transmits the data to the control device 10 of the test company 1.

Next, in the control device 10 of the test company 1, the processing unit 15 inputs the shuttle (shuttle S) received from the terminal device 20 of the circuit design company 2 and the number of samples of the target chip into the storage unit 14 ( Step S 1201).

[0067] Subsequently, the processing unit 15 refers to the database related to the shuttle service stored in the storage unit 14, and determines whether or not the shuttle S has a vacant space corresponding to the number of samples (schedule). Step S 1202).

The processing unit 15 ends the processing when there is not enough space for the number of samples in the shuttle S (No in step S1202), and when there is space for the number of samples in the shuttle S (Y in step S1202) es), the chip is registered in the database related to the shuttle service in the storage unit 14 (step S1203). By this registration, the free area of the shuttle S will be reduced accordingly.

[0068] Next, the processing unit 15 calculates the test cost of the entire shuttle S (step S1204: details will be described later in Fig. 13), and divides the test cost of the entire shuttle S by the total number of samples per unit area. The test cost of the chip is calculated, and the test cost of the chip is calculated by multiplying the value by the number of samples of the specific chip (step S 1205).

Thereby, the control device 10 can calculate the test cost of the chip in the shuttle S.

FIG. 13 is a flowchart showing processing for calculating the test cost of the entire shuttle S in step S1204 of FIG.

First, the processing unit 15 sets M, which is the number of tester models used for the shuttle S test, to 1 (step S1301).

[0070] Next, the processing unit 15 sets the shuttle product number, that is, the product number of the chip manufactured by the shuttle S, to 0 (step S1302), and sets the total test time T to 0 (step S).

1303).

Subsequently, the processing unit 15 adds 1 to the value of the shuttle product number by D = D + 1 (step S

1304), by referring to the storage unit 14, it is determined whether or not the tester used for the chip having the shuttle product number is already registered as the tester used for the shuttle S (step S1305).

[0071] If the tester has already been registered (Yes in step S1305), it is not necessary to change the number of tester models used for Shuttle S. If the tester has not yet been registered (No in step S1305) ), The processing unit 15 registers the tester in the storage unit 14 as a tester to be used for the shuttle S (step S 1306), and this increases the number of tester models to be used for the shuttle S, so that M = M + The value of M is updated by 1 (step S 1307).

[0072] Next, the processing unit 15 reads the test time t per sample number from the storage unit 14 from the storage unit 14 (step S1308), and T = T + t X number of samples (tested with the tester) The value of T is updated according to the number of samples of the chip to be used (step S1309). Subsequently, the processing unit 15 determines whether or not the chip is the final product (step S 13 10), and if it is not the final product (No), returns to step S1304 and repeats the process, and if it is the final product, (Yes), the total work change time, that is, the total time required to change the tester is calculated by TD = change work time (work time required for one tester change) X (M-1) (Step S 1311).

Thereafter, the processing unit 15 calculates the test cost of the entire shuttle S by (T + TD) X unit price (test cost per unit time) (step S1312). Note that the test cost for the entire Shuttle S may be calculated using different unit prices for each tester.

In this way, the control device 10 can calculate the test cost of the entire shuttle S in the shuttle service.

[0074] Then, the smaller the number of testers used for each chip in the same shuttle (the number of models), the lower the test cost of the entire shuttle S, and the lower the test cost of each chip. Therefore, if the circuit design company 2 seeks a tester with a lower test cost by performing the processing shown in FIGS. 12 and 13, the number of testers used in the same shuttle is reduced, and the test company 1 is also working. It can be efficient.

In addition, the yield of chips (ratio of non-defective products) can be improved by conducting tests with the shuttle.

FIG. 14 is a flowchart showing processing when creating a defective gate map. The defective gate map is a map that displays defective locations (positions of defective gates) on the wafer. The defective gate map created here is used as part of the test result in step S817 in FIG.

[0076] The processing unit 15 of the control device 10 inputs the defective data (defective pattern) obtained from the test performed in step S816 of Fig. 8, that is, stores it in the storage unit 14 (step S1401). The processing unit 15 refers to a gate dictionary that is a data base related to the gate on the wafer stored in the storage unit 14 (step S 1402), and identifies a defective gate (step S 1403). In the gate dictionary, defective data and a defective gate are associated with each other.

Subsequently, the processing unit 15 acquires the layout information of the wafer stored in the storage unit 14. (Step S1404), the position of the defective gate is specified (Step S1405).

Then, the processing unit 15 determines whether or not it is the final defective data force, that is, whether or not the processing has been completed for all the defective data (step S 1406), and if it is not the final defective data (No), Returning to step S1401, the process is repeated, and if it is the final defective data (Yes), the process ends.

In this way, a defective gate map is created, and in step S817 of FIG. 8, the control device 10 of the test company 1 transmits the defective gate map to the terminal device 20 of the circuit design company 2, and the terminal device 20 The display 21 shows the defective gate map (see the defective gate map window 29 in FIG. 2). The defective gate map can be created for each chip or for the entire wafer.

The circuit design company 2 can estimate or identify the cause (contamination of foreign matter, etc.) in the chip manufacturing process by looking at the defective gate map. It is possible to improve the efficiency efficiently and improve the yield (ratio of non-defective products) in the production of semiconductor integrated circuits.

[0079] Although the description of the embodiments is finished as above, the aspects of the present invention are not limited to these.

For example, the present invention can be applied to all devices using semiconductor technology, such as a memory that can be used only by a semiconductor integrated circuit such as an LSI.

As DFT, another technology such as BIST (Built-In Self-Test) that uses only SCAN may be used.

Furthermore, when each device transmits and receives various data via the network 4, the security level may be improved by encryption using only a password or the like. In addition, specific configurations such as hardware and flowcharts can be appropriately changed within a range without departing from the gist of the present invention.

Claims

The scope of the claims

[1] Development of a semiconductor integrated circuit comprising a control device owned by a tester of a semiconductor integrated circuit test by a tester and a terminal device held by the test requester and connected to the control device via a network A support system,

The control device includes a storage unit and a processing unit,

The storage unit designates parameters necessary for the test, converts the tester language program used for the tester and uses the tester for the operation of the tester including the parameters necessary for the test with respect to the plurality of testers. Store tester data including the allowable range of data,

When the processing unit transmits the tester language program to the terminal device in response to a request from the terminal device and receives the test program created based on the tester language program, the terminal device power, Analyzing an arbitrary part of the test program to extract the tester operation data, and comparing the operation data with the tester data stored in the storage unit to extract usable testers A semiconductor integrated circuit development support system characterized by:

[2] The storage unit further stores a time usage unit price for each tester,

The processing unit further converts an arbitrary part of the test program into an operation program for the tester, estimates a required test time for each usable tester based on the operation program, and Based on the time and the unit price stored in the storage unit! / Calculate the test cost for each usable tester and send the usable tester and the test cost for each tester to the terminal device.

The semiconductor integrated circuit development support system according to claim 1, wherein:

[3] The storage unit further stores a calculation formula for calculating an increased area of the semiconductor integrated circuit when design for testability is used for the semiconductor integrated circuit,

The processing unit calculates the increased area when the testability design is used based on the calculation formula stored in the storage unit, and the processing when the testability design is used. The increased area is transmitted to the terminal device together with an available tester and its test cost. The semiconductor integrated circuit development support system according to claim 2.

[4] The calculation expression is an expression for calculating the increased area based on adding three gates to each flip-flop in the semiconductor integrated circuit. Item 4. The semiconductor integrated circuit development support system according to Item 3.

[5] The processing unit further specifies the position of the data force defective gate generated when the semiconductor integrated circuit is tested by the tester, and creates a defective gate map indicating the position of the defective gate, 4. The semiconductor integrated circuit development support system according to claim 3, wherein the defective gate map is transmitted to the terminal device.

[6] A control device possessed by a tester of a semiconductor integrated circuit test by a tester and a terminal device possessed by the test requester and connected to the control device via a network, and the same wafer A semiconductor integrated circuit development support system for manufacturing a plurality of types of semiconductor integrated circuits on a board,

The control device includes a storage unit and a processing unit,

The storage unit designates parameters necessary for the test, converts the tester language program used for the tester and uses the tester for the operation of the tester including the parameters necessary for the test with respect to the plurality of testers. The semiconductor integrated circuit based on tester data including an allowable range of data, a time unit usage price for each tester, and a test time including replacement work time for a plurality of testers for each of the plurality of wafers. And a calculation formula for calculating the test cost of

When the processing unit transmits the tester language program to the terminal device in response to a request from the terminal device and receives the test program created based on the tester language program, the terminal device power, Analyzing an arbitrary part of the test program to extract the tester operation data, and comparing the operation data with the tester data stored in the storage unit to extract usable testers And calculating a test cost of the semiconductor integrated circuit based on the calculation formula stored in the storage unit, and transmitting a tester usable for each wafer and the test cost to the terminal device. Semiconductor integrated circuit development support system.