TWI363185B - - Google Patents

Description

[185] IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a support system developed with a semiconductor integrated circuit. [Prior Art] In recent years, with the development of semiconductor technology, the development and efficiency of semiconductor integrated circuits such as LSI (Large Scale Integration) have progressed, and the research and development efficiency has become more and more important. The development steps of the _ + volume body circuit, that is, the steps from design to manufacture are generally as follows. When developing a semiconductor integrated circuit, the design of the action level, that is, the system design, is first performed. Next, enter the (four) inter-layer, the logical design of the level and the electrical design of the design at the component level. Then, the process is switched to a manufacturing process called a pre-wafer process in which a photomask is fabricated and an integrated circuit is formed on the wafer using the photomask. Then, using the probe test to test the wafer fabricated in the pre-process, determine whether it is a good product, and divide the wafer into a wafer (semiconductor integrated circuit) to find out that it is good by the probe test. A good wafer is assembled for the package. This assembly is debugged by characterization and, when it is determined that the characteristic meets the desired value, is transferred to mass production via the final test of the bin program according to the final test specification. In some of these tests, a device called a test machine is used. The test machine is a high-priced device for every tens of thousands of yen to hundreds of millions of rounds, and the cost of use is high. The selection of the 'Be J test machine is an important issue for the user^

2036'7232-PF 5 ICO = Test machine consists of test head, job body, controller, etc. The term "terminal" refers to the input and output of the semiconductor integrated circuit as the test object, and a plurality of dielectric panels for inputting and receiving signals to the semiconductor integrated circuit are built in. The structure referred to as the "testing machine" includes a shared resource method for generating a circuit and a pattern generating circuit when a plurality of pins are shared, and a circuit for generating a circuit and sharing a pattern generating circuit for each /. The foot mode has a timing generation circuit and a pattern generation circuit on each of the pins (hereinafter referred to as "completely for each pin method"). k went to the test machine that used the resources together, but recently, many people started using the method for each (four). After pushing the material, there will be more people to fully handle each pin. Each of the test machines has a power supply for supplying power to the semiconductor integrated circuit, a DC measurement system for evaluating DC (Direct Current) characteristics of the input and output terminals of the semiconductor body circuit, and a DC level DAC for supplying the semiconductor integrated circuit (Digital) t〇Anal〇gC〇nverter) converters, etc. These test machines are controlled by a test program that operates under the operating system (the operating system). This test program is written in the so-called test machine language. In other words, different test machine architectures, supported by The test machine language is also different. In this test machine language, 'includes the language that was originally used to directly control the hardware and is called the combined language form of machine language. In contrast, in the highly fluent language, the test has been designed. The machine control language also uses the 卩(10)"... form and the BASIC form. In addition, the structured language pASCAL has also been widely used. 'Currently, the C language § is the main one. In addition, in recent years, in the field of semiconductor integrated circuits. In the middle, there are 6

2036-7232-PF ^^185, the company's include: a circuit design company called a non-manufacturing company, providing tools to evaluate the function of the semiconductor integrated circuit set by the circuit design company on a computer such as a workstation. Also known as EDA (Engineering/Design/Automatic Reconstruction.) = The company of the seller, the semiconductor integrated circuit designed by the circuit design company, the four-way test program is converted into a program that the test machine can execute and is called test I. The company that has been inspected, the circuit design designed by the circuit design company, the mask manufacturing company that produces the mask for the poor material, and the wafer fabrication company that manufactures the semiconductor integrated circuit using the fabricated photomask and is called the manufacturing waste company. The company's semiconductor integrated circuit development has progressed to division of labor, using a test program produced by a test company to contract tests of all test machines and called test manufacturing. "Therefore, in Patent Document 1, a technology related to a business model is disclosed," which is a 'first' test company that proposes a test machine language to an enteric vendor, a circuit design company, and a wafer fabrication company, and then, a ship dealer. The circuit design company provides logic simulation of the semiconductor integrated circuit. After that, the circuit design company designs the semiconductor integrated circuit with the desired logic function, and performs the logic function of the virtual test machine (showing the function of the test machine on the computer). 'Detection' then transmits the test program made by the test machine language to the test company via the Internet, and then the test company selects the test machine that can be used according to the test program. Patent Document 1····· 270305 (Paragraphs 0033 to 〇〇35, FIG. 6) [Disclosure] [Problems to be Solved by the Invention] However, there is a problem in the technique of Patent Document 1, that is, selection at 2036-7232-PF 7 1363185 Before the test machine, there were many professional companies that were complicated or inefficient, so the cost has become more and more. Invented in the above-mentioned problems, providing a semi-conducting system such as selection. The development of volumetric circuits is related to and efficient. [Means for Solving the Problem] For the problem of loading, the semiconductor dragon circuit development support of the present invention is The test machine is used as a trustee of the semiconductor integrated circuit test: the device is installed by the client of the above test and connected through the Internet control device, and the control device has a memory portion: the memory portion The storage test language program and the test machine test language program are specified and converted in the above test order and used on the above test machine. The test machine data includes the allowable range of the action data of the upper machine, and the plurality of the above tests and tests Including the necessary parameter 'When the processing unit receives the test program of the semiconductor integrated circuit from the terminal device in response to a request from the terminal device, 'can analyze any part of the test program and extract the action of the track tester Using the data, by comparing the two data of the action and storing the above test machine data of the memory department, [Effect of the Invention] According to the present invention, an efficient support system can be realized in the development of a semiconductor integrated circuit including selection of a test machine, etc. [Embodiment] Hereinafter, a semiconductor integrated body of the present invention will be described with reference to the drawings. Circuit development support 2036-7232-PF 8 1363185 system. First, the structure of the semiconductor integrated circuit support system will be described with reference to Fig. 1 to Fig. 7. _ Fig. 1 shows the overall structure of the semiconductor integrated circuit development support system. & Figure. The semiconductor integrated circuit development support system 1 000 includes the test company (trustee of the measurement $) 1, the circuit design company (the tester's commissioner) 2, and the wafer system; ^ ^ division 3, these companies Each of the devices is connected to each other by an Internet 2 or the like. In addition, the circuit design company 2 and the wafer fabrication company 3 are displayed in one figure in the figure, but may be plural. In addition, although not specifically shown, the mask manufacturing company and the testing and tooling company can also have a relationship with the development of semiconductor integrated circuits. When the test company 1 is to perform the test of the semiconductor integrated circuit, the control device 10 is additionally provided with a plurality of test machines. The control device 10 is a computer device such as a personal computer, a communication unit U for communicating with the external device, an input unit 12 configured by a keyboard or the like for inputting data, and a display unit for data output. The output unit 13 is a memory unit 14 that stores various types of data, and a processing unit 15 that performs various types of arithmetic processing, such as a coffee (-trai and ΤΓΓβ It), as the memory 16 of the calculation area of the processing unit 15. The company 2 specializes in the circuit design of the semiconductor integrated circuit: I, device 2〇. The terminal device 20 is a computer device such as a personal computer, and has a display unit 21 that displays a screen.廄: Round!: Company 3 is a wafer that mainly uses semiconductor integrated circuits. It includes terminal devices 30 for computer devices such as personal computers. 2036-7232-pp 1363185 Fig. 2 is a display unit (10) in the terminal device 2 () of the circuit design company 2: an example of a surface display (please refer to FIG. 1 as appropriate). Here is a summary of each written (see), details of which are described later. In addition, in the second picture, each picture (window) is displayed simultaneously and can be displayed separately. In addition, even if it is not specifically shown, the terminal steps into Jinchuan and s θ as the device. : The device-like image is controlled by the user. The user of the terminal device 2G is used to input the user name and password of the witness during communication. The interactive editor window 2 3 is a face-to-face, using the interactive editor indicated by the test company i (test machine language program: the tester to make the test program by the test machine), input the semiconductor product Measurement of the body circuit;: Required parameters (applying voltage, etc.) to make a test program. If the interactive editor uses the function of the C language to write, for the test run by the C language, the function of the c language is pre-set on the test machine, i °,. , and the test can be used without conversion. machine. The interactive editor is stored in the memory unit 14 of the control unit 1 . In addition, there is a feature that the necessary test money is written in the test program created by the interactive editor. It is also easy to convert the program to a test machine operating in a language other than C. So by using this interactive editor, you can write a suitable test program for those who don't know much about the test machine. The test pattern window 2 4 is a screen for the circuit design company to input a test pattern for inspecting the semiconductor integrated circuit. Here, the term "test pattern" refers to a set value of each parameter when the module 2036-7232-PF 10 is used to inspect the semiconductor integrated circuit in accordance with the chronological order. Usually, in circuit design company 2, a type of time-driven party is created to produce a s-pattern, which is to update the point-time information by monitoring the logic change 7 to write a test pattern. Although it is useful to drive the design between the slaves and the slaves, there is a problem that the tester cannot read them directly. Therefore, it must be converted into a method called rate mode, which is to divide the test pattern by a certain period and write the test pattern as 1/() information to write the test pattern. It can be read on the S type machine. Therefore, in the structure of the present invention, the circuit design company 2 inputs the test pattern in a time-driven manner and converts it into a rate mode in the test company. In this way, the test company 1 can combine the rate mode test program and the RTL form of the semiconductor integrated circuit data described later to perform a virtual test on the computer, and transmit the result to the circuit design company 2 via the Internet, etc. A research and development-related and efficient support system for semiconductor integrated circuits. Further, in the following description, the test program expressed in a time-driven manner is simply referred to as "pattern" for distinction. Returning to the description of Figure 2, the test pattern window 24 is the circuit design company 2 input pattern file name, select the pattern form (text, VCD (Value Change

Dump), WGL (Wavef〇rm Generation Language), STIIXStandard Tester Interface Unguage)) and input the pattern of the pattern in a time-driven manner. The Pan 1 view window 25 is a screen which can display a list of usable test machines 2036-7232-PF 11 1363185 and the use of each test machine based on the data transmitted from the control device 10 of the test company 1. The cost of column 4, the straw is selected by the financial situation (accounting) project, to find out which test machine will actually be used. The virtual test window 26 is a screen that can be used to perform a virtual test. In the case of a virtual test performed on a computer device, when the semiconductor integrated circuit is written in the form of RTL (Register, for example, a direct-connected register logic circuit), the semiconductor integrated circuit is input. The RTL file name and the indication ^ ^ ^ ^ 1 隹 以 以 手 手 体积 体积 TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL 不过 不过 不过 不过 不过 不过 不过 不过 不过 不过 不过 不过 不过 不过 不过 不过 不过 不过 不过 不过 不过 不过The screen display is displayed. The design window 27 is - the surface, which can be displayed on the semiconductor integrated circuit according to the received data from the test device i.

DmDesb fQr Testability: The area increase rate of the bulk circuit when testing the simplified design. In addition, if you want to implement the RTL name and indicate it. The pick-up window 28 is a screen for wishing to calculate the instruction to use each of the pick-up services. + The defective idle mapping window 29 is a screen for displaying the position of the defective pole on the wafer. Figure 3 is a table showing an example of the specifications of each test machine. This table is stored in the memory unit U (refer to the old one) and shows the specifications of each test machine at the highest operating frequency. Number of feet 4 Figure 4 shows the configuration of the 妓通美本 in various types of test machines. As shown in FIG. 4, the tester paste is configured to include a power supply unit for supplying a power supply voltage to the semiconductor integrated circuit L of the object. 〇ι pairs 2036-7232-PF 12 1363185 The semiconductor integrated circuit L is in turn. λ彳_^ station - a driver 302 that invades the editor input 6谠, a comparator 303 that compares the signal output from the output of the semiconductor integrated circuit, the output of the dice, and an expected value, and generates an input to the semiconductor integrated body. The test data generator of the body bar circuit L and the expected value of the pattern generator 3〇4, the timing generator 3G5 for generating the timing of the signal input from the wheel main body and the input to the rich volume body circuit, each of which is tested by a program The controller 3〇6 for controlling, the DC test circuit 3〇7 for performing DC test such as (4) level detection of the output pin. In addition, the power supply unit 301 and the DC test circuit 3〇7 are similar to the test program, and are not different for each test machine. In addition, as a technique for measuring the semiconductor integrated circuit, the change is unnecessary, and the material can be passed. The code. Figure 5 shows an example of the test machine language TL. In this test machine, there are several test machine resources in the test machine code 5Q (test machine operation data including parameters required for the test machine operation) and support for each c language function form 5 2 When the test machine resource is the device power supply 51, the c language function form 52 is "VS {unit number, applied voltage, f voltage range, measured current range upper limit clamp current, lower limit clamp current}". In this case, if you want to use the tester language and enter the parameters used for the test of the tester, you can enter the parameters such as the number of cells (unit number of the power supply) at the position where it is displayed. If it is not input, the preset parameters specified by the semiconductor integrated circuit development support system are input, so the engineer who designs the test program does not need to know all the parameters. The same is true for other tester resources. Figure 6(a) is a schematic diagram showing a semiconductor integrated circuit in the form of RTL. Between the input terminal 68 and the output terminal 69 of the semiconductor integrated circuit L, 2036-7232-PF 13 3 is 3185. The combination circuit 6 having both the logical operation function and the plurality of flip-flops (FF) 61 interacts. The combined circuit lines 65 (g in the figure, the other lines are also the same) are connected, and all the flip-flops 61 are connected by the time base 66. With this configuration, the flip-flop 61 can be synchronized in the semiconductor integrated circuit, the signal input from the input terminal 68 can be processed in a good order, and the signal can be output from the output terminal 69. (b) is a pattern diagram showing the case of adding & multiplexer _ (MUX) in various flip-flops 61 when the semiconductor integrated circuit L shown in Fig. 6(a) uses the SCAN technique. . One multiplexer 62 is added to one flip-flop 61. The multiplexer 62 is composed of three gates, a gate 621, 622 and an OR gate 623. The test circuit line 63, the SCAN circuit line 64, and the combined circuit line 65 are connected in the manner shown in the figure. Thereby, in the semiconductor integrated circuit of Fig. 6(a), the respective flip-flops 61 can be interlocked to operate in cooperation, and the position of the defective interpole can be found during the test. In addition, the details of this SCAN technology are described in the special open bulletin. Figure 7 shows the construction of the shuttle service wafer. Enlarge the (10) part of the large wafer. In the enlarged view of Fig. 71, there are three types of "wafer sharing" (Α wafer, etc.), 5_1 mm (U #, β wafer, etc.), and -m (C wafer, etc.). In recent years, the production of semiconductor integrated circuits has progressed to miniaturization, and high-tech devices and multilayer wiring have been used. Therefore, the price has become very high. Therefore, the shuttle service for fabricating a plurality of semiconductor integrated circuits on the same wafer can effectively reduce the manufacturing cost of the semiconductor integrated circuit. 2036-7232-PF 14 1363185 The above description of the structure of the semiconductor integrated circuit development support system 1000 is completed. Next, the operation will be described with reference to Figs. 8 to 14 (please refer to Fig. 1 as appropriate). . Fig. 8 is a flow chart showing the overall operation flow of the semiconductor integrated circuit development support system 100. First, the test-test company 1 uses the control device 1 to disclose a web page (Hp) of the introduction of the tester for testing the semiconductor power supply circuit (step S8〇1). The circuit design company 2 uses the terminal device 20 to fabricate circuit design data related to the pre-fabricated volume body circuit (step S8〇2), and according to the circuit design data, commissions the wafer fabrication company 3 to fabricate the wafer, in other words, This information is transmitted to the terminal device 3 of the wafer fabrication company 3 (step S8〇3). Next, Circuit Design Company 2 can use the terminal device 2 to search the Internet to find the test machine used to test the pre-made semiconductor integrated circuit, enter the test company 1 website, and use the interactive editor through the Internet. . In addition, an interactive editor can be downloaded from the control device 10 (step s8〇4). In addition, you can download other test programs even without an interactive editor. Also, when you enter the test company! In the case of the website, authentication is required, and the circuit company 2 can use the environment by the authentication window 22 (see (9)) of the display unit 21, the user name and the secret sound. By this, the security level. The display department = the design company 2 uses the terminal farm 2 〇 ' - the aspect refers to the horse · interactive editing „. The surface is edited by the interactive editor window 23 (refer to the second figure) using the work 'self' another aspect Circuit design information, production and use

2036-7232-PF 15 丄: To write the test program for the semiconductor integrated circuit test project, and to make it in any form of T:STiL (step (4) (6), transfer the test program and pattern to the test company i (4) _. In step _6, using the test pattern window Erzhao also selects and transmits from the four in the form of a pattern file. Sub-2 = interactive editor made the test program based on electricity:: ten The narrative mode code written by the technique has a feature that can easily recognize the meaning of the command from the valley of the program. In step S8°7, 'in the test company 1. Here, the processing unit 15 of the control device 10 comes from The circuit design shows the test pattern of the rate mode. ' Then' pre-extracts the hardware that is stored in the control device to extract the timing signal from the test pattern by the speed or specification required for the test (hereinafter referred to as Further, the length of each pattern required for the test can be extracted on the use hardware of the pattern generator, etc. In the case of extracting the timing resource, the processing unit 15 analyzes the whole (four) by trying Any part of it (for example, 1%) extracts the required data. In the second 4th of the RTL synchronization design, the circuit design data related to the 4 patterns can be used by a few percent to tens of percent. The analysis to ensure the necessary information is obtained 'so, in this case - part of the analysis. After j, it takes a lot of time and expense to analyze the entire test pattern, but the right can go into part of the analysis, to the test company 1 It can be said that it can achieve a very labor-saving effect. It-person, test company 1 uses the control device ίο to search (extract) the usable tester, and calculate the test cost of each test machine (step S808: relevant

2036-7232-PF 16 Section 1363185 will be described later in the figure ίο). In addition, 'in step S808', if DFT is used, a cheaper test machine can be extracted to reduce the test cost. In addition, the area increase rate of the cymbal can be calculated by using DFT at the same time, and the information is proposed to circuit design company 2, The details will be described later in Figure 11. Further, in the case of step S808, the case where the test cost is calculated when the shuttle service is used will be described later in Fig. 12 and Fig. 13. Next, the test company 1 transmits the test cost of the usable test machine and each test machine to the terminal device 2 of the circuit design company 2 using the control device 1 (step S809). After receiving the data, the circuit design company 2 displays the received tester and each test cost on the display unit 21 by the terminal device 20 (see the browsing window 25 of Fig. 2). When the circuit design company 2 wishes to perform the virtual test, the terminal device 20 is used to specify the circuit design data UTL file name through the virtual test window 26 of the display unit 21, and the virtual test item is checked and transmitted to the control device 1 Thereby, the test company is commissioned to perform the virtual test (step S8). The test company 1 uses the control device 10 to execute a virtual test by the processing unit 15 based on the test program, the test pattern, and the circuit design data, and transmits the result to the terminal device 20 of the circuit design company 2 (step 811). By means of the virtual test, it is found that the test pattern, timing setting, etc. of each test machine cannot be applied. After receiving the result, the circuit design company 2 can appropriately correct the test program, test pattern, and the like. In addition, when the logic function of the semiconductor integrated circuit is subjected to the virtual test 2036-7232-PF 17, the detection should be performed in a rate mode and the pattern generation method is called a time-driven mode or a time event mode ==. . Specifically, the time-based mode logic changes the point m 吟 事件 event mode hunting by monitoring the doubled point to take the timing information and sample of the change point, in contrast, the rate mode is determined by the pattern Information to produce a pattern. In the case of the pattern, the test pattern that can be used in the figure can be shortened even if it is not the entire pattern, and only a random knife (a few hundred to a few hundred percent) can be used. The time of the door increases efficiency. The combination of the leeks and the people's circuit design company 2 uses the final test machine, by the value of ... ^ ^ device 2 selected for the actual transfer to the test company 1 control f set 委托 ^ commission test ( Step S812). t device 10, then, the test company 丨 according to the need, ^ test machine action program and mention ...:: (10)% conversion to test S813) 〇 供 供 供 供 供 供 供 供 ( ( ( ( Production company 3 receives from the circuit = commission (step S_, making the wafer (step _, then = round again to test 5 company 1 (step S81 5).," Then, test company! can use the control device 1 〇, test The test (step _) is performed by transferring the test result to the terminal device 20 by converting the test pattern into 5 steps ▲, ▲ and stem, flying, and measuring the circuit design data. 』Device 1〇' Finally, on the control device 10, test machine resources, test results, etc.

2036-7232-PF 18 1363185 Various information is registered in the memory unit 14 (Tianyi + Times, Xiangxiang 6818). The test company 1 can use the information to control the frequency of the H-type machine, the number of pins, the length of the pattern, the timing of the negative source, etc. related to f % π ▲ 丄 \ ^ Λ, off the circuit s ten companies in the desired direction, appropriate and future purchase of test machines, etc., and the development of low-cost test machines, etc. Figure 9 is a machine diagram, shown in the step of Figure 8 extraction In the control device 10, the processing unit 15 inputs a test program, that is, a test program that is received from the terminal device 2 of the circuit design company 2 (refer to the interactive editor window of FIG. 2). M) is stored in the memory unit 14 (step S901). Processing: 卩15 starts from the number of lines of the test program n = ( (step sg 〇 2), searches for the 丨 line with n = n + l (step S9 〇 3) To determine whether the line is a pin code, that is, whether the line is a program related to the number of pins (step § 904). When the behavior is Pi η code (Yes in step S9 04), processing The unit 15 extracts the value of the number of pins from the Pin code and stores it in the storage unit 14 (step S905). • When the line is not When the pin code is No (No in step S904), the processing unit 15 proceeds to step S906 to determine whether the line is a VS code, that is, whether the line is a program related to the power of the device. When the behavior is VS code When it is Yes (Yes in step S906), the processing unit 15 extracts the value of the number of power sources from the VS code in the memory unit 1 & (step S907). Further, here, only 117 of the test machine resources are extracted. And store the value of the number of pins and the number of power supplies, but in fact also extract and store other tests

2036-7232-PF 19 1363185

The value of the test resource. The processing unit (4) breaks whether the line is the last line (step (8) if not: take the back line (10)), returns to step (10), and repeats the processing to the last line (Yes), and ends the processing. Thus, the test machine can be extracted from the resource m on the control device: 1 is a flowchart showing the process of searching for the test machine and calculating the test cost in the step 8 of Fig. 8. In the control device 10, the processing unit 15 inputs the test machine resource I, that is, the test machine resource and the timing resource extracted in the step leakage of Fig. 8 are stored in the storage unit 14 (step S1 01). The processing unit 15 acquires the test machine information from the storage unit 14, that is, acquires the data related to the test machine specifications (see FIG. 3) (step 2). - The processing unit 15 starts from the model 11 = 0 of the test machine (step s1 〇〇 3), searches for the specification of the first test machine with (4) + 1 (step training (4), and judges whether the values of the test machine source meet the test. The condition of the test machine resource (test machine data) of the machine (step S1 005). If the processing unit 15 satisfies the condition (Yes) in step 51〇〇5, the test machine is not displayed in the output unit (a test machine that can be used) (Step S1〇〇6), if the condition (No) is not satisfied, the process proceeds to step S1 007. In step S1007, the processing unit 丨5 determines whether or not all the test machines of the test machine are processed or not, and if not, (N) Then, the process returns to step S1004, and the processing is repeated. If the result is (Yes), the test cost of each tester that can be used is calculated and displayed on the output unit 13 (step S1008). 2〇36*7232-pf 20 When you have enough test costs, you can first consider the time to write the test program. ·: Class: The test needs to be determined by the type of test machine used. The test takes time to multiply the cost of each test machine. Can be determined by the calculation of the circle / second, etc.). _ Early use price (10) day, J type machine early time, your department 15 from the storage, _ grid can also be processed by the purchase price, make the F1 w) table towel test machine 4, repayment period As for personnel costs, etc., the test cost of each test machine that can be used can be searched (selected). The dissipative satr map is a flowchart ’ shows the processing when calculating the wafer area increase rate of the DFT described in Fig. 6(b). In the control device 10, the processing unit 15 inputs the RTL, that is, stores the circuit design data in the memory unit 14 (step S1101). Next, the processing unit 15 performs logical synthesis 'that is, a logic circuit that converts it into circuit design data in the form of RTL (step S1I02). Next, the processing unit 15 counts the total number of idle poles including the flip-flops in the logic circuit (step S1103), and counts the number of flip-flops therein (step S1104). The processing unit 15 calculates at m=3xn. The number of gates m used in the multiplexer (Μυχ) (step sii 〇 5). As described in the 6th (b) diagram, when using the DFT of the scan technique, '3 multiplexers are added to one flip-flop, so the number of gates can be obtained by m=3xn^ The last 'processing section The area increase rate (%) of the wafer of the DFT is calculated by m/N. 100 (step S1106). 2036-7232-PF 21 1363185 λ This increases the rate. The area of the wafer when the DFT is used can be calculated on the control device ίο. When the DFT using the technology is used, the cost of the wafer area is increased as the wafer area is increased, but the test can be reduced: Counting or reducing the test frequency, so you can search for (extract) a cheap test machine at the step of Figure 8, which can be used as a test to reduce the test cost. Therefore, in the step 12 of the eighth drawing, even if the knowledge related to the DFT is insufficient, the circuit design company 2 can increase the cost of the wafer as the wafer area increases, and the test cost decreases. The fact of the matter, to properly determine whether DFT should be used. Further, if the circuit design company 2 wishes to use the DFT, the design of the DFT can be input through the design window 27 (see FIG. 2) of the display unit 21, and transmitted to the control device 1 of the test company i. Fig. 12 is a flow chart showing the process of calculating the test cost when using the shuttle service. In addition, the number of samples referred to below refers to the number of wafers to be used for calculating the unit area by division. For example, in FIG. 7, when the unit area is set to 25 mm 2 , the A wafer, the B wafer, the c wafer, and The number of samples of the D wafer is 4, 2, 1, and 2, respectively. In addition, the process of calculating the test cost when using the pick-up service performed in FIG. 12 corresponds to the process of calculating the test cost in step S8 08 of FIG. 8, in which case the circuit design company from FIG. 8 2 The wafer creation request from the wafer fabrication company 3 (step S803) is performed at a time point after step S808. First, the circuit design company 2 selects the shuttle device using the terminal device 20 (refer to 2036-7232-PF 22 13*63185

A. The data is transmitted to the pick-up window 28) of the test company's control chart 2, and the device 10 is manufactured. Next, in the control device 1 of the test company, the processing unit 15 inputs the sample number of the wafer (the shuttle s) from the terminal device 2 () of the circuit design company 2 as the wafer of the stomach image to the memory unit] 4 (step s〗 2〇l). Next, the processing unit 15 refers to the database related to the pick-up service stored in the storage unit 14, and determines whether or not the number of samples is vacated by the pick-up device S (S1202). - • # When the number of samples above the pick-up is not vacated ((4) in step S1202, the processing unit 15 ends the processing 'When the number of samples on the pick-up 5 is vacated (Yes in step 51 202), The crystal moon is registered in the database related to the pick-up service of the memory unit η (step sl2〇3). By this registration, the vacant area of the feeder S is reduced. Next, the processing unit 15 calculates the test of the entire pick-up unit 8. Cost (step SI 204··detailed in detail in Figure 13), divide the test cost of the entire pick-up S by the total number of samples, calculate the test cost per unit area, by multiplying the value by The number of samples of the t chip, # test cost of the wafer (step S1 205). The test cost can be calculated on the control device 10, and the 13th picture of the wafer on the shuttle s is a flow chart showing the calculation The processing of the test cost of the entire shuttle S in step 312 4 of Fig. 12. First, the processing unit 15 sets the number M of test machines used in the test of the shuttle S to U step S13G1). 2036-7232-PF 23 Ι3ύ3185 Next, the processing unit 15 sets the product number of the wafer, which is the pick-up product number, that is, the wafer produced by the pick-up device, to 〇 (step S1302), and sets the total test time to 0 (step S1303). . The receiver' processing unit 15 adds ι to the value of the pick-up product number by D-D+1 (step S1304), and refers to the memory unit 14, and uses the test machine for the wafer of the pick-up product number as the test for the pick-up machine S. The machine determines whether it has been logged in (step S1 305). If the test machine has been registered (Yes in step S1305), it is not necessary to change the number of models of the test machine used in the shuttle S, and if the test machine has not been registered (No in step S1 305) The processing unit 15 registers the test machine as a test machine used in the shuttle s in the storage unit 14 (step S1 306). Thereby, the number of test machines used in the shuttle s is increased. One, so the value of Μ can be updated by M=M+1 (step S1307). Next, the processing unit 15 reads the test=inter-t of each sample number from the memory unit 14 (step S1308), and updates the T by the number of T=T + tx samples (the number of samples of the wafer tested on the test machine). Value (step S1309). • Then the 'processing unit 15 determines whether the wafer is the last product (step s1310), if not the last product (N〇), returns to step si3〇4, and repeats the second right to the last product (Yes), and exchanges the working time with TD= (Operation time required for one-time test machine exchange) χ (i) Calculate the total operation exchange time, that is, the total time required to exchange the test machine (step si3H). Thereafter, the processing unit 15W (T + TD) X unit price (test cost per unit time) outputs the test cost of the entire shuttle S (step S131 2). In addition, the unit price varies depending on each test machine, and the test cost of the entire shuttle (4) can be calculated. 2036-7232-ET 24 13153185 In this case, the test cost of the shuttle s can be calculated on the control device 10 and then the same type of bobbin in the same shuttle can be used. The type of measuring machine used, the more (the number of models), the lower the test cost of the entire pick-up 3, the test of each wafer is too close! And then, with the processing of Figure a and Brother 13, the test of the lower test cost of the eight people of the ridiculous ice blaze 〆 — — — — — — — — — — — — — — — — — — — — — — — — — — — — The homework will also be more efficient. “In addition, by testing on the shuttle, the wafer can be increased (the ratio of good products). The hand J2 is a flowchart showing the processing when making a poor closed-pole mapping. The :::: mapping' means The defective portion displayed on the wafer (the defective open pole map is used as the test result in step S817 of Fig. 8). The processing unit of the control device 10] ^In the water P 5, the step 58 from the 8th circle is input, and the 6th part of the method is also used to detect the deficiencies, nlAr^mc (bad pattern), that is, to store it in the hidden portion 14 ( Step S1401) The processing unit 15 refers to the database related to the pole stored on the wafer of the memory unit 14, that is, the gate gate library (step S1402), and finds the bad gate (step 514〇3)» In addition, +031> In the gate of the gate library, the bad data and the bad gate are related to β. The circuit design of the wafer stored in the memory unit 14 is obtained. 4), find the position of the poor opening (step si4 〇 5). Then, the processing unit 15 determines whether it is the last Bad information, that is,

2036-7232-PF 25 The king's non-re-investment is coarse. 0 Bad information is second (step is called (6). If it is not the last one, return step (4) 401, repeat the processing, if it is the last bad information (Yes), end The test VIII I makes a bad gate mapping, and in step SS1 7 of FIG. 8, the control device 10 of the singapore 401 transmits the bad gate map to the terminal of the circuit setting = division 2, at the terminal The display unit (4) of the device 2Q indicates the non-polar mapping (refer to the defective inter-pole mapping window 29 of Fig. 2). Further, the =-polar mapping can be created on each wafer, or it can be created over the entire 0. Then, Circuit Design Company 2 can observe the bad gate mapping and find out: it is the cause of the problem somewhere in the wafer fabrication process (foreign matter, etc.), by transmitting this reason to the crystal. In the production company 3, it is possible to effectively improve 'increasing the yield (the ratio of the good products) in the production of the semiconductor integrated circuit. The above description of the embodiment is completed, however, the embodiment of the present invention is not limited thereto. The present invention can be applied not only to LSI, etc. The semiconductor integrated circuit can also be applied to various devices using semiconductor technology such as memory. In addition, in the DFT, not only SCAN technology but also other technologies such as BIST (Built~In Self-Test) can be used. When each device transmits and receives various data through the Internet 4, not only a password or the like, but also a coding level can be used to improve the security level. Further, the specific structure of the hardware, the process diagram, and the like can be omitted from the present invention. 2036-7232-PF 26 13153185 m [Simple diagram of the diagram] The overall structure of the semiconductor integrated circuit development support system. The picture shows the display in the terminal device 2〇 of the circuit design company 2. Part (4) Dong's appearance is not typical. Figure 3 is a table showing the specifications of each test machine. Figure 4 shows the common basic structure of the test machine in various ways. Figure 5 shows the test An example of the machine language TL. Fig. 6(a) is a schematic diagram showing a semi-derivative volume circuit in the form of RTL. (b) is a mode circle showing when the corpus is not in the () · Make In the case of SCAN technology, in the case of various positive and negative 4, you can add additional multiplexers (Μυχ). Figure 7 shows the structure of the shuttle service wafer. Figure 8 is a flow chart showing the semiconductor product. The overall operation flow of the system 1_. The development diagram is shown in the flowchart, showing the processing when extracting the test machine resources. Figure 10 is a flow chart showing the search engine in Figure 8 and calculating the test cost. Fig. 11 is a flowchart showing the processing when calculating the wafer area increase rate of the DFT using the SCAN technique. Fig. 12 is a flowchart showing the processing for calculating the test cost when the shuttle service is used. Fig. 13 is a flowchart showing the process of calculating the test cost of the entire boarding machine S in step S1204 of Fig. 12. 2036-7232-PF 27 1563185 Figure 14 is a flow chart showing the processing when creating a bad gate map. [Main component symbol description] 1 Test company 2 circuit design company 3 wafer fabrication company 4 network 1 0 control device 1' 4 memory unit 15 processing unit 20 terminal device

2036—7232-PF 28

Claims (1)

1363185 +, the scope of application for patents: a semiconductor integrated circuit control device 'to be tested by the machine; and the # terminal circuit test of the trusted terminal device, the above _ 舆 the above control device connection, 5 owned and Through the Internet, it is characterized in that: the control device has a memory unit and a processing unit, a middle memory system, a test machine language, a test machine language program, and a test machine data in the above test, which is used on the above test machine. The second test converts the permissible range of the necessary action data of the reference machine, and the test includes the above test and the test contains the necessary parameters; a plurality of the above test machines are related to the processing. P is transmitted to the terminal device in accordance with the language program from the terminal farm test machine, and the test is performed by the mosquito tester, and any part of the test program is extracted according to the test machine language program and extracted (4) H 'analysis The action data of the M, L ± J mouth machine is used to extract the usable test machine by comparing the action data and storing the data. The above-mentioned test machine of U / 2. The semiconductor integrated circuit research and development support system of the scope of the patent application of the second aspect of the invention, wherein the above memory unit further stores the unit time use price of each test machine. Any part of the above test program is converted into an action program of the above test machine, and according to the action, it is estimated that the test time of each of the test machines that can be used requires time, according to the above 2036-7232-PF 29 13*63185 s = test time and the above-mentioned unit price calculated in the above-mentioned memory unit = the test cost of the test machine that can be used by the parent, and the test cost of the above-mentioned test machine and each test machine can be transmitted. The semiconductor product of the second item of the second aspect of the invention, wherein: the memory unit further stores an arithmetic expression in which the integrated circuit is used when the simple material is used in the semiconductor integrated circuit. When the area is increased, the processing unit calculates the increased area when the test is simplified by using the above-described calculation formula stored in the above-described test, and the test is simple. Above may be used in the design; and testing the machine to the formula έ too v spleen μ, +, said device 1. W and transfer the above-mentioned increase % area to the above-mentioned terminal 4. As for the semiconductor dragon circuit research and development support of the third item of the patent scope, the above-mentioned arithmetic expression is the flip-flop in the above semiconductor integrated circuit. Each time three idle poles are added to calculate the above formula for increasing the area. 5. In the middle of the semiconductor integrated circuit research and development support in the third paragraph of the patent application, the above-mentioned processing unit proceeds to find the position of the bad gate from the data generated when testing the above-mentioned test machine, ".4 The poor gate mapping of the position of the defective pole is transmitted to the terminal device. ^ 6. A semiconductor integrated circuit development support system, including a control device, and a test machine for testing the semiconductor integrated circuit And the w and the end of the "set, the above-mentioned test of the commission (4) and through the control device;; Intersection, Zhou Road 2036-7232-PF 30, 5 Guyang round on the production of a variety of semiconductors The integrated electric machine is characterized in that: the control device has a memory unit and a processing unit; the memory unit stores a test machine, and the parameters of the test machine data and the calculation parameters are determined by The conversion must be used on the above test machine, the action of a test machine. The operation of the test machine is used to reduce the amount of the above-mentioned test, and the test contains 〃, and a plurality of the above test machines. The unit time of the machine is such that the test is performed according to each of the above tests. It takes time to test the plurality of semiconductors on the plurality of wafers, and the test cost of the above-mentioned equal volume circuit is calculated; The processing unit performs the test from the test device according to the request from the test machine, and the device is sent to the terminal for charging according to the test. When the program's tone is long, the data is analyzed by comparing the action information of the #^aa machine, ... compared to the action data and stored in the data, extracting the above test machine 屮π # « In the above-mentioned wafers stored in the memory section, the test cost of the circuit will be available in the device. The K machine and its test cost are transmitted to the above terminal 2036-7232-pp 31