TWI363257B - - Google Patents

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Publication number
TWI363257B
TWI363257B TW95123119A TW95123119A TWI363257B TW I363257 B TWI363257 B TW I363257B TW 95123119 A TW95123119 A TW 95123119A TW 95123119 A TW95123119 A TW 95123119A TW I363257 B TWI363257 B TW I363257B
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TW
Taiwan
Prior art keywords
tester
test
terminal
semiconductor integrated
integrated circuit
Prior art date
Application number
TW95123119A
Other languages
Chinese (zh)
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TW200712810A (en
Inventor
Satoh Masayuki
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority to PCT/JP2005/011798 priority Critical patent/WO2007000806A1/en
Application filed filed Critical
Publication of TW200712810A publication Critical patent/TW200712810A/en
Application granted granted Critical
Publication of TWI363257B publication Critical patent/TWI363257B/zh

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318314Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuit
    • G01R31/31903Tester hardware, i.e. output processing circuit tester configuration
    • G01R31/31912Tester/user interface

Description

1363257 - IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a support system accompanying the development of a semiconductor integrated circuit. [Prior Art], In recent years, with the development of semiconductor technology, semiconductor integrated circuits such as LSi (Large Scale φ intergratlon) have become more and more diverse, and the efficiency of their development is also important. The steps of the semiconductor integrated circuit, the steps from design to manufacture are generally as follows. When developing a volumetric body, first, the system is set up. Ten is the design of the action level centered on this action. Next, the logic design of the logic gate level and the circuit design of the logic design are performed at the component level. Then, a photomask is produced and transferred to a wafer fabrication process called a front process, which uses the photomask to form a semiconductor integrated circuit on the wafer. • Afterwards, test the wafers manufactured in the previous process with a probe test. • Determine whether the wafer is divided into wafers (semiconductor integrated circuits) and screen out the probes. Good wafers' are assembled for packaging. 1. The assembly is debugged by characterization, and when its characteristics are identified as meeting the established value, it is transferred to mass production after the final test provided by the test program according to the final test specification. In these two tests, a device called a tester was used. The tester is an expensive device with a value of tens of millions of rounds to hundreds of millions of rounds, using 2036-8152-pp; the cost of Ahddub 5 iD/ is also very high. 'The choice of tester is for the latter. An important question is 0 phase: , · 4 oil test, tester body, controller, etc. Month: The input and output terminals of the 4-type head and the semiconductor integrated circuit to be tested are connected to a plurality of dielectric panels called pin electronic products, in which the pin electronics output signals to the semiconductor integrated circuit. As the architecture of the S-type device, there are a plurality of pins sharing the shared resource mode of the timing generating circuit and the pattern generating circuit, and each pin has a timing generating circuit U pattern generating circuit. The method of squatting, each pin has a timing generating circuit and a pattern generating circuit (hereinafter referred to as "all-by-pin method"). In the past, the tester of the shared resource method was heavily used, and the recent 'pin-by-pin tester' began to receive a lot of money. It is predicted that the tester in the future will be heavily used. Each of the testers has a power supply for supplying power to the semiconductor integrated circuit, a measurement system for evaluating DC (Direct Current) characteristics of the input and output terminals of the semiconductor integrated circuit, and a DAC for generating a Dc level for supplying the semiconductor integrated circuit ( Digital
Analog Converter) converters, etc. These testers are controlled by a test program that operates under the OSCOperating System of the CPU (Central Processing Unit). Such test programs are written in a so-called tester language. The tester language generally varies with the tester architecture. As such a tester language, a combined language for direct control of hardware and called machine language appeared. In contrast to this, in order to pay for the procedural §§ §, someone came up with a tester control 2036-8152-PF; Ahddub 6 1363257 language, and also began to use FORTRAN form and BASIC form. Furthermore, pascal as a structural language has also been widely used, but now c language has become mainstream. Moreover, in recent years, in the field of a half-body volume circuit, a circuit design company called a fabless company has appeared, and an evaluation tool has been provided to evaluate a semiconductor integrated circuit designed by a circuit design company on a computer such as a workstation. A company that functions as EDA (Automatic Design Engineering), a test program that converts a test program related to a volumetric circuit designed by a circuit design company into a testable program, and is called a test house test company. The circuit design data designed by the circuit design company, the photomask manufacturing company that manufactures the mask, the photomask manufacturing circuit that manufactures the photomask, and is called the wafer fabrication company, the use test company. The testers that are produced by the test program contract test are called test factory companies, etc. These professional companies have a division of labor in the development of semiconductor integrated circuits: potential. Therefore, in Patent Document 4, a technique relating to a business model is disclosed, that is, a test company first proposes a tester language to an EDA vendor, a circuit design company, and a company, and then, an EDA vendor provides a circuit design: a program for performing a logic simulation of a semiconductor integrated circuit, after which the circuit design company designs a semiconductor integrated circuit including a desired logic function and verifies the logic function of the virtual tester (a tester that exhibits a tester function on a computer), and then 'Transfer the test program made in the tester language to the test company via the Internet. Then, the test company selects the tester that can be used according to the test program. 2036-8152-PF; Ahddub 7 1363257 [Patent Document 1] JP-A-2003-270305 (paragraphs 0033 to 0035, FIG. 6) [Explanation] [Problems to be Solved by the Invention] However, in the technique of Patent Document 1, In the stage before the selection of the tester, there are many professional companies involved, so the work becomes complicated or inefficient, so there are problems that cost a lot. Therefore, the object of the present invention is to provide a support system which is related to the development of a semiconductor integrated circuit including the selection of a tester and the like. [Means for Solving the Problem] In order to solve the above problems, the semiconductor integrated circuit development support system of the present invention includes a control device owned by a trust company and a domain test commissioner who is testing the semiconductor integrated circuit using a tester. And the terminal device connected to the control device via the network, wherein the control device includes a memory unit and a processing unit. The memory unit stores a parameter that specifies and converts parameters required for the test, and then uses the tester in the tester. a program, a test beta data included in an allowable range of the action data of the tester related to the plurality of testers and including the above-mentioned parameters required for the test, the processing unit according to the request from the terminal device The tester language program is transmitted to the above terminal, U., and receives the test program 6 2036-8152-PF created according to the tester language program 1 from the above-mentioned terminal device; Ahddub 1363257 and then 'analyzes any part of the test program and extracts The action data of the above tester, by comparing the action data The above tester data stored in the above-mentioned memory unit is used to extract a usable tester. [Effect of the Invention] The present invention indicates that an effective support system relating to the development of a semiconductor bulk circuit including a tester selection or the like can be realized.
[Embodiment] Hereinafter, the semiconductor integrated circuit development support system of the present invention will be described with reference to the drawings. First, the configuration of the semiconductor integrated circuit development support system will be described with reference to FIGS. 1 is a diagram showing the overall structure of the semiconductor money circuit development support system. The volumetric circuit development support system includes the test diagram. The semi-company (tested trustee company, circuit design company (testing company) 2 and wafer fabrication company 3') are connected to each other by a network such as the Internet. In addition, the circuit design company 2 and the wafer fabrication company 3 can only be shown in the figure, but they can also be plural. In addition, although not specifically illustrated, in the development of the semiconductor integrated circuit, it is possible to work with the mask manufacturing company and the fixture manufacturing company. The test company! In the semiconductor integrated circuit (4), the device 10', although not shown, the dry diameter system ^, . ^ w, η ^ is associated with the money machine (four) tester. A computer device such as a personal computer includes a communication unit 11 for communicating with an external device 2036-8152-PF, Ahddub 9 , a wheel-in portion 12 composed of a keyboard or the like and inputting data, and a display unit. The output unit 13 that outputs the data, the memory unit 14 that stores various materials, and the cpu (Centrai)
A processing unit π configured to perform various kinds of arithmetic processing, such as a unit, and a memory unit 6 as a calculation area of the processing unit 15. The circuit design company 2 includes the terminal device 20 when performing circuit design of the semiconductor integrated circuit. The terminal device 2 is a computer device such as a personal computer, and has a display unit 21 that displays a screen. The wafer fabrication company 3 manufactures a wafer as a basis for a semiconductor circuit, and includes a terminal device that is also a computer device such as a personal computer. Fig. 2 is a screen display example of the display unit 21 in the terminal device 2 of the circuit design company 2 (please refer to the figure for reference). Here, the outline of each screen (view window) will be described, and details will be described later. Further, in Fig. 2, the respective screens (windows) are simultaneously displayed, and are actually displayed separately. Further, even if it is not specifically indicated, all of the communication φ objects of the terminal device 2 are the control device 1 〇. The screen for inputting the authentication user name and password for communication to the user of the terminal device 20 is also referred to as 22. The interactive editor window 23 is an interactive editor (an editor made in a tester language) disclosed by the test company j, a parameter (a value of an applied voltage, etc.) required for inputting a test of the semiconductor integrated circuit, and the like. Create a screen of the test program. In the interactive editor's use of C language function syntax, for the tester operated by C language in the tester side prepared c language 2〇36-8152-PF; Ahddub 10 1363257 function definition 'Can be used on this tester without conversion. The interactive editor is stored in the memory unit 14 of the control unit 1〇. Further, the test program created by the interactive editor describes the required parameters. Therefore, the tester operating in a language other than the C language has a feature that it is easy to perform program conversion. Thus, by using this interactive editor, it is also possible to create an appropriate test program for those who know less about the tester. The test pattern window 24 is a screen for the circuit design company 2 to input a test pattern for testing the semi-conductor volume circuit. Here, the test pattern refers to a pattern in which the set values of the respective parameters at the time of simulation are expressed in time series in order to examine the semiconductor integrated circuit. In the circuit design company 2, a test pattern is created by extracting the timing information and logic values of the change points by monitoring the logic change points and describing the time-driven manner of the test pattern. However, in the design stage, the time-driven mode is useful. Before that, there was a problem that the tester could not be read. Therefore, during a certain period of time, it is necessary to separate the test pattern and convert it into a rate mode in which the test pattern is described as 1/〇 of the test pattern, so that the tester becomes readable. Therefore, in the present application, the circuit design company 2 inputs the test pattern in a time-driven manner and converts it into a code rate mode at the test company. Thereby, the test pattern of the combined code rate method and the semiconductor integrated circuit data of the RTL described later can be tested on the computer, and the result can be transmitted to the circuit design through the Internet or the like. Company 2, therefore, can realize an efficient support system related to the development of semiconductor integrated circuits. 2036-8152-PF; Ahddub 1363257 • In the following description, the test pattern indicated by the time drive method may be simply referred to as a "pattern" as a difference. • Go back to the description in Figure 2 'Test Pattern Window 24 for Circuit Design Company 2 Wheeling Pattern Name' to select the pattern form (Text, VCD (Value Change - Dump), WGLCWaveform Generation Language), STIL (Standard Test Interface Language) ), input the pattern of the pattern in a time-driven manner. The navigation window 2 5 displays a list of tests that can be used based on the data transmitted from the control device of the test company 1, the test cost when using each tester, and selects the actual tester by selecting a payment item. Picture. The virtual test window 2 6 is in the case of a virtual test (virtual test performed on a computer device) in the case of RTL (Regis ter Trans is ter
Logic: Direct type transistor logic circuit) A screen in which the indication φ is performed in accordance with the input of the rTL file name of the semiconductor integrated circuit when the semiconductor integrated circuit is described. Further, the semiconductor integrated circuit is premised on the RTL method. However, when other methods are used, there is a screen display in which the type is matched. The design window 27 is based on the data received from the control device of the test company 1 and displayed on the semiconductor integrated circuit using DFT (Design for
Testability: The area of the semiconductor integrated circuit at the time of testability designation and the screen for the indication with the input of the RTL file name when DFT is desired. The common reticle window 28 is a screen for performing the instruction when calculating the test cost by using the respective commissure masks. 2036-8152-PF; Ahddub 12 1363257 The bad logic gate mapping window 29 is a defective portion on the display wafer (bad The screen of the position of the logic gate). Figure 3 is a table showing an example of the specifications of each tester. This table is stored in the memory unit 14 (see Fig. 1) and is used to indicate the specifications of each tester such as the highest operating frequency and the number of bows. Figure 4 shows the basic structure common to testers of various modes. As shown in FIG. 4, the tester 300 is configured to include a power supply unit 3 for supplying a power supply voltage to the semiconductor integrated circuit L as a test object, and a driver for inputting a signal to an input terminal of the semiconductor integrated circuit L. Comparing the signal and the expected value signal outputted from the output terminal of the semiconductor integrated circuit L to the comparator 3〇3, the pattern generator 304 for generating the test data and the desired value input to the semiconductor integrated circuit 1, for generating an input to The timing generator 3〇5 for guiding the timing of the signal of the volume circuit L, the controller 306 for performing each control by the test program, the DC test circuit for performing the DC test such as the voltage level detection of the output pin 307. Further, the power supply unit 301 and the DC test circuit 3〇7 are similar to the test program, and are not different for the tester. Moreover, the technique for measuring the semiconductor integrated circuit L does not need to be changed, and a common code can be used. Figure 5 shows an example of the tester language TL. In this tester language, each tester resource in the tester code 50 (the action data of the tester in which the parameters required for the operation of the tester are included) corresponds to each of the c language function forms 52. For example, when the tester resource is component power supply 51, the C language function form 52 is "VS {unit number, voltage applied, current range measurement current is 2036-8152-Pp; Ahddub 13 1363257 upper limit 'box current lower limit} "." In this case, to use the tester language TL to input the parameters used for testing with the tester, the parameters such as the number of cells (unit number of the power supply) can be input to the position where they are displayed. If the preset parameters specified in the semiconductor integrated circuit development support system are not input, the producer who created the test program does not need to understand all the parameters. The same is true for other tester resources. Fig. 6(a) is a schematic view showing a semiconductor integrated circuit of the rTL method. In the semiconductor integrated circuit L, a combination circuit 65 that performs a predetermined logical operation between the input terminal 68 and the output terminal 69 and a plurality of flip-flops (FF) 61 are alternately combined (although One is connected, but the other lines are the same) to connect, and all the flip-flops 61 are connected by the clock line 66. With this configuration, in the semiconductor integrated circuit L, the signal input from the input terminal 68 can be processed in a good order in synchronization with the flip-flop 61, and the signal is output from the output terminal 69. Fig. 6(b) is a schematic view showing a state in which the multiplexer (MUX) 62 is attached to each of the flip-flops 61 when the SCAN technique is used in the semiconductor integrated circuit L shown in Fig. 6(a). A flip-flop 61 is attached to a multiplexer 62. The multiplexer 62 is composed of three logic gates, an AND logic gate 621, 622 and an OR logic gate 623. The test circuit line 63, the SCAN circuit line 64, and the combined circuit line 65 are connected as shown in the figure. By means of such a connection 'in the semiconductor integrated circuit L of FIG. 6(a), the respective flip-flops 61 can be linked together and linked, and 2036-8152-PF can be selected during the test; Ahddub 14 1363257 The position of the bad logic gate. In addition, the details of this SCAN technology are described in the special article of the Japanese Patent Publication No. 2003-1 49300. Figure 7 shows the structure of the reticle shared wafer. A magnified view 71 magnifies a portion of the wafer 70. In the enlarged view 71, the wafer has three types of 10 mm x 10 mm (A wafer or the like), 5 nnn x 10 mm (B wafer, D wafer, etc.), 5 nnnx 5 miii (C wafer, etc.). In recent years, the fabrication of semiconductor integrated circuits has developed a miniaturization process, which uses complicated devices, multiple layers of wiring, etc., and therefore becomes very expensive. Thus, the fabrication of a plurality of semiconductor integrated circuits on the same wafer can effectively reduce the fabrication cost of the semiconductor integrated circuit. The semiconductor integrated circuit development support system 丨000 has been described above with reference to the above description, and the operation will be described with reference to Fig. 8 to Fig. 7 (please refer to Fig. 1 as appropriate). Fig. 8 is a flowchart showing the overall operation flow related to the semiconductor integrated circuit development support system 1000. First, the test company 1 uses the control device to disclose a web page (HP) relating to the introduction of the tester used in the test of the semiconductor integrated circuit (step S801). The circuit design company 2 uses the terminal device 2 to fabricate circuit design data relating to the predetermined semiconductor body circuit (step S8〇2), according to the wafer '
2036-8152-PF; Ahddub road design data, commissioned by the wafer fabrication company 3, and the terminal device 30 of the production company 3 transmits the title of the subject. 1363257 Further, an interactive editor can be downloaded from the control device 10 for use. (Step S804). Alternatively, you can download additional test authoring tools without using an interactive editor. Further, when the web page of the test company 1 is entered, authentication is required, and the circuit design company 2 can input the user name and password through the authentication window 22 (see Fig. 2) of the display unit 21 to use this environment. In this way, the security level of information communication can be improved. Then, the circuit design company 2 uses the terminal device 20 to refer to the display unit 21' while using the interactive editor in the interactive editor window 23 (see FIG. 2) to test the semiconductor integrated circuit based on the circuit design data. The test program of the project, and the test program is produced in any form of text, VCD, WGL, STIL (step S805), and the test program and pattern are transmitted to the control device 10 of the test company 1 (step S806) e at step 6 In the test pattern window 24 (refer to FIG. 2), the form of the pattern file is also selected and transmitted from the four. In addition, the test program created by the interactive editor is a code based on the description of the electronic measurement technology, and has a feature that can easily recognize the meaning of the narrative from the description. In step S807, the test company 1 extracts the tester resources from the test program received from the circuit design company 2 through the processing unit 15' of the control device (the details are described in the following ninth figure). Further, the processing unit 15' of the control device i 产生 generates a test pattern of a code rate method from the pattern received from the circuit design company 2. Then, the hardware is extracted from the hardware stored in advance in the control device (hereinafter referred to as a time series resource), and the hardware can be obtained from the test pattern ^36-8152-PF; Ahddub 16 丄北3257 according to the measurement domain The required speed or specification produces a timing signal. Furthermore, the lengths of various patterns required for the test, etc., are extracted from the used hardware of the pattern generator. When the timing resource is extracted, the processing section 15 extracts the necessary data by analyzing all or any part (e.g., 10%) of the test pattern. In the test pattern related to the circuit design data designed in synchronization with RTL in recent years, by analyzing a few percent to a few tens of percent, it is guaranteed to obtain the required information 'so' in this case. Analysis. In addition, when analyzing all the test patterns, it takes a lot of time and expense. By only a part of the analysis, it is quite labor-saving for the test company 1. Next, the test company 1 searches for (extracts) the usable tester using the control device 10 to calculate the test cost of each tester (step S8〇8: details, which will be described later in the first drawing). In addition, in step S808, if DFT is used, a cheaper tester can be extracted to reduce the test cost, and at the same time, the wafer area increase rate caused by using the DFT can be calculated, and the circuit design company 2 prompts the information about the detail. , described in the eleventh figure below. 'In step S808, the calculation of the test cost after using the common-shaping mask is described in the following 12th and 13th drawings." Next, the test company 1 uses the control device 1 and the tester and each test to be used. The test cost of the device is transmitted to the terminal device 20 of the circuit design company 2 (step S809). After receiving the content, the circuit design company 2 displays the received usable tester and each test cost on the display unit 21 via the terminal device 20 (refer to 2036-8152-PF; Ahddub 17 1363257, FIG. 2, the navigation window 25 ). ψ When the circuit design company 2 wants to perform the virtual test, the terminal device 2 specifies the circuit design data (RTL file) name through the virtual test window 26 of the display unit 21, tickes the virtual test item, and transmits it to the control device. This 'commissioned test company 1 performs a virtual test (step S8丨〇). The test company 1 uses the control device 1 to perform a virtual test by the processing unit 15 based on the test program, the test pattern, and the circuit design data, and transmits the result to the terminal device 20 of the circuit design company 2 (step S8n). ^ By performing this virtual test, test patterns, timings, and the like that are not applicable to each tester can be found. After receiving the result, the circuit design company 2 can appropriately correct the test program, test pattern, and the like. Furthermore, when performing a virtual test on the logic function of the semiconductor integrated circuit, the test should be performed in a code rate manner. Here, the code rate method refers to a pattern generation method that is opposite to a pattern generation method called a time drive method or a time event method. Specifically, the time event mode extracts the timing information and the logical value of the change point by the monitoring • logical change point to generate a graph = f. In contrast, the bit rate mode divides the pattern in a certain period, and the pattern step becomes 1/0. Information 'to generate test patterns. Further, here, the test pattern to be used may not be all of the patterns, and any part (a few percent to several tens of percent) may be used within a range in which a defect can be sufficiently found, and g may be used. The time for the work is shortened and the efficiency is obtained. Next, the circuit design company 2 uses the terminal device 20 to select the tester actually used in the test, and transmits it to the control device of the test unit, by 2036-8152-PF; Ahddub 18 1363257 • This commission test (step S812) ). Then, the test company 1 performs a preparation work for converting the test program into a test program, a preliminary test, and the like, as needed (step S813). Further, the wafer production company 3 accepts the request for the wafer production from the circuit design company 2 (step S803), creates the wafer (step S8H), and transfers the wafer to the test company 1 (step S81 5). Then, the test company 1 performs the wafer test (step S816) using the control device 10, the tester, the test program (converted into an action program as needed), the test pattern 'circuit design data, the jig, etc., the wafer and the test As a result, the parent is transferred to the circuit design company 2 (step S817). The test result can be transmitted from the control device 10 to the terminal device 2A. Finally, on the control device 10, various information such as tester resources, test results, and the like are registered in the memory unit 14 (step S818). The test company 1 grasps the demand trend of the circuit design company 2 related to the frequency of the tester, the number of pins, the length of the pattern, and the like, by using various kinds of information, and can appropriately carry out the purchase of the tester in the future. Investment plans, development of low-cost testers, etc. Fig. 9 is a flowchart showing the processing when the tester resource is extracted in step S8〇7 of Fig. 8. In the control device 10, the processing unit 15 inputs a test program, that is, the test program received from the terminal device 2 of the circuit design company 2 (see the interactive editor window 23 of Fig. 2) in the memory unit 14 ( Step S901). The processing unit 15 starts from the number of lines of the test program n = ( (step S902), searches for the first line by 2036-8152-PF; Ahddub 19 1363257 n=n+1 (step S903) 'determines whether the line is a pin The code, that is, whether it is a program related to the number of pins (step S9〇4). The processing unit 15 is in the behavior of the Pin code (in step S9〇4)
Yes) 'The value of the pin number is extracted from the pin code and stored in the memory unit 14 (step S905). When the line is not the pin code (No in step 4), the processing unit 15 proceeds to step S906 to determine whether the line is a ... code, that is, whether it is a program related to the component power supply. The processing unit 15 is in the behavior VS code (in the step Μοβ
Yes), the value of the power source number is extracted from the VS code and stored in the memory unit 14 (step S907). In addition, here, only the pin count and the power supply number of the tester resource are extracted and stored, but in fact, the values of other tester resources can also be extracted and stored. The processing unit 15 determines whether or not the line is the last line (step S9〇8). If φ is the last line (No), the process returns to step S903 to perform the reverse processing, and if the line is the last line (Yes), the processing ends. Thus, in the control device 1, the tester resources can be extracted from the test program. The first diagram is a flowchart 'showing the processing when searching for the tester and calculating the cost in step S808 of Fig. 8. In the control unit 10, the processing unit 丨5 inputs a tester resource or the like, that is, the tester resource and the time-series resource extracted in step S807 of Fig. 8 are stored in the storage unit 14 (step S1001). 2036-8152-PF; Ahddub 20 ^ 63257 Next, the processing unit 15 acquires the tester information from the storage unit 14, that is, acquires the data relating to the specifications of the tester (see Fig. 3) (step S1002). The processing unit 15 starts from the model of the tester n = 0 (step sl1), and searches for the first by n=nH! The specifications of the testers (step S1〇〇4) determine whether the respective values of the tester resources satisfy the conditions of the tester model resource (tester data) of the tester (step Si〇〇5). In step S1005, when the condition is satisfied (Yes), the processing unit 15 displays the tester (a tester that can be used (step sl6)), and when the condition is not satisfied (No), the process proceeds to the step. Sl〇〇7. The processing unit 15 determines in step S1007 whether or not the processing of all the models of the tester is completed, and if it is not completed (N〇), returns to step S1004 to perform the reverse processing, and the right element is (Yes). Calculate the test cost of each tester that can be used and display it on the output unit 13 (step sl8). When calculating the test cost, first ask for the time required for the test. When the program is used, the type of the language used by the #胄# device is not relevant to the type of tester used by the household. The test cost can be multiplied by the time required for the test (4) multiplied by each tester. The unit time is obtained by using the unit price (3 yen/sec, etc.). The unit price of the tester can be used by the unit price processing unit 15 from the table of the memory unit 14 (see Fig.). Depreciation staff costs, etc. Do the appropriate calculations. In this way, you can search (select) the testers that can be used, and calculate the test cost of each tester. In addition, in addition to the test cost, you can also calculate 2036-8152-PF; Ahddub 21 1363257 and Prompt for estimating the usage time of the tester to be used. Fig. 11 is a flowchart showing the processing when calculating the wafer area increase rate when using the DFT of the SCAN technique described in Fig. 6(b). In the control device 10, the processing unit 丨5 inputs the RTL, that is, stores the circuit design data in the RTL format in the memory unit 14 (step s丨丨〇丨). Then the processing unit 15 performs logic synthesis, that is, a logic circuit for converting circuit design data in the form of RTL (step Sii 〇 2) » Next, the processing unit 15 counts the total number of logic gates N including the flip-flops in the logic circuit (step S1103), and counts the same The number of flip-flops n (step S1104) The processing unit 15 calculates the number of logical gates m used in the multiplexer by m = 3xn (step S1105). As illustrated in Fig. 6(b), Attach a flip-flop when using the %-technical DFT Since three multiplexers are used, the logical gate number m can be obtained by m = 3xn. Finally, the processing unit 15 calculates the wafer area increase rate U) caused by the DFT by m/N · 1 ( (step S1106). . As described above, the control device 10 can calculate the wafer area increase rate when the DFT is used. Then, if the DFT of SCAN technology is used, the cost of wafer fabrication will increase as the area of the wafer increases. However, the number of pins required for testing can be reduced and the test frequency can be reduced. Therefore, the steps in Figure 8 can be used. In S8〇8, a cheap tester is searched (extracted) as a usable tester, thereby making the test cost cheap. Therefore, in the step S812 of Fig. 8, even if the knowledge of 2036-8152-PF; Ah.ddub 22 1363257 DFT is insufficient, the increase in the wafer fabrication cost due to the increase in the wafer area can be considered. Each cost item such as a reduction in test cost is appropriately judged whether or not DFT will be used. Further, when the circuit design company 2 wants to use the DTF, the use of the DFT can be input through the design window 27 (see FIG. 2) of the display unit 21, and transmitted to the control device 10 of the test company 1. Fig. 12 is a flow chart showing the test cost calculation processing when the reticle is used for sharing. In addition, the number of samples referred to below is a value obtained by dividing the unit area by the target wafer. For example, in Fig. 7, the unit area is 25 mm 2 (5 mm per side) ' A chip, B chip, C chip And the number of samples of the D chip are 4, 2, 1 and 2 respectively » and 'the processing of the test cost calculation when using the reticle sharing performed in Fig. 12 and the test in the step S808 of Fig. 8 Corresponding to the cost calculation, in this case, the request for wafer fabrication from the circuit design company 2 of FIG. 8 to the wafer fabrication company 3 (step S8〇3) is performed at a time point after step S8〇8. First, the circuit design company 2 selects the shared photomask (refer to the sharing mask window 28 of Fig. 2) using the terminal device 2, and transmits the data to the control device 10 of the testing company 1. Next, in the control device 1 of the test company 1, the processing unit 15 inputs the number of samples of the shared photomask (the shared photomask phantom) received from the circuit design company 2 into the memory. The processing unit 15 determines whether or not the number of samples in the common-sharing mask s is absent (step S1202) by referring to the database relating to the sharing mask stored in the memory unit 4 (step S1202). 〇2036-8152-PF; Ahddub 23 1363257 The processing unit 15 ends the processing when the number of samples in the common-sharing mask is not missing (No in step S1202), and the number of samples in the common-sharing mask is from When there is no time (Yes in step 51202), the wafer is registered in a database related to the sharing mask of the memory unit (step S1203). By registering, the sharing mask S is vacated. The area is reduced accordingly. Next, the processing unit 15 calculates the test cost of the entire commissure mask s (step S1 204: details, which will be described later in FIG. 3), and the S-type of the entire commissure mask S The cost divided by the total number of samples, the test cost per unit area is calculated by multiplying the value by the specific The number of samples of the slice is used to calculate the test cost of the wafer (step S1 205). By this, the test cost of the wafer in the shared photomask s can be calculated on the control device 10. Fig. 13 is a flow chart showing The calculation processing of the test cost of the entire photomask sharing mask S in step S1204 of Fig. 12. First, the processing unit 15 sets the number of models used in the test of the common-sharing mask S to 1 (step S1301) Next, the processing unit 15 sets the product number of the wafer produced on the common-sharing mask S, that is, the shared mask product number to 〇 (step S1302), and sets the total test time Τ to 〇 (step S1303). Then, the processing unit 15 adds 1 to the value of the shared mask product number by D = D+1 (step S1 304), and refers to the memory unit 14 to determine the test of the wafer used for the shared mask product number. Whether the device has been logged in as the tester used on the common reticle S (step S1305). If the tester has logged in (Yes in step S1305), it is not necessary to change 2036-8152-PF; Ahddub 24 1363257. The number of models of the tester shared by the reticle s, and, if the tester is not logged in (in step In No. S1305, the processing unit 15 registers the tester in the memory unit 14 as a tester used in the sharing mask S (step S13〇6), and is used in a tester of the shared mask S. Therefore, the number is incremented by one, so the value of μ is updated by M = MH (step S1307). Next, the processing unit 15 reads the test time t of each sample number from the memory unit 14 (step S1308), by The T = T + tx sample number (the number of samples of the wafer tested using the tester) updates the value of T (step S1309). ® Next, the processing unit 15 determines whether the wafer is the last product (step S1310), and if it is not the last product (N〇), the returning step repeats the processing with 3〇4 'if the last product (Yes)' by TD = exchange work time (time required for the exchange of testers) χ (M_丨) Calculate the total job exchange time, that is, the total time required to exchange the testers (step s 311). Thereafter, the processing unit 15 extracts the test cost of the entire commissure mask S by the (T + TD ) X unit price (test cost per unit time) (step S1312). In addition, if the unit price of φ varies with each tester, the test cost of the entire shared mask S can be calculated. Thus, on the control device 10, the test cost of the entire commissure mask s in the reticle sharing can be calculated. Then, the fewer the types of testers (the number of models) using the wafers in the same sharing mask, the lower the test cost of the entire shared mask S, and the test cost of each wafer is proportional to it, followed by lowering . Thus, with the processing of Figures 12 and 13, when the circuit design company 2 requires a lower test cost tester, the type of tester used in the same shared mask can be reduced by 2036-8152. -PF; Ahddub 25 1363257 Less, the test company 1's work can also be more efficient. Moreover, by performing tests in a shared photomask, the yield of the wafer (the ratio of good products) can be improved. Figure 14 is a flow chart showing the processing when creating a bad logic gate map. The term "bad logic gate map" refers to a map showing defects on the wafer (the position of the defective logic gate). The bad logic gate map created here is used as part of the test result in step S817 of Fig. 8.
The processing unit 15 of the control device 10 inputs the defective material (defective pattern) obtained from the test executed in step S816 of Fig. 8, that is, it is stored in the storage unit 14 (step S1401). The processing unit 15 refers to the logical element reference manual (step si4〇2), which is a database related to the issue gate stored on the wafer of the storage unit 14, and sets the bad logic between right (step S14〇3). In addition, in the logic component reference hand*, bad data and bad logic gates are related to each other. Then, the processing unit 15 obtains the layout information of the wafer stored in the memory unit 14 (step S14G4) '^ the position of the defective logic gate (step S1405). Then, the processing unit 15 determines the basin 曰太*田斯, 疋Whether it is the last bad information, t is 'whether it has completed all the bad consultations from the treatment of Xiao Biaobei (step S14〇6), if it is the last bad data. 'Return to step 14〇1 to repeat Shoulder, if it is the last bad sister ~, Yu Yu (Yes), the end of the treatment. In this way, a defective 私^ private gate map is created. In step S81 of Fig. 8, the control device of the test company 1 is set to 10 to transmit the bad Logic Gate map to the terminal device 2 of the driving design company 2 at the terminal. The bad logic gate map is shown on the display portion 21 of the device 20 (see Fig. 2, the bad logic gate map of Fig. 2 is viewed as 2036-8152-PF; Ahddub 1363257 29). In addition, this bad logic gate map can be fabricated on individual wafers or on the entire wafer. Then, the circuit design company 2 can check whether the bad logic is closed, whether it is caused by a certain cause (such as foreign matter mixing, etc.) in the process of each wafer. By transmitting the reason to the wafer fabrication company 3 It can make more efficient improvements to its order and improve the yield (good ratio) in the production of semiconductor integrated circuits. Next, a modification of the navigation window 2 5 (see FIG. 2) will be described with reference to Fig. 15 (please refer to Fig. 1 as appropriate). In Fig. 15, (a) shows the navigation window 25a before the correction resource parameter, and (b) displays the navigation window 25a after the parameter is corrected. In step S1 006 of Fig. 10, the processing unit 15 (see Fig. 1) of the control device ι (see Fig. 1) is like the navigation window 25 (see Fig. 2) to the output unit 13 (see the first Figure) shows the tester that can be used. However, as shown in Figure 15 (a), it is not displayed as such, and the tester list is displayed as in the navigation window 25a. In Figure 15(a), the testers a, B, C and whether they can be used together are displayed. Here, when the operator selects the tester B that is not usable (X: can also be displayed by other symbols), in the next stop, the parameter setting of the tester B is displayed with NG or OK for each resource (cause). Whether it is appropriate to judge the result. In this resource, only the frequency is judged as NG. By correcting the parameter of the frequency, as shown in Fig. 15(b), the judgment result of the frequency becomes OK, and the tester B becomes ready for use. 2036-8152-PF; Ahddub 27 1363257 In addition, when the parameter correction of the frequency is set to 40 nanoseconds and the NG state is set to 40 nanoseconds or more, the value is rewritten to 60 nanometers. Seconds, etc., can be corrected. Thus, by displaying the display such as the navigation window 25a, the operator can easily know the reason why the tester is in an unusable state, and it is easy to make the tester usable by rewriting the parameters and the like. Further, the display of the navigation window 25a, the rewriting of parameters, and the like can be performed on the display unit 21 of the terminal device 20 of the circuit design company 2 that displays a usable tester or the like in step S809 of Fig. 8 . Next, the conversion of the command used on the tester will be described with reference to Fig. 16 (please refer to Fig. 1 as appropriate). Figure 16 is an explanatory diagram showing the conversion of instructions used on the tester. In step S816 of Fig. 8, the test company 1 performs the wafer test using the tester or the like, but at this time, the command used on the tester may not be the terminal device 2 of the circuit design company 2 in Fig. 16 Display section. The command such as "VS" shown above (see Fig. 5) is a command such as "GTL-VS" stored in the memory unit 14 of the control device 1 of the test company i in Fig. 16 in advance. In other words, a command such as "VS" is displayed on the display unit 21 of the terminal device 20 of the circuit design company 2 (see the interactive editor window (3) of Fig. 2, and the processing unit 15 is on the control device 10 of the test company i. When all these instructions are stored in the memory unit 14, the prefix or suffix (here, "GTL-") of w characters or more (here, ^ characters) can be attached. Then, at the end of the tester, The slanting tester Λ ^ attaches the so-called word 2036-8152-PF to all instructions; Ahddub 1363257 first or suffix, interpret and execute these instructions in advance. Thus, even if "vs", "ST〇p" and other instructions are in a certain In the stylized ^, the reserved words (predetermined instructions) representing other meanings, etc., in the tester, H interprets these instructions without any hindrance, and executes the test program. The characters of the right or the suffix can be avoided. The content of the reserved words can be determined by freely combining English symbols, hyphens (_), etc. Next, while referring to the 17th circle, the selection of the function definition used on the tester is explained (please refer to the figure! Etc.) Figure 17 is a flow chart, display and letter For example, as described above, in step S813 of FIG. 8, the test company prepares for the test operation of the tester, and at this time, from the control device ι to the test S- Only the function definition required for the test is stored. As shown in Fig. 17, first, the processing unit 15 of the control device 10 reads the predetermined test program to be used next from the storage unit 14 (step si7〇i). 15 sets i = l (step sl7 〇 3), reads the "description of narration (programma) (step S1705), and determines whether the function definition required for the narration is in the selection function definition file (step S1 707) In addition, the so-called selection function definition slot case refers to the function definition required for the execution of the test program at this time. The collected files are stored in the memory unit 14. If the required function definition is not selected In the function definition file (No in step S1707), the processing unit 15 extracts the function definition from the function definition library of the storage unit 14 and registers it in the selection function definition file (steps s17 and 9). The so-called function definition library' means pre- Many functions are defined and used to define the database that is collected together. 2036-8152-PF; Ahddub 29 1363257 • If the required function is defined in the selection function definition file (Yes in step S1707) and After the step s17a, the processing unit 15 determines whether the narration is the last line (step S1 711). If the narration is not the last line (No in step 31), the processing unit 15 sets i = i + i (Step S1713), the process returns to step s17. 。 5. If the description is the last line (Yes in step 81711), the processing unit 15 ends the process. Thus, the control device 10 collects a call-by-function definition library from a number of function definitions (for example, the number of function definitions is 1 000), and creates a function definition that only collects the execution of the test program at this time (for example, a letter) The selection function defines a library with a number of 2〇〇) and then passes it to the tester. The 'tester' can store only the required function definitions without storing unnecessary function definitions, thus reducing the extra burden and the like, and reducing the processing time required for testing. In addition, the selection (extraction) of the function definition required for 'here' and the use are performed when the test is performed using the tester, but in addition to this, the aforementioned virtual test may be performed (step S811 of Fig. 8). Time to proceed. The above elements have been described as an implementation form, but the form of the present invention is not limited thereto. For example, the present invention can be applied not only to a semiconductor integrated circuit such as an LSI but also to all devices using semiconductor technology such as a memory. In addition, in terms of DFT, not only SCAN technology but also other technologies such as BIST (Built-In Self-Test) can be used. Furthermore, when each device transmits and receives various data through the network 4, it can not only borrow 2036-8152-PF; Ahddub 30 1363257 can use a password and other technologies to improve the security level by encryption and the like. In addition, the specific structures of the hardware, the flowchart, and the like can be appropriately changed without departing from the spirit of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing the overall configuration of a semiconductor integrated circuit development support system. Fig. 2 is a screen display example of the display unit in the terminal device 2 of the circuit design company 2. Figure 3 is a table showing an example of the specifications of each tester. Figure 4 shows the basic structure common to testers of various modes. Figure 5 shows an example of the tester language TL. Fig. 6(a) is a schematic diagram showing a semiconductor integrated circuit of the RTL method. Fig. 6(b) is a schematic view showing a state in which the multiplexer 62 is attached to each of the flip-flops 61 when the SCAN technique is used in the semiconductor integrated circuit L shown in Fig. 6(a). Figure 7 shows the structure of the reticle shared wafer. Fig. 8 is a flow chart showing the overall operation flow related to the semiconductor integrated circuit development support system 1 000. Figure 9 is a flow chart showing the processing when the tester resources are extracted. Fig. 10 is a flowchart showing the processing when the tester is searched for in the step S8〇8 of Fig. 8 and the cost is calculated. Fig. 11 is a flow chart showing the processing when calculating the increase rate of the crystal area when the DFT using the SCAN technique is calculated. Figure 12 is a flow chart showing the test cost calculation using the reticle sharing 31 - PF; Ahddub 1363257 processing. Fig. 13 is a flowchart showing the arithmetic processing of the test cost of the entire mask shared photomask S in the step sl2〇4 of Fig. 12. Figure 14 is a flow chart showing the processing when a bad logic gate map is created. Fig. 15(a) shows a navigation window 253 before the correction parameter, and the first view shows the navigation window 253 after the correction parameter. Figure 16 is a diagram showing the transformation of the instructions used on the tester. Figure 17 is a flow chart showing the processing associated with the selection of the function definition. [Main component symbol description] 1~ test company; 2~ circuit design company; 3~ wafer fabrication company; 4~ network; 10~ control device; 11~ communication part; 12~ input part; 13~ output part; ~ memory part; 15~ processing part; 16~ memory; 20~ terminal device; 21~ display part; 22~ authentication window; 2 5~ navigation window; 23~ interactive editor window; 25a~ navigation window; 2 4 ~ test pattern window; 26 ~ virtual test window; 27 ~ design window; 28 ~ common reticle window; 29 ~ bad logic gate mapping window. 3 0 ~ terminal device; 50 ~ tester code; 51 ~ component Power supply; 52~C language form; 2036-8152-PF; Ahddub 32 1363257
61 ~ forward / reverse; 6 3 ~ test circuit line; 65 ~ combination circuit; 6 7 ~ combination circuit; 69 ~ output terminal; 71 ~ enlarged view, 30 power supply unit; 303 ~ comparator; 305 ~ timing generator; 307~DC test circuit; 623~OR logic gate; 62~ multiplexer 64~ scan circuit line; 6 6~clock line; 68~ input terminal; 7 0~ wafer, 300~ tester; 302~driver; ~ pattern generator; 306~ controller; 621, 622~AND logic gate L~ semiconductor integrated circuit; 1 000~ semiconductor integrated circuit development support system.
2036-8152-PF; Ahddub 33

Claims (1)

1363257 X. The scope of application for patents: 1 · A semiconductor integrated circuit development support system for the contact of the Fengxie solution + the use test of the dry = the volume control circuit (4) of the controlled company owned by the trustee (four) the supporter (four) Further, the above (4) is connected to the terminal device, wherein the control device includes a memory unit and a processing unit, and the memory unit converts the parameters required for the test and then uses the same in the tester. The tester language program, the plurality of the above tests include the tester data of the above-mentioned tester's action data required for the test, and the above-mentioned processing section The request of the terminal device transmits the tester language program to the above, and receives the lion from the terminal device according to the tester's language, and analyzes the test program; The action data of the tester is obtained by comparing the action data with the upper device stored in the memory unit.义 忒 忒 枓 枓 枓 枓 枓 枓 枓 提取 提取 提取 提取 提取 提取 提取 提取 提取 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体"1" The processing unit further converts any part of the test program into an action program of the tester, and estimates the time required for each of the testable devices based on the action program. Calculating the test cost or tester estimation fee of each of the above-mentioned testers 2036-8152-PF according to the above-mentioned test required time and the above-mentioned unit price used for the above-mentioned memory unit; Ahddub loading tester and its respective tests The material test cost or "test condition estimate fee is transmitted to the above terminal device." 3. The semiconductor integrated circuit development of the second part of the patent scope is supported by the t' above memory material - the step material is used in the upper volume of the material. In the testability design, the calculation of the increase in the semiconductor integrated circuit is calculated, and the processing unit is calculated based on the arithmetic expression stored in the memory unit. Using the above-mentioned increased area in the above-described testability design, the above-mentioned usable tester and the tester cost or test H estimated cost and the above-mentioned increased area are transmitted to the above-mentioned terminal device using the above testability design. The semiconductor integrated circuit development support system according to the third aspect of the invention, wherein the arithmetic expression is a mathematical expression for calculating the increased area by adding three logic gates to each of the semiconductor integrated circuits. 5. The semiconductor integrated circuit development support system of claim 3, wherein the processing unit further determines a position of the defective logic gate from data generated after the tester tests the semiconductor integrated circuit. A defective logic gate map showing the position of the defective logic gate, and transmitting the defective logic gate map to the terminal device. 6. The semiconductor integrated circuit development support system of the first application of the patent scope is in which the above processing unit further Unusable tester and unusable reason to display the above control device And the display unit of any one of the above-mentioned terminal devices. 7. The semiconductor integrated circuit development support 2036-8152-PF of the first application of the patent scope, the Ahddub 35 system, which causes the above processing. & μ > 卞 is related to each instruction in the receiving program received from the upper terminal device, and the prefix or suffix is attached to each command and the JIANG 锉 锉 6 1 factor is stored in the memory unit. 'The various instructions of the suffix are used to test the above-mentioned detectors. The semiconductor integrated circuit development support of the first part of the system TP patent scope is further described in the processing section, and the above test program is further interpreted. The extracted function definition required for the action of the above tester is supplied to the above tester. 9. A semiconductor integrated circuit developer performs a semiconductor product m including a terminal device that is owned by a controlled phase (4) owned by a tester who uses a test circuit, and which is owned by (4) _Fixed on the wafer: integrated circuit, dry lead 遐 is characterized by: two == ===...._test in the tester is used in the above test containing a plurality of testers and Allowance...: The tester data of the bit-time gate/inside of the action data of the above tester, the single a-chao price of each of the above testers, and the test according to the exchange time including a plurality of testers, the time required for the plural The calculation formula of the test cost of each of the wafers of the wafers, and the request of the terminal device of the processing unit transmits the tester language program to the terminal terminal, and sets the terminal from the terminal The device receives a test program prepared according to the above tester 2〇36-8152-PF; Ahddub 36 丄 just 257 language type, analyzes a part of the test process and extracts the tester The kinetic data x is used to calculate the data of the above-mentioned tester stored in the memory unit, and the tester can be extracted according to the above-mentioned calculation formula stored in the memory unit. The test cost of the above semiconductor integrated circuit is transmitted to the terminal device for each of the above wafers. 2036-8152-Pp; Ahddub 37
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JP2002350499A (en) * 2001-05-30 2002-12-04 Ando Electric Co Ltd Test mediating system for semiconductor integrated circuit and test mediating method for it
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