JP2005316595A - Method for verifying equivalence between circuit description and program for verifying equivalence between circuit description - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily verify equivalence between a circuit description in a system level design language and a circuit description in a hardware description language by using simulation results. <P>SOLUTION: Each time signal value transition is generated, simulation results 12 and 22 where signal name information, generation time information and first signal value information and second signal value information are made to correspond to one another are acquired by simulation using circuit descriptions 10 and 20 (S1, S2). Then, the generation time of the signal value transition of a verification object signal in the simulation result 12 is successively changed to the generation time in the simulation result 22 as long as the influence order of the signal value transition is maintained on the basis of each information of the simulation result 12 (S3). Afterwards, when all generation times of the signal value transition in the verification object signal are matched in the simulation results 12 and 22, it is decided that the circuit descriptions 10 and 20 are equivalent (S4). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for verifying equivalence between an operation level circuit description described in a system level design language and an RTL (Resister Transfer Level) circuit description described in a hardware description language.

  Recently, in system LSI design, instead of a technique for creating RTL circuit descriptions using hardware description languages (HDL) such as Verilog-HDL and VHDL, SystemC based on C (C ++) language is used. Introduction of a technique for creating a behavioral circuit description using a system level design language such as SpecC or SpecC. Since system level design languages can be described with a high level of abstraction, the introduction of circuit description creation methods using system level design languages can reduce the amount of circuit description description, that is, the time required to create a circuit description. Can be improved. In system LSI design that introduces a method for creating circuit descriptions in a system level design language, the circuit description in the system level design language (upper circuit description) is converted into a circuit description (lower circuit description) that can be logically synthesized in the hardware description language. High level synthesis is performed. Then, formal verification is performed to verify equivalence between the upper circuit description and the lower circuit description.

Patent Document 1 discloses a technique for performing accurate verification by suppressing a race between an address and data by adding a clock signal to each of two different circuit descriptions of a memory circuit and performing a simulation. Has been. Patent Document 2 corresponds to the application of a signal to each terminal of a verification target circuit in a test bench conversion method described in a hardware description language for supplying a test vector at the time of logic verification of a semiconductor integrated circuit. A technique for converting an operation description method from a description method using a delay time into a description method synchronized with a clock is disclosed.
JP-A-6-301740 Japanese Patent Laid-Open No. 10-319090

  However, current high-level synthesis tools and formal verification tools have problems such as being unable to deal with large-scale circuits or being limited in applicable descriptions. For this reason, the actual situation is that a simulation using the upper circuit description and the lower circuit description is performed, and the equivalence between the upper circuit description and the lower circuit description is manually determined from the simulation result. However, while the concept of clocks exists in hardware description languages, the concept of clocks does not exist in system-level design languages. Therefore, the simulation results (inputs) using the upper circuit description and lower circuit description respectively (input) The signal value transition timings of the signal and the output signal hardly match each other. For this reason, it is not easy to determine the equivalence between the upper circuit description and the lower circuit description from the simulation result, and much time is required to verify the equivalence between the circuit descriptions. As a result, the design efficiency is remarkably lowered, and the effect of improving the design efficiency accompanying the introduction of a circuit description creation method using a system level design language cannot be fully enjoyed.

  The present invention has been made in view of such a conventional problem, and the equivalence between the circuit description in the system level design language and the circuit description in the hardware description language is easily verified using the simulation result. For the purpose. Another object of the present invention is to improve the efficiency of cause analysis of inequality between a circuit description in a system level design language and a circuit description in a hardware description language.

  In one aspect of the present invention, a computer that verifies the equivalence between the upper circuit description described in the first design language and the lower circuit description converted from the upper circuit description and described in the second design language. The processing shown is performed. First, a simulation using the upper circuit description obtains an upper simulation result in which signal name information, generation time information, first signal value information, and second signal value information are associated with each occurrence of signal value transition. . Here, the signal name information indicates the signal name of the signal in which the signal value transition has occurred. The occurrence time information indicates the occurrence time of signal value transition. The first signal value information indicates the signal value after the signal value transition of the signal in which the signal value transition has occurred. The second signal value information indicates the signal value of the signal that causes the signal value transition to occur in the signal in which the signal value transition has occurred. In addition, a simulation using the lower circuit description obtains a lower simulation result in which signal name information, generation time information, and first signal value information are associated with each occurrence of a signal value transition.

  Thereafter, an occurrence time change process is performed on the upper simulation result. In the generation time change process, the generation time of the signal value transition of the verification target signal in the higher simulation result is determined based on the signal name information, the generation time information, the first signal value information, and the second signal value information in the higher simulation result. As long as the propagation order of the signal value transition in the simulation result is maintained, the signal value transition in the lower simulation result is sequentially changed to the generation time of the signal value transition.

  When all the signal value transition occurrence times in the verification target signal match between the higher simulation result and the lower simulation result after the generation time change processing, it is determined that the upper circuit description and the lower circuit description are equivalent. . In other words, if at least one of the signal value transition occurrence times in the verification target signal does not match between the higher simulation result and the lower simulation result after the generation time change process, it is determined that the upper circuit description and the lower circuit description are not equivalent. Is done.

  As a result, after a simulation using the upper circuit description and the lower circuit description, even if any of the signal value transition occurrence times in the verification target signal does not match between the upper simulation result and the lower simulation result, the upper circuit description And the lower circuit description can be easily verified using simulation results. For this reason, the time required for equivalence verification between circuit descriptions can be greatly reduced, and the design efficiency can be improved.

  In a preferable example of the aspect of the invention, the lower simulation result is further associated with the second signal value information. In addition, when at least one of the signal value transition occurrence times in the verification target signal does not match between the higher simulation result and the lower simulation result after the occurrence time change processing, causal relationship information is presented. Here, the causal relationship information includes the signal value transition of the verification target signal whose generation time does not match between the higher simulation result and the lower simulation result after the generation time change process and the signal value transition involved in the generation of the signal value transition. The causal relationship in the lower simulation results is shown. For this reason, the causal relationship information is used when it is determined that the upper circuit description and the lower circuit description are unequal, thereby improving the efficiency of the cause analysis of the inequality between the upper circuit description and the lower circuit description. be able to. Since it is possible to reduce the time required to analyze the cause of inequality between the upper circuit description and the lower circuit description, it is possible to contribute to the improvement of design efficiency.

  In a preferred example of the embodiment of the present invention, the signal waveform of each signal defined in the lower circuit description is generated and displayed on the display device using the lower simulation result, and the propagation path information is generated and converted into the signal waveform. Overlapping is displayed on the display device. Here, the propagation path information is information for clearly indicating the propagation path of the signal value transition that causes the signal value transition of the verification target signal whose generation time does not match between the higher simulation result and the lower simulation result after the generation time change process. It is. Therefore, the designer can visually recognize the cause of inequality between the upper circuit description and the lower circuit description from the display of the signal waveform and the propagation path information.

  In the present invention, the equivalence between the upper circuit description in the first design language and the lower circuit description in the second design language can be easily verified using the simulation result, and the design efficiency can be improved. In addition, the efficiency of the cause analysis of inequality between the upper circuit description and the lower circuit description can be improved, which can contribute to the improvement of design efficiency.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows the basic principle of the present invention. The following processing is performed by a computer that verifies the equivalence between the upper circuit description 10 described in the first design language and the lower circuit description 20 converted from the upper circuit description 10 and described in the second design language. Is done. First, a simulation using the upper circuit description 10 shows a higher simulation result (upper Sim) in which signal name information, generation time information, first signal value information, and second signal value information are associated with each occurrence of signal value transition. (Result) 12 is acquired (step S1). Here, the signal name information indicates the signal name of the signal in which the signal value transition has occurred. The occurrence time information indicates the occurrence time of signal value transition. The first signal value information indicates the signal value after the signal value transition of the signal in which the signal value transition has occurred. The second signal value information indicates the signal value of the signal that causes the signal value transition to occur in the signal in which the signal value transition has occurred. Further, a simulation using the lower circuit description 20 obtains a lower simulation result 22 in which signal name information, generation time information, first signal value information, and second signal value information are associated with each occurrence of signal value transition. (Step S2).

  Thereafter, an occurrence time change process is performed on the upper simulation result 12 (step S3). In the generation time change process, based on the signal name information, the generation time information, the first signal value information, and the second signal value information in the higher simulation result 12, the generation time of the signal value transition of the verification target signal in the higher simulation result 12 is determined. As long as the spillover order of the signal value transition in the higher simulation result 12 is maintained, the signal value transition in the lower simulation result 22 is sequentially changed to the generation time of the signal value transition.

  When all the signal value transition occurrence times in the verification target signal match between the higher simulation result 12 and the lower simulation result 22 after the generation time change processing, the upper circuit description 10 and the lower circuit description 20 are equivalent. Is determined (step S4). That is, if at least one of the signal value transition occurrence times in the verification target signal does not match between the higher simulation result 12 and the lower simulation result 22 after the generation time change process, the upper circuit description and the lower circuit description are not equivalent. It is determined.

  When at least one of the signal value transition occurrence times in the verification target signal does not match between the higher simulation result 12 and the lower simulation result 22 after the generation time change process, that is, the upper circuit description 10 and the lower circuit description 20 are not equivalent. If it is determined that there is, causal relationship information is presented (step S5). Here, the causal relationship information includes the signal value transition of the verification target signal whose generation time does not match between the higher simulation result 12 and the lower simulation result 22 after the generation time change process and the signal value transition involved in the generation of the signal value transition. The causal relationship is shown. For example, using the lower simulation result 22, the signal waveform of each signal defined in the lower circuit description 20 is generated and displayed on the display device, and the propagation path information is generated and displayed on the display device so as to overlap the signal waveform. The Here, the propagation path information clearly indicates the propagation path of the signal value transition that causes the signal value transition of the verification target signal whose generation time does not match between the higher simulation result 12 and the lower simulation result 22 after the generation time change process. Information.

  FIG. 2 shows a system configuration example for realizing the present invention. A system for realizing the present invention includes, for example, a computer such as a workstation 1 and a recording medium such as a CD-ROM 8 or a flexible disk 9 on which an equivalence checking program is recorded. The workstation 1 includes a display 2 for displaying a screen, a keyboard 3 for inputting an instruction by pressing a key, and a control device 7 in which a CPU 4, a hard disk 5, and a recording medium drive device 6 are incorporated. A CD-ROM 8 or a flexible disk 9 can be attached to the recording medium drive device 6. The work station 1 responds to an instruction input via the keyboard 3 after the CD-ROM 8 or the flexible disk 9 is mounted on the recording medium drive device 6, and the equivalent recorded in the CD-ROM 8 or the flexible disk 9. Download the verification program to the hard disk 5. The workstation 1 can perform equivalence checking processing between circuit descriptions by the CPU 4 executing the equivalence checking program.

FIG. 3 shows an embodiment of the present invention. FIG. 4 shows an example of the circuit description 100 and the test bench 101 by SystemC of FIG. FIG. 5 shows a simulation result of simulation using the circuit description 100 and the test bench 101 of FIG.
In FIG. 3, first, the workstation 1 uses a System C simulator using a circuit description 100 (higher circuit description) at a behavior level described in System C (first design language) and a test bench 101 as shown in FIG. A simulation is performed, and a simulation result 102 (higher simulation result) as shown in FIG. 5 is acquired and stored in the hard disk 5 (step S10). In the simulation result 102, each time a signal value transition occurs, signal name information (signal name column in FIG. 5), generation time information (occurrence time column in FIG. 5), and first signal value information (in FIG. 5). Signal value column) and second signal value information (occurrence factor column in FIG. 5) are associated with each other. Here, the signal name information indicates the signal name of the signal in which the signal value transition has occurred. The occurrence time information indicates the occurrence time of signal value transition. The first signal value information indicates the signal value after the signal value transition of the signal in which the signal value transition has occurred. The second signal value information indicates the signal value of the signal that causes the signal value transition to occur in the signal in which the signal value transition has occurred. For example, in the simulation result 102 of FIG. 5, in the row with an asterisk (*), a signal value transition to the signal value p [2] of the signal p occurs at time T2, and the signal that causes the signal p to generate a signal value transition. The signal values of a and b are a [2] and b [2], respectively. Since the signal value transition of the signals a and b is generated by the test bench 101, the second signal value information corresponding to the signals a and b is the same as the first signal value information.

  Further, the workstation 1 performs a simulation by a VHDL simulator using an RTL circuit description 200 (lower circuit description) written in VHDL (second design language) and a test bench 201, and a simulation result 202 (lower simulation). (Result) is acquired and stored in the hard disk 5 (step S20). Here, the circuit description 200 by VHDL is a circuit description generated by high-level synthesis of the circuit description 100 by SystemC. Although not shown, in the simulation result 202, as in the simulation result 102, signal name information, generation time information, first signal value information, and second signal value information are generated every time a signal value transition occurs. Are associated with each other.

  Thereafter, the workstation 1 performs a generation time change process on the simulation result 102 (step S30). In the generation time change process, based on the signal name information, the generation time information, the first signal value information, and the second signal value information in the simulation result 102, the signal value transition of the verification target signals a, b, and c in the simulation result 102 As long as the generation order of the signal value transition in the simulation result 102 is maintained, the generation time is sequentially changed to the generation time of the signal value transition of the verification target signals a, b, and c in the simulation result 202. Here, the propagation order of the signal value transition in the simulation result 102 indicates the generation order of the signal value transition of a certain signal and the signal value transition of another signal generated due to the signal value transition. After the signal value transition occurrence times of the verification target signals a, b, and c in the simulation result 102 are sequentially changed, all the signal value transition occurrence times in the verification target signals a, b, and c are changed to the simulation result 102 and the simulation result. In the case of a match with 202, the success of the occurrence time change process is notified. Further, when at least one of the signal value transition occurrence times in the verification target signals a, b, and c does not match between the simulation result 102 and the simulation result 202, the failure of the occurrence time change process is notified. Details of the generation time change process will be described with reference to FIGS.

  Then, the workstation 1 determines equivalence between the circuit description 100 and the circuit description 200 according to the success or failure of the generation time change process (step S40). Specifically, the workstation 1 determines that the circuit description 100 and the circuit description 200 are equivalent when the success of the generation time change process is notified. Further, the workstation 1 determines that the circuit description 100 and the circuit description 200 are not equivalent when notified of the unsuccessful occurrence time change process.

  Further, when the workstation 1 determines that the circuit description 100 and the circuit description 200 are not equivalent, the workstation 1 uses the simulation result 202 to superimpose the propagation path information on the signal waveform of each signal defined in the circuit description 200. Is displayed on the display 2 (display device) (step S50). Here, the spillover path information indicates the spillover path of the signal value transition that causes the signal value transition of the verification target signals a, b, and c whose generation times do not match between the simulation result 102 and the simulation result 202 after the generation time change process. It is information to clarify. In other words, the workstation 1 is involved in the signal value transition of the verification target signals a, b, and c whose generation times do not match between the simulation result 102 and the simulation result 202 after the generation time change process and the occurrence of the signal value transition. The causal relationship information indicating the causal relationship with the signal value transition to be generated is generated and presented.

FIG. 6 shows details of the generation time change process of FIG.
The workstation 1 performs the following processing while searching for the signal name information, generation time information, first signal value information, and second signal value information of the simulation results 102 and 202 stored in the hard disk 5.
In step S301, the workstation 1 designates one of the verification target signals a, b, and c. Thereafter, the process proceeds to step S302.

  In step S302, the workstation 1 specifies one of the signal value transitions in the verification target signal specified in step S301. For example, when the verification target signal a is designated in step S301, the workstation 1 transitions the signal value in the verification target signal a (signal value transition to signal value a [1], signal value to signal value a [2]. Transition, signal value transition to signal value a [3]). Thereafter, the process proceeds to step S303.

  In step S303, the workstation 1 determines whether or not the generation time in the simulation result 102 and the generation time in the simulation result 202 match with respect to the signal value transition specified in step S302 in the verification target signal specified in step S301. To do. If both occurrence times do not match, the process proceeds to step S304. If both occurrence times match, the process proceeds to step S308.

  In step S304, the workstation 1 determines whether the generation time in the simulation result 102 is earlier than the generation time in the simulation result 202 for the signal value transition specified in step S302 in the verification target signal specified in step S301. To do. If the occurrence time in the simulation result 102 is earlier than the occurrence time in the simulation result 202, the process proceeds to step S305. If the occurrence time in the simulation result 102 is not earlier than the occurrence time in the simulation result 2, the process proceeds to step S306.

In step S305, the workstation 1 performs forward change processing with the signal value transition specified in step S302 in the verification target signal specified in step S301 as the change target. Details of the forward change process will be described with reference to FIG. Thereafter, the process proceeds to step S307.
In step S306, the workstation 1 performs the backward change process with the signal value transition specified in step S302 in the verification target signal specified in step S301 as the change target. Details of the backward change process will be described with reference to FIG. Thereafter, the process proceeds to step S307.

In step S307, the workstation 1 determines whether the success of the backward change process performed in step S305 or the forward change process performed in step S306 has been notified. When the success is notified, the process proceeds to step S308. When the success is not notified, that is, when the unsuccess is notified, the process proceeds to step S311.
In step S308, the workstation 1 determines whether or not processing has been performed for all signal value transitions in the verification target signal specified in step S301. If the process has not been performed for all signal value transitions, the process proceeds to step S302, the workstation 1 designates the next signal value transition in the verification target signal designated in step S301, and the processes in and after step S303. Are implemented as appropriate. When the process is performed for all signal value transitions, the process proceeds to step S309.

  In step S309, the workstation 1 determines whether or not processing has been performed for all the verification target signals. When the processing has not been performed for all the verification target signals, the processing proceeds to step S301, and the workstation 1 designates the next verification target signal, and appropriately performs the processing after step S302. When the process is performed for all the verification target signals, the process proceeds to step S310.

In step S310, the workstation 1 notifies the success of the occurrence time change process, and completes the occurrence time change process.
In step S311, the workstation 1 notifies the failure of the occurrence time change process and completes the occurrence time change process.
FIG. 7 shows details of the forward change process of FIG.

  In step S701, the workstation 1 sets the generation time in the simulation result 102 of the signal value transition to be changed to the simulation result 202 of the signal value transition specified in step S302 in the verification target signal specified in step S301 in FIG. In the case of changing to the generation time in, it is determined whether or not the signal value transition ripple order in the simulation result 102 can be maintained. If the signal value transition ripple order in the simulation result 102 cannot be maintained, the process proceeds to step S702. If the signal value transition ripple order in the simulation result 102 can be maintained, the process proceeds to step S707.

In step S702, the workstation 1 designates one of the signal value transitions in the signal that causes the signal value transition to be changed. Thereafter, the process proceeds to step S703.
In step S703, the workstation 1 determines whether or not the signal value transition occurrence time designated in step S702 can be changed. If the occurrence time can be changed, the process proceeds to step S704. If the occurrence time cannot be changed, the process proceeds to step 709.

In step S704, the workstation 1 recursively executes the forward change process with the signal value transition designated in step S702 as the change target. Thereafter, the process proceeds to step S705.
In step S705, the workstation 1 determines whether or not the success of the forward change process performed in step S704 has been notified. When the success is notified, the process proceeds to step S706. If success is not notified, that is, if unsuccessful is notified, the process proceeds to step S709.

  In step S706, the workstation 1 determines whether or not processing has been performed for all signal value transitions in the signal that causes the signal value transition to be changed. If the process has not been performed for all signal value transitions, the process proceeds to step S702, and the workstation 1 designates the next signal value transition in the signal that causes the signal value transition to be changed, and after step S703. The process is appropriately implemented. When the process is performed for all signal value transitions, the process proceeds to step S707.

In step S707, the workstation 1 sets the generation time in the simulation result 102 of the signal value transition to be changed to the simulation result 202 of the signal value transition designated in step S302 in the verification target signal designated in step S301 in FIG. Change to the time of occurrence at Thereafter, the process proceeds to step S708.
In step S708, the workstation 1 notifies the success of the forward change process and completes the forward change process.

In step S709, the workstation 1 notifies the failure of the forward change process and completes the forward change process.
FIG. 8 shows details of the backward change process of FIG.
In step S801, the workstation 1 sets the generation time in the simulation result 102 of the signal value transition to be changed to the simulation result 202 of the signal value transition specified in step S302 in the verification target signal specified in step S301 in FIG. In the case of changing to the generation time in, it is determined whether or not the signal value transition ripple order in the simulation result 102 can be maintained. If the propagation order of the signal value transition in the simulation result 102 cannot be maintained, the process proceeds to step S802. If the signal value transition ripple order in the simulation result 102 can be maintained, the process proceeds to step S807.

In step S802, the workstation 1 specifies one of the signal value transitions generated due to the signal value transition to be changed. Thereafter, the process proceeds to step S803.
In step S803, the workstation 1 determines whether or not the time of occurrence of the signal value transition designated in step S802 can be changed. If the occurrence time can be changed, the process proceeds to step S804. If the generation time cannot be changed, the process proceeds to step 809.

In step S804, the workstation 1 recursively performs the backward change process with the signal value transition designated in step S802 as the change target. Thereafter, the process proceeds to step S805.
In step S805, the workstation 1 determines whether or not the success of the backward change process performed in step S804 has been notified. When the success is notified, the process proceeds to step S806. If success is not notified, that is, if unsuccessful is notified, the process proceeds to step S809.

  In step S806, the workstation 1 determines whether or not processing has been performed for all signal value transitions generated due to the signal value transition to be changed. If the process has not been performed for all signal value transitions, the process proceeds to step S802, and the workstation 1 specifies the next signal value transition that occurs due to the signal value transition to be changed, and step S803. The subsequent processing is appropriately performed. When the process is performed for all signal value transitions, the process proceeds to step S807.

In step S807, the workstation 1 sets the generation time in the simulation result 102 of the signal value transition to be changed to the simulation result 202 of the signal value transition specified in step S302 in the verification target signal specified in step S301 in FIG. Change to the time of occurrence at Thereafter, the process proceeds to step S808.
In step S808, the workstation 1 notifies the success of the backward change process, and completes the backward change process.

In step S809, the workstation 1 notifies the unsuccessful backward change process and completes the backward change process.
Here, the occurrence time changing process as described above will be specifically described. FIG. 9 shows simulation results 102 and 202 before the generation time change processing. FIG. 10 shows simulation results 102 and 202 during the generation time change process. FIG. 11 shows simulation results 102 and 202 after the generation time change processing. In this example, the times T1, T2, and T3 in the simulation result 102 are treated as times T1 ′, T4 ′, and T7 ′ in the simulation result 202.

  First, the workstation 1 designates the verification target signal a from the verification target signals a, b, and c (step S301 in FIG. 6). Then, the workstation 1 designates a signal value transition to the signal value a [1] of the verification target signal a (Step S302 in FIG. 6). Since the generation time of the signal value transition to the signal value a [1] of the verification target signal a coincides with the simulation result 102 (time T1 ′) and the simulation result 202 (time T1 ′), the workstation 1 verifies Neither forward change processing nor backward change processing for changing the signal value of the target signal a to the signal value a [1] is performed.

  Next, the workstation 1 designates a signal value transition to the signal value a [2] of the verification target signal a (step S302 in FIG. 6). The generation time of the signal value transition to the signal value a [2] of the verification target signal a does not match between the simulation result 102 (time T4 ′) and the simulation result 202 (time T2 ′), and the generation time in the simulation result 102 Since T4 ′ is not earlier than the generation time T2 ′ in the simulation result 202, the workstation 1 performs forward change processing with the signal value transition to the signal value a [2] of the verification target signal a as the change target (FIG. 6 step S306). Since the verification target signal a is an input signal, the generation time of the signal value transition to the signal value a [2] of the verification target signal a in the simulation result 102 is expressed as the signal value a [2 of the verification target signal a in the simulation result 202. ], The propagation order of the signal value transition in the simulation result 102 can be maintained even when the signal value transition occurrence time T2 ′ is changed. Therefore, as illustrated in FIG. 10A, the workstation 1 determines the generation time of the signal value transition to the signal value a [2] of the verification target signal a in the simulation result 102 by using the verification target signal a in the simulation result 202. Is changed to the signal time transition occurrence time T2 ′ to the signal value a [2] (step S707 in FIG. 7).

  Next, the workstation 1 designates a signal value transition to the signal value a [3] of the verification target signal a (step S302 in FIG. 6). Then, as in the case where the signal value transition of the verification target signal a to the signal value a [2] is designated, the workstation 1 changes the signal value transition of the verification target signal a to the signal value a [3]. Then, the forward change process is performed (step S306 in FIG. 6). Accordingly, as illustrated in FIG. 10B, the workstation 1 determines the generation time of the signal value transition to the signal value a [3] of the verification target signal a in the simulation result 102 by using the verification target signal a in the simulation result 202. Is changed to the occurrence time T3 ′ of the signal value transition to the signal value a [3] (step S707 in FIG. 7).

  Next, the workstation 1 designates the verification target signal b (step S301 in FIG. 6). As in the case where the verification target signal a is designated, the workstation 1 performs either the forward change process or the backward change process in which the signal value transition of the verification target signal b to the signal value b [1] is the change target. Without the implementation, the forward change process is performed with the signal value transition of the verification target signal b to the signal values b [2] and b [3] as the change target. That is, as illustrated in FIGS. 10C and 10D, the workstation 1 determines the generation time of the signal value transition to the signal values b [2] and b [3] of the verification target signal b in the simulation result 102. In the simulation result 202, the signal value transition of the verification target signal b to the signal values b [2] and b [3] is sequentially changed to the generation times T2 ′ and T3 ′.

  Next, the workstation 1 designates the verification target signal c (step S301 in FIG. 6). Then, the workstation 1 designates a signal value transition to the signal value c [1] of the verification target signal c (step S302 in FIG. 6). The generation time of the signal value transition to the signal value c [1] of the verification target signal c does not match between the simulation result 102 (time T1 ′) and the simulation result 202 (time T4 ′), and the generation time in the simulation result 102 Since T1 ′ is before the occurrence time T4 ′ in the simulation result 202, the workstation 1 performs the backward change process with the signal value transition of the verification target signal c to the signal value c [1] as the change target (FIG. 6 step S305). Since the verification target signal c is an output signal, the generation time of the signal value transition to the signal value c [1] of the verification target signal c in the simulation result 102 is expressed as the signal value c [1 of the verification target signal c in the simulation result 202. ], The propagation order of the signal value transition in the simulation result 102 can be maintained. Therefore, as illustrated in FIG. 10E, the workstation 1 determines the generation time of the signal value transition to the signal value c [1] of the verification target signal c in the simulation result 102 by using the verification target signal c in the simulation result 202. Is changed to the occurrence time T4 ′ of the signal value transition to the signal value c [1] (step S807 in FIG. 8).

  Next, the workstation 1 designates a signal value transition to the signal value c [2] of the verification target signal c (step S302 in FIG. 6). Then, similarly to the case where the signal value transition to the signal value c [1] of the verification target signal c is specified, the workstation 1 changes the signal value transition of the verification target signal c to the signal value c [2]. As shown in FIG. 6, backward change processing is performed (step S305 in FIG. 6). Therefore, as illustrated in FIG. 10F, the workstation 1 determines the generation time of the signal value transition to the signal value c [2] of the verification target signal c in the simulation result 102, and the verification target signal c in the simulation result 202. Is changed to the occurrence time T5 ′ of the signal value transition to the signal value c [2] (step S807 in FIG. 8).

  Next, the workstation 1 designates a signal value transition to the signal value c [3] of the verification target signal c (step S302 in FIG. 6). The generation time of the signal value transition to the signal value c [3] of the verification target signal c does not match between the simulation result 102 (time T7 ′) and the simulation result 202 (time T6 ′), and the generation time in the simulation result 102 Since T7 ′ is not earlier than the generation time T6 ′ in the simulation result 202, the workstation 1 performs forward change processing with the signal value transition to the signal value c [3] of the verification target signal c as a change target (FIG. 6 step S306). The signal value transition of the verification target signal c to the signal value c [3] occurs due to the signal value transition of the signal s to the signal value s [3]. For this reason, the generation time of the signal value transition to the signal value c [3] of the verification target signal c in the simulation result 102 is set as the generation time of the signal value transition to the signal value c [3] of the verification target signal c in the simulation result 202. When the time T6 ′ is changed, the generation time of the signal value transition to the signal value c [3] of the signal c to be verified is before the generation time T7 ′ of the signal value transition to the signal value s [3] of the signal s. Therefore, it is not possible to maintain the signal value transition ripple order in the simulation result 102.

  Accordingly, the workstation 1 designates the signal value transition of the signal s to the signal value s [3] in order to change the occurrence time of the signal value transition of the signal s to the signal value s [3] (FIG. 7). Step S702). Since the signal value transition to the signal value s [3] of the signal s can change the generation time, the workstation 1 performs forward change processing on the signal value transition of the signal s to the signal value s [3] as a change target. Is recursively implemented (step S704 in FIG. 7). The signal value transition of the signal s to the signal value s [3] is caused by the signal value transition of the signal p to the signal value p [3] and the signal value transition of the signal q to the signal value q [3]. Occur. For this reason, the occurrence time of the signal value transition to the signal value s [3] of the verification target signal s in the simulation result 102 is set to the occurrence of the signal value transition to the signal value c [3] of the verification target signal c in the simulation result 202. When the time T6 ′ is changed, the generation time of the signal value transition to the signal value s [3] of the signal to be verified s is changed to the generation time T7 ′ of the signal value transition to the signal value p [3] of the signal p and the signal q. Before the signal value transition occurrence time T7 ′ to the signal value q [3], the propagation order of the signal value transition in the simulation result 102 cannot be maintained.

  Accordingly, the workstation 1 first designates the signal value transition of the signal p to the signal value p [3] in order to change the occurrence time of the signal value transition of the signal p to the signal value p [3] ( Step S702 in FIG. Since the signal value transition of the signal p to the signal value p [3] can change the generation time, the workstation 1 performs forward change processing on the signal value transition of the signal p to the signal value p [3] as a change target. Is recursively implemented (step S704 in FIG. 7). The signal value transition of the signal p to the signal value p [3] is caused by the signal value transition of the signal a to the signal value a [3] and the signal value transition of the signal b to the signal value b [3]. Occur. However, the generation time of the signal value transition to the signal value p [3] of the verification target signal p in the simulation result 102 is the generation time of the signal value transition to the signal value c [3] of the verification target signal c in the simulation result 202. Even if it is changed to T6 ′, the ripple order of the signal value transition in the simulation result 102 can be maintained. Therefore, as illustrated in FIG. 11G, the workstation 1 determines the generation time of the signal value transition to the signal value p [3] of the verification target signal p in the simulation result 102 as the verification target signal c in the simulation result 202. Is changed to a signal value transition occurrence time T6 ′ to the signal value c [3] (step S707 in FIG. 7).

  Next, the workstation 1 designates the signal value transition of the signal q to the signal value q [3] in order to change the occurrence time of the signal value transition of the signal q to the signal value q [3] (FIG. 7 step S702). Then, similarly to the case where the signal value transition of the signal p to the signal value p [3] is designated, the workstation 1 performs the forward change process with the signal value transition of the signal q to the signal value q [3] as a change target. Is recursively implemented (step S704 in FIG. 7). Therefore, as shown in FIG. 11 (h), the workstation 1 uses the signal value transition time to the signal value q [3] of the signal q in the simulation result 102 as the signal of the verification target signal c in the simulation result 202. The signal value transition to the value c [3] is changed to the occurrence time T6 ′ (step S707 in FIG. 7).

  Thereafter, when the workstation 1 recognizes the success of the forward change process for changing the signal value transition of the signal p to the signal value p [3] and the signal value transition of the signal q to the signal value q [3]. As shown in FIG. 11 (i), the occurrence time of the signal value transition to the signal value s [3] of the signal s in the simulation result 102 is changed to the signal value c [3] of the verification target signal c in the simulation result 202. Is changed to the occurrence time T6 ′ of the signal value transition (step S707 in FIG. 7).

  Then, when the workstation 1 recognizes the success of the forward change process in which the signal value transition of the signal s to the signal value s [3] is changed, the verification in the simulation result 102 is performed as shown in FIG. The generation time of the signal value transition to the signal value c [3] of the target signal c is changed to the generation time T6 ′ of the signal value transition to the signal value c [3] of the verification target signal c in the simulation result 202 (FIG. 7 step S707). As a result, the processes for all the verification target signals a, b, and c are completed, and the workstation 1 notifies the success of the generation time change process and completes the generation time change process.

FIG. 12 shows a display example of signal waveforms and signal value transition spillover paths associated with the inequality determination between the circuit descriptions 100 and 200 of FIG. This example shows a case where the occurrence time change process is notified of failure when the signal value transition to the signal value c [2] of the verification target signal c is designated.
When the workstation 1 determines that the circuit description 100 and the circuit description 200 are not equivalent based on the notification that the generation time change process is not successful, the signals a and b defined in the circuit description 200 are used using the simulation result 202. , C, x, y, z signal waveforms are provided with arrows (propagation path information) for clearly indicating the propagation path of the signal value transition that causes the signal value transition of the verification target signal c to the signal value c [2]. It is displayed on the display 2 in a superimposed manner. The signals x, y, and z are signals newly defined in the circuit description 200 as the circuit description 100 is synthesized at a high level.

In the simulation using the circuit description 200 and the test bench 201, the signal x is caused by the signal value transition of the signal a to the signal value a [3] and the signal value transition of the signal b to the signal value b [2]. Signal value transition to the signal value x [2]. The signal value transition of the signal y to the signal value y [2] occurs due to the signal value transition of the signal a to the signal value a [2] and the signal value transition of the signal b to the signal value b [2]. To do. The signal value transition of the signal z to the signal value z [2] occurs due to the signal value transition of the signal x to the signal value x [2] and the signal value transition of the signal y to the signal value y [2]. To do. Due to the signal value transition of the signal z to the signal value z [2], a signal value transition of the signal c to the signal value c [2] occurs. Accordingly, the following signal value transition propagation paths (1) to (4) exist as signal value transition propagation paths that cause the signal value transition of the verification target signal c to the signal value c [2].
(1) a [3]-> x [2]-> z [2]-> c [2]
(2) b [2]-> x [2]-> z [2]-> c [2]
(3) a [2]-> y [2]-> z [2]-> c [2]
(4) b [2]-> y [2]-> z [2]-> c [2]
The causal relationship between the signal value transitions involved in the generation of the signal value transition to the signal value c [2] of the verification target signal c is indicated by an arrow, whereby the signal to the signal value c [2] of the verification target signal c Since the signal value transition propagation paths (1) to (4) for generating the value transition are clearly indicated, the signal value transition propagation path for generating the signal value transition to the signal value c [2] of the verification target signal c is used. It can be easily recognized that a signal value transition to the signal value a [3] of the signal a that should not be included is included. As a result, the efficiency of the cause analysis of inequality between the circuit description 100 and the circuit description 200 is improved.

  As described above, in the present embodiment, even if any of the signal value transition occurrence times in the verification target signal does not match between the simulation result 102 and the simulation result 202 after the simulation using the circuit description 100 and the circuit description 200, respectively. The equivalence between the circuit description 100 and the circuit description 200 can be easily verified using the simulation results 102 and 202. For this reason, the time required for the equivalence verification between the circuit descriptions 100 and 200 can be greatly reduced, and the design efficiency can be improved.

  When it is determined that the circuit description 100 and the circuit description 200 are not equivalent, the simulation result 102 and the simulation result 202 after the generation time change process are added to the signal waveform of each signal defined in the circuit description 200. Since the arrows for clearly indicating the propagation path of the signal value transition for generating the signal value transition of the verification target signal whose generation times do not coincide with each other are displayed on the display 2 in an overlapping manner, the circuit description 100 and the circuit description 200 are not equivalent. The cause can be visually recognized, and the efficiency of inequality cause analysis can be improved. Since the time required for the cause analysis of the inequality between the circuit description 100 and the circuit description 200 can be shortened, the design efficiency can be improved.

  In the above-described embodiment, the example in which the present invention is applied to the equivalence verification between the circuit description 100 by SystemC and the circuit description 200 by VHDL has been described. However, the present invention is not limited to such an embodiment. For example, when the circuit description 100 is described in another system level design language (for example, SpecC) or the circuit description 200 is described in another hardware description language (for example, Verilog-HDL), the present invention is also applied. Can be applied as well.

  In the above-described embodiment, when it is determined that the circuit description 100 and the circuit description 200 are not equivalent, the simulation result 102 and the simulation after the generation time change process are added to the signal waveform of each signal defined in the circuit description 200. The example in which the arrows for clearly indicating the propagation path of the signal value transition for generating the signal value transition of the verification target signal whose generation time does not coincide with the result 202 is displayed on the display 2 has been described. However, the present invention is not limited to such an embodiment. For example, a text message may be displayed on the display 2 that clearly indicates the propagation path of the signal value transition that generates the signal value transition of the verification target signal that does not coincide with the generation time.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
By the simulation using the upper circuit description described in the first design language, the signal name information indicating the signal name of the signal in which the signal value transition has occurred and the time at which the signal value transition has occurred are shown for each occurrence of the signal value transition. A higher simulation result is obtained in which the generation time information, the first signal value information indicating the signal value after the signal value transition, and the second signal value information indicating the signal value of the signal causing the signal value transition are associated with each other. ,
Signal name information indicating the signal name of the signal in which the signal value transition has occurred, for each occurrence of the signal value transition, by simulation using the lower circuit description converted from the upper circuit description and described in the second design language; Obtaining a lower simulation result in which occurrence time information indicating the occurrence time of the signal value transition and first signal value information indicating the signal value after the signal value transition are associated with each other;
Based on the signal name information, the generation time information, the first signal value information, and the second signal value information in the upper simulation result, the generation time of the signal value transition of the verification target signal in the upper simulation result is As long as the propagation order of the signal value transition in the upper simulation result is maintained, the generation time change process for sequentially changing to the generation time of the signal value transition of the verification target signal in the lower simulation result is performed,
When all the signal value transition occurrence times in the verification target signal match between the higher simulation result after the occurrence time change process and the lower simulation result, the upper circuit description and the lower circuit description are equivalent. A method for verifying equivalence between circuit descriptions, characterized by determining.
(Appendix 2)
In the method for verifying equivalence between circuit descriptions described in Appendix 1,
The lower simulation result is further associated with second signal value information indicating a signal value of a signal causing a signal value transition,
If at least one of the signal value transition occurrence times in the verification target signal does not match between the higher simulation result after the generation time change process and the lower simulation result, the signal value transition of the verification target signal that does not match the generation time A method for verifying equivalence between circuit descriptions, characterized by generating and presenting causal relationship information indicating a causal relationship in a lower simulation result with a signal value transition involved in the occurrence of the signal value transition.
(Appendix 3)
In the method for verifying equivalence between circuit descriptions described in Appendix 2,
Using the lower simulation result, a signal value of each signal defined in the lower circuit description is generated and displayed on a display device, and a signal value for generating a signal value transition of the verification target signal whose generation time does not match A method for verifying equivalence between circuit descriptions, characterized in that spillover path information for clearly indicating a spillover path of transition is generated as the causal relation information and displayed on the display device so as to be superimposed on the signal waveform.
(Appendix 4)
A computer for verifying equivalence between the upper circuit description described in the first design language and the lower circuit description converted from the upper circuit description and described in the second design language;
According to the simulation using the upper circuit description, for each occurrence of the signal value transition, signal name information indicating the signal name of the signal in which the signal value transition has occurred, generation time information indicating the occurrence time of the signal value transition, and signal value A first step of acquiring an upper simulation result in which first signal value information indicating a signal value after transition and second signal value information indicating a signal value of a signal causing a signal value transition are associated;
Based on the simulation using the lower circuit description, for each occurrence of the signal value transition, signal name information indicating the signal name of the signal in which the signal value transition has occurred, generation time information indicating the occurrence time of the signal value transition, and signal value A second step of acquiring a lower simulation result associated with first signal value information indicating a signal value after transition;
Based on the signal name information, the generation time information, the first signal value information, and the second signal value information in the upper simulation result, the generation time of the signal value transition of the verification target signal in the upper simulation result is A third step of performing an occurrence time changing process that sequentially changes to the occurrence time of the signal value transition of the verification target signal in the lower simulation result as long as the propagation order of the signal value transition in the upper simulation result is maintained;
When all the signal value transition occurrence times in the verification target signal match between the higher simulation result after the occurrence time change process and the lower simulation result, the upper circuit description and the lower circuit description are equivalent. A program for verifying equivalence between circuit descriptions, characterized in that a fourth step of determination is executed.
(Appendix 5)
In the equivalence checking program between circuit descriptions described in Appendix 4,
The lower simulation result is further associated with second signal value information indicating a signal value of a signal causing a signal value transition,
In the fourth step, if at least one of the occurrence times of signal value transitions in the verification target signal does not match between the higher simulation result after the generation time change process and the lower simulation result, the verification target whose generation times do not match Causing the computer to further execute a fifth step of generating and presenting causal relationship information indicating the causal relationship in the lower simulation result between the signal value transition of the signal and the signal value transition involved in the generation of the signal value transition. A program for verifying equivalence between circuit descriptions.
(Appendix 6)
In the method for verifying equivalence between circuit descriptions according to appendix 5,
The fifth step uses the lower simulation result to generate a signal waveform of each signal defined in the lower circuit description and display it on a display device, and the signal value of the verification target signal whose generation time does not match Between circuit descriptions characterized in that it is a step of generating, as the causal relationship information, spillover path information for clearly indicating a spillover path of a signal value transition that causes a transition, and displaying the spillover path information on the display device in a superimposed manner Equivalence verification program.

  As mentioned above, although this invention was demonstrated in detail, the above-mentioned embodiment and its modification are only examples of this invention, and this invention is not limited to these. Obviously, modifications can be made without departing from the scope of the present invention.

It is explanatory drawing which shows the basic principle of this invention. It is explanatory drawing which shows the system configuration example for implement | achieving this invention. It is explanatory drawing which shows one Embodiment of this invention. It is explanatory drawing which shows an example of the circuit description and test bench by SystemC of FIG. FIG. 5 is an explanatory diagram showing a simulation result of simulation using the circuit description and the test bench of FIG. 4. It is a flowchart which shows the detail of the generation time change process of FIG. It is a flowchart which shows the detail of the front change process of FIG. It is a flowchart which shows the detail of the back change process of FIG. It is a timing chart which shows the simulation result before generation time change processing. It is a timing chart which shows the simulation result in the generation time change process. It is a timing chart which shows the simulation result after generation time change processing. It is explanatory drawing which shows the example of a display of the propagation path of the signal waveform and signal value transition accompanying the inequality determination between the circuit descriptions of FIG.

Explanation of symbols

1 Workstation 2 Display 3 Keyboard 4 CPU
5 Hard disk 6 Recording medium drive device 7 Control device 8 CD-ROM
9 Flexible disk 10 Upper circuit description 12 Upper simulation result 20 Lower circuit description 22 Lower simulation result 100, 200 Circuit description 101, 201 Test bench 102, 202 Simulation result

Claims (5)

By the simulation using the upper circuit description described in the first design language, the signal name information indicating the signal name of the signal in which the signal value transition has occurred and the time at which the signal value transition has occurred are shown for each occurrence of the signal value transition. A higher simulation result is obtained in which the generation time information, the first signal value information indicating the signal value after the signal value transition, and the second signal value information indicating the signal value of the signal causing the signal value transition are associated with each other. ,
Signal name information indicating the signal name of the signal in which the signal value transition has occurred, for each occurrence of the signal value transition, by simulation using the lower circuit description converted from the upper circuit description and described in the second design language; Obtaining a lower simulation result in which occurrence time information indicating the occurrence time of the signal value transition and first signal value information indicating the signal value after the signal value transition are associated with each other;
Based on the signal name information, the generation time information, the first signal value information, and the second signal value information in the upper simulation result, the generation time of the signal value transition of the verification target signal in the upper simulation result is As long as the propagation order of the signal value transition in the upper simulation result is maintained, the generation time change process for sequentially changing to the generation time of the signal value transition of the verification target signal in the lower simulation result is performed,
When all the signal value transition occurrence times in the verification target signal match between the higher simulation result after the occurrence time change process and the lower simulation result, the upper circuit description and the lower circuit description are equivalent. A method for verifying equivalence between circuit descriptions, characterized by determining. The equivalence checking method between circuit descriptions according to claim 1,
The lower simulation result is further associated with second signal value information indicating a signal value of a signal causing a signal value transition,
If at least one of the signal value transition occurrence times in the verification target signal does not match between the higher simulation result after the generation time change process and the lower simulation result, the signal value transition of the verification target signal that does not match the generation time A method for verifying equivalence between circuit descriptions, characterized by generating and presenting causal relationship information indicating a causal relationship in a lower simulation result with a signal value transition involved in the occurrence of the signal value transition. The equivalence checking method between circuit descriptions according to claim 2,
Using the lower simulation result, a signal value of each signal defined in the lower circuit description is generated and displayed on a display device, and a signal value for generating a signal value transition of the verification target signal whose generation time does not match A method for verifying equivalence between circuit descriptions, characterized in that spillover path information for clearly indicating a spillover path of transition is generated as the causal relation information and displayed on the display device so as to be superimposed on the signal waveform. A computer for verifying equivalence between the upper circuit description described in the first design language and the lower circuit description converted from the upper circuit description and described in the second design language;
According to the simulation using the upper circuit description, for each occurrence of the signal value transition, signal name information indicating the signal name of the signal in which the signal value transition has occurred, generation time information indicating the occurrence time of the signal value transition, and signal value A first step of acquiring an upper simulation result in which first signal value information indicating a signal value after transition and second signal value information indicating a signal value of a signal causing a signal value transition are associated;
Based on the simulation using the lower circuit description, for each occurrence of the signal value transition, signal name information indicating the signal name of the signal in which the signal value transition has occurred, generation time information indicating the occurrence time of the signal value transition, and signal value A second step of acquiring a lower simulation result associated with first signal value information indicating a signal value after transition;
Based on the signal name information, the generation time information, the first signal value information, and the second signal value information in the upper simulation result, the generation time of the signal value transition of the verification target signal in the upper simulation result is A third step of performing an occurrence time changing process that sequentially changes to the occurrence time of the signal value transition of the verification target signal in the lower simulation result as long as the propagation order of the signal value transition in the upper simulation result is maintained;
When all the signal value transition occurrence times in the verification target signal match between the higher simulation result after the occurrence time change process and the lower simulation result, the upper circuit description and the lower circuit description are equivalent. A program for verifying equivalence between circuit descriptions, characterized in that a fourth step of determination is executed. The equivalence checking program between circuit descriptions according to claim 4,
The lower simulation result is further associated with second signal value information indicating a signal value of a signal causing a signal value transition,
In the fourth step, if at least one of the occurrence times of signal value transitions in the verification target signal does not match between the higher simulation result after the generation time change process and the lower simulation result, the verification target whose generation times do not match Causing the computer to further execute a fifth step of generating and presenting causal relationship information indicating the causal relationship in the lower simulation result between the signal value transition of the signal and the signal value transition involved in the generation of the signal value transition. A program for verifying equivalence between circuit descriptions.

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