JP4564914B2 - Automatic assertion generation device and logic circuit design verification method - Google Patents

Description

  The present invention relates to logic circuit design verification in which assertion automatic generation and assertion are incorporated as a checker. An assertion is a description that expresses the functional specification and design intention of a logic circuit.

  As one of means for verifying the design of a logic circuit, assertion-based verification in which an assertion is incorporated as a checker is known. In assertion-based verification, when designing a new logic circuit using an IP (Intellectual Property) of a general-purpose circuit or an existing circuit, the assertion is incorporated as a checker to set the user's logic circuit from the verification result. It can be judged whether it is a mistake or a malfunction of the IP itself.

  In order to create an assertion, it is necessary to have an element that allows the detailed specification of the circuit to be verified to be understood from the circuit specification and circuit description, and the assertion creator and circuit verifier must specify the specification of the circuit to be verified. Need to figure out. As shown in the schematic diagram of FIG. 4, when verifying the changed circuit A ′ generated by adding or deleting functions to the original reference circuit A, the specification of the reference circuit A is grasped and the assertion before the change is performed. A new assertion C different from B is created.

  In order to eliminate an artificial mistake in this case, an assertion generation method having a mechanism capable of automatically generating an assertion has been proposed (see, for example, Patent Document 1). The “property” in this patent document corresponds to the assertion here, and the automatic property generation flow is as shown in FIG.

  The input elements of the automatic generation apparatus 301 in FIG. 5 are a circuit specification 302 of the processor to be verified and a circuit description 305 of the processor. The circuit specification 302 is analyzed by the specification analysis unit 303 to generate necessary information, and an operation model is generated by the operation model generation unit 304 from this information. On the other hand, the circuit description 305 is input to the circuit description reading unit 306 and analyzed by the description analysis unit 307. Then, the behavior model obtained from the circuit specification 302 and the description analysis result obtained from the circuit description 305 are input to the property generation unit 308, and the property 309 is generated.

JP2000-268074 (pages 6-7, FIG. 33)

  However, in the prior art described in Patent Document 1 described above, detailed specifications and circuit descriptions must be analyzed in order to create an assertion. There is a first problem that it is very difficult to generate an assertion for a circuit that cannot.

  In addition, if the specification is misinterpreted, it will lead to an error in the assertion checker, which is the standard for judging whether the circuit is correct. There is a second problem that much time is required until the verification is performed.

  Therefore, an object of the present invention is to provide an assertion automatic generation apparatus and an assertion automatic generation method capable of automatically generating an assertion even in a circuit in which detailed specifications cannot be analyzed like IP and a circuit description cannot be referred to. It is to provide.

  Another object of the present invention is to provide a logic circuit design verification method that reduces the backtracking of the verification process even when the verification result is not correct.

  An assertion automatic generation apparatus according to the present invention is an assertion automatic generation apparatus that generates an assertion as a checker when a new logic circuit is designed using a verification reference circuit and the circuit is a verification target circuit. A signal information file storing signal information (101 in FIG. 1) which is signal name information in each verification reference circuit, and a level transition of a signal appearing in an evaluation pattern of a verification target circuit in an operation pattern of the verification reference circuit Signal change information (104 in FIG. 1) for the verification target signal and the corresponding verification reference signal from the waveform data file storing the operation waveform data (102 in FIG. 1), the signal information file and the waveform data file. , 105) for generating signal change information (103 in FIG. 1) and signal change information And force, and having an assertion generating unit that generates an assertion is a description representing the functional specification and design intent of a logic circuit (107 in FIG. 1) (106 in FIG. 1).

  The signal change information includes the value at the predetermined time of the first function Tn (t) for extracting the time at which the value of the signal n transitions from the operation waveform data, and the value at the time of transition of the signal n. The second function N (t) to be taken out from the value at a predetermined time, and the assertion generator generates the second function value Na (t) of the verification reference signal a and the verification target signal corresponding to the verification reference signal a. The value Nb (t) of the second function for b and the value Qab (t) of the third function as change time information obtained from the relative difference between the first function values of the verification reference signal a and the verification target signal b. Assertion is generated by a function H for converting to an assertion description using as a variable.

  Further, the assertion automatic generation method of the present invention is the verification target signal name in the user logic specification (201 in FIG. 2) of the verification target circuit in the logic circuit design verification method based on the verification reference circuit using the above assertion automatic generation device. And a step in which the verifier prepares signal information (101 in FIG. 2) which is information of the verification reference signal name in the corresponding verification reference circuit (202 in FIG. 2), and a test created based on the user logic specification A step of creating an evaluation pattern (206 in FIG. 2), which is a pattern, and an operation pattern (203 in FIG. 2) are executed (step S1 in FIG. 2). A circuit description of the evaluation pattern and verification reference circuit (204 in FIG. 2) ) To generate operation waveform data (102 in FIG. 2) that is information indicating the level transition of the signal appearing in the evaluation pattern among the operation patterns, and the signal information and the operation waveform data. Characterized in that it has automatically generate (step S2 in FIG. 2) comprises an assertion.

  The logic circuit design verification method of the present invention is a logic circuit design verification method using assertions generated by the assertion automatic generation method, and is based on the user logic specifications and the outline specifications of the verification reference circuit (205 in FIG. 2). Ascertain the new specification (step S3 in FIG. 2), and determine whether there is a circuit change from the circuit description and the generated assertion based on this (step S4 in FIG. 2). If there is a stage for changing the verification reference circuit, a stage for verifying the verification target circuit using the evaluation pattern and the generated assertion based on the verification reference circuit (step S5 in FIG. 2), and the verification result must be OK. (Step S6 in FIG. 2), the method includes returning to the grasp of the specification, creating a verification reference circuit after the change, and performing verification again.

  The first effect of the present invention is that for a verification target circuit in which detailed circuit specifications and circuit descriptions such as IP cannot be analyzed if the operation waveform data of the circuit and the verification target signal can be clarified. However, it is possible to perform assertion-based verification. The reason is that the circuit detailed specification analysis result and the circuit description are not required as input elements for the automatic generation of assertion.

  The second effect of the present invention is that, when the verification result is judged to be incorrect, the return of verification is less than that of the prior art, and when the IP or part of the existing circuit is changed and reused, etc. By incorporating an assertion automatically generated from the circuit as a checker into the circuit after the change, a difference in the circuit such as an unintended change can be found earlier. The reason for this is that if the verification result is determined to be incorrect, the verifier returns to grasping the specifications, and the review is limited to the circuit to be verified. Is shortened.

  A feature of the present invention is that signal information having information on a verification target signal name and a verification reference signal name and operation waveform data of a circuit serving as a verification reference are input, and a verification reference signal change is performed with respect to a signal specified by the signal information. An automatic signal change information generation unit that generates information and verification target signal change information, and an assertion automatic generation program that automatically generates an assertion using the generated verification reference signal change information and verification target signal change information as inputs There is. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 2 is a flowchart showing the logic circuit design verification method of the present invention. This logic circuit design verification method verifies the user logic specification 201 of a new logic circuit using IP202. The IP 202 includes an operation pattern 203, a circuit description 204, and an outline specification 205. The IP 202 functions as a verification reference circuit, and the user logic specification 201 functions as a verification target circuit.

  First, the verifier prepares signal information 101 that is information on the verification target signal name in the user logic specification 201 and the corresponding verification reference signal name in IP202. Also, an evaluation pattern, which is a test pattern created based on the user logic specification 201, is created. User logic specifications 201, IP 202 and signal information 101 are connected as a file to a computer for executing this logic circuit design verification method.

  When a program for executing this logic circuit design verification method is activated, an operation pattern 203 is executed (step S1 in FIG. 2), and operation waveform data (hereinafter, “waveform data”) is based on the evaluation pattern 206 and the circuit description 204. 102) is generated. The waveform data 102 is information indicating a level transition of a signal that appears in the evaluation pattern 206 in the operation pattern 203.

  Next, an assertion is automatically generated from the signal information 101 and the waveform data 102 (step S2 in FIG. 2). FIG. 1 is a diagram for explaining automatic generation of assertions. The signal change information automatic generation unit 103 extracts the verification reference signal change information 104 and the verification target signal change information 105 from the waveform data 102 for the verification reference signal and the verification target signal specified by the signal information 101. The assertion generation unit 106 compares the verification reference signal change information 104 with the verification target signal change information 105 and generates an assertion 107.

  Next, a new specification is grasped based on the user logic specification 201 and the summary specification 205 (step S3 in FIG. 2), and based on this, it is determined whether there is a circuit change from the circuit description 204 and the generated assertion 107. Is done. If there is a circuit change, the changed IP 207 is created by changing the IP 202 (step S4 in FIG. 2).

  Finally, the verification target circuit is verified using the evaluation pattern 206 and the assertion 107 based on the changed IP207 or IP208 (same as IP202) (step S5 in FIG. 2). If the verification result is OK, the logic circuit design verification ends. If the verification result is not OK (step S6 in FIG. 2), the verifier checks whether the bug is in the IP itself, a circuit change error, or an evaluation pattern error (verification result feedback process). After that, the process returns to grasping the specifications (step S3 in FIG. 2), creating the changed IP207, and re-verifying (step S5 in FIG. 2).

  Here, it should be noted that the feedback of the verification result depends on grasping the specification which is a process after the automatic generation of the assertion. As a result, it is not necessary to recreate the assertion even if the verification result is not OK.

  FIG. 6 is a flowchart of circuit design verification assuming that the verification result is not OK and the verification result is fed back in the circuit verification using the conventional property automatic generation method shown in FIG. In FIG. 6, since the assertion creation (step T3 in FIG. 6) is performed after the specification is grasped (step T2 in FIG. 6), the assertion must be generated again in the backtracking process. A lot of time is required.

  Next, a method for creating the assertion 107 will be described using a specific example of the waveform data 102. Assume that the verification reference signal a and the verification target signal b specified in the signal information 101 are as shown in FIG. Referring to FIG. 3, during time t = 0 to tend, the verification reference signal a changes three times, and the verification target signal b is the second after k1 from the rise of the first verification reference signal a. After the rising edge of the verification reference signal a, the signal rises k3 after the rising edge of the third verification reference signal a, and k3 <k1 <k2. In this case, the assertion to be automatically generated is “the signal b changes during the time k3 to k2 from the rising edge of the signal a”.

The waveform data 102 shown in FIG. 3, the signal information 101 including the verification reference signal a and the verification target signal b, and the signal change information automatic generation unit 103 shown in FIG. The signal change information automatic generation unit 103 verifies the verification reference signal change information 104 and the verification reference signal change information 104 in which the value and time of the signal change are sequentially input from the waveform data 102 with respect to the verification reference signal a and the verification target signal b specified in the signal information 101 The target signal change information 105 is generated. Here, assuming that the function for taking out the time when the value of the signal n changes from the waveform data 102 is Tn (t), the signal change information of the signal a at the time t = 0 to tend is the equation (1) and the signal change of the signal b. The information is expressed by equation (2).

Next, the verification reference signal change information 104 and the verification target signal change information 105 are input to the assertion generation unit 106, and the relationship between the signals a and b specified in the signal information 101 is recognized by comparing the two. Here, a function for obtaining the time from the changing point of the signal n to the changing point of the signal m is defined as Qmn (t). The time k1 from the change point of the signal a to the change of the signal b is expressed by the equation (3).
k1 = (first data of signal a change information) − (first data of signal b change information) = Qab (3)
Further, the change time information Qab of the signal b with respect to the signal a from time t = 0 to tend is expressed by Expression (4).

  If the function for taking out the value of the signal n from the waveform data 102 is N (t), the value of the signal a is A (t) and the value of the signal b is B (t). Further, let H be a function for converting the change time information Qmn (t) and the value N (t) at the time of change into an assertion description.

An assertion for the signals a and b from time t = 0 to tend is expressed by equation (5), and an assertion 107 for the waveform data shown in FIG. 3 is expressed by equation (6).

Assertion = signal b: if (rising of signal a) then change allowable range [k3 to k2] (signal b changes) (Expression 6)
It is.

Further, the assertion when there are a plurality of designation signals is expressed by Expression (7).

  In addition, the signal change of the verification reference signal and the verification target signal in FIG. 1 is clear, and the verification reference signal change information 104 and the verification target signal change information 105 can be generated without using the signal change information automatic generation unit 103. 4 are the verification reference signal change information 104 and the verification target signal change information 105 of FIG. In the assertion automatic generation unit 208, only the assertion automatic generation program 106 operates to generate the assertion 107.

The figure for demonstrating automatic generation of the assertion of this invention Flowchart of logic circuit design verification method according to the present invention The figure which illustrates the waveform data for demonstrating this invention Schematic diagram showing the verification environment for the changed circuit A 'in which the reference circuit A is changed Diagram showing conventional property automatic generation method Diagram showing assertion-based verification flow incorporating prior art

Explanation of symbols

101 Signal information
102 Waveform data
103 Automatic signal change information generator
104 Verification reference signal change information
105 Signal change information to be verified
106 Assertion generator
107 Assertion
201 User logic specifications
202 IP
203 Operation pattern
204 Circuit description
205 General specifications
206 Evaluation pattern
207 IP after change
208 IP

Claims (4)

In an automatic assertion generation device that generates an assertion as a checker when a new logic circuit is designed using a verification reference circuit and the circuit is a verification target circuit,
A signal information file storing signal information which is signal name information in each of the verification target circuit and the verification reference circuit;
A waveform data file storing operation waveform data which is information indicating a level transition of a signal appearing in an evaluation pattern of the verification target circuit among the operation patterns of the verification reference circuit;
A signal change information automatic generation unit for generating signal change information for each of the verification target signal and the corresponding verification reference signal from the signal information file and the waveform data file;
An assertion automatic generation apparatus, comprising: an assertion generation unit that inputs the signal change information and generates an assertion that is a description expressing a functional specification or design intention of a logic circuit. The signal change information includes a value at a predetermined time of a first function Tn (t) for extracting a time at which the value of the signal n has transitioned from the operation waveform data, and a value at the time of transition of the signal n as the operation waveform. A value of a second function N (t) for extracting from the data at a predetermined time,
The assertion generation unit includes a value Na (t) of the second function of the verification reference signal a, a value Nb (t) of the second function for the verification target signal b corresponding to the verification reference signal a, and a verification reference. A function H for converting the value Qab (t) of the third function as change time information obtained from the relative difference between the first function value of the signal a and the signal to be verified b into an assertion description as a variable. The assertion automatic generation apparatus according to claim 1, wherein the assertion is generated. An assertion automatic generation method for generating an assertion as a checker when a new logic circuit is designed using a verification reference circuit and the circuit is a verification target circuit,
A verifier prepares signal information which is information of a verification reference signal name in the verification reference circuit corresponding to the verification target signal name in the user logic specification of the verification target circuit;
Creating an evaluation pattern, which is a test pattern created based on the user logic specification;
By executing the operation pattern of the verification reference circuit, based on the evaluation pattern and the circuit description of the verification reference circuit, operation waveform data which is information indicating a level transition of a signal appearing in the evaluation pattern in the operation pattern Generating stage,
A method for automatically generating an assertion, comprising: automatically generating an assertion based on the signal information and the operation waveform data. A logic circuit design verification method using an assertion generated by the assertion automatic generation method according to claim 3,
Grasping a new specification based on the user logic specification and a summary specification of the verification reference circuit, and determining whether or not there is a circuit change from the circuit description and the generated assertion based on the new specification; and
Changing the verification reference circuit if there is a circuit change; and
Verifying the verification target circuit using the evaluation pattern and the generated assertion based on the verification reference circuit;
If the verification result is not OK, the logic circuit design verification method includes a step of returning to grasping the specification, creating a verification reference circuit after the change, and performing verification again.

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