CN116631867B - Preparation method of groove Schottky diode - Google Patents
Preparation method of groove Schottky diode Download PDFInfo
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- CN116631867B CN116631867B CN202310449929.1A CN202310449929A CN116631867B CN 116631867 B CN116631867 B CN 116631867B CN 202310449929 A CN202310449929 A CN 202310449929A CN 116631867 B CN116631867 B CN 116631867B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims abstract description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 21
- 238000002955 isolation Methods 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 18
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- 150000002500 ions Chemical class 0.000 claims abstract description 9
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- 238000011049 filling Methods 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 238000001039 wet etching Methods 0.000 claims description 11
- 238000001312 dry etching Methods 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 238000005036 potential barrier Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 230000005684 electric field Effects 0.000 description 5
- IYYIVELXUANFED-UHFFFAOYSA-N bromo(trimethyl)silane Chemical compound C[Si](C)(C)Br IYYIVELXUANFED-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses a preparation method of a novel groove Schottky diode, which comprises the following steps: providing a substrate, sequentially growing an epitaxial layer, a first dielectric layer and a second dielectric layer on the substrate, defining a groove position on the dielectric layer through photoresist, and etching a groove reaching the epitaxial layer; transversely etching the first dielectric layers at the two sides of the opening of the groove to expose the table-boards of the epitaxial layers at the two sides of the opening; removing the second dielectric layer, and performing ion implantation on the table top and the bottom of the groove to form a doped region; removing the first dielectric layer, growing a gate oxide layer on the integral structure, depositing polysilicon and filling the trench; growing an isolation layer on the gate oxide layer, etching to form a barrier region, and then implanting ions into the barrier region to form a lightly doped region; sequentially depositing a Schottky barrier metal layer and an anode metal layer on the isolation layer and the barrier region; and finally, depositing a cathode metal layer on the bottom surface of the substrate. The invention effectively improves the reverse breakdown voltage of the device and reduces the reverse leakage current and the forward voltage drop.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a novel groove Schottky diode.
Background
The TMBS rectifying device is provided with a groove structure, an insulating layer is arranged on the inner wall of the groove, and conductive materials are filled in the groove, so that a groove MOS structure is formed, and the groove MOS structure surrounds the Schottky barrier junction. When the device is connected with reverse bias, the groove MOS structure is beneficial to reducing the electric field intensity of the Schottky surface, and the effect that the barrier height of the Schottky barrier junction is reduced along with the increase of the reverse bias is restrained.
The structure of a conventional TMBS exists: 1. in reverse bias, the depletion layer at the bottom of the trench has no effect of increasing the width of the depletion layer caused by expanding the lateral depletion layer, so that a large electric field exists at the bottom of the trench, and reverse breakdown of the conventional trench TMBS structure usually occurs at the position; 2. in the manufacturing process, a local silicon dioxide layer on the side surface of the top of the mesa is easy to damage, so that the reverse leakage current of the device is large.
Disclosure of Invention
In order to solve the technical problems in the prior art, the invention discloses a preparation method of a novel trench Schottky diode, which comprises the following specific technical scheme:
A preparation method of a novel trench Schottky diode comprises the following steps:
step one, providing a substrate of a first conductivity type, sequentially growing an epitaxial layer and a dielectric layer on the substrate, defining a groove position on the dielectric layer through photoresist, and etching a groove reaching the epitaxial layer;
The dielectric layers comprise a first dielectric layer and a second dielectric layer;
Step two, adopting wet etching, and transversely etching the first dielectric layers at the two sides of the opening of the groove to expose the table-boards of the epitaxial layers at the two sides of the opening;
Removing the second dielectric layer by wet etching, and implanting ions of a second conductivity type into the table surface and the bottom of the groove by an ion implantation method to form a doped region of the second conductivity type;
step four, after removing the first dielectric layer by wet etching, a gate oxide layer grows on the surface of the epitaxial layer, the bottom surface and the side wall of the groove, and then polysilicon is deposited and the groove is filled;
step five, growing an isolation layer on the gate oxide layer, etching the isolation layer to form a barrier region, injecting second conductivity type ions into the barrier region, and forming a second conductivity type lightly doped region after annealing;
step six, depositing a Schottky barrier metal layer on the isolation layer and the barrier region, and depositing an anode metal layer on the top surface of the Schottky barrier metal layer;
And step seven, grinding the bottom surface of the substrate, and completing the preparation of the novel groove Schottky diode after depositing the cathode metal layer on the bottom surface of the substrate.
Further, the first conductivity type is N type, and the second conductivity type is P type; the substrate is a heavily doped semiconductor substrate, and the epitaxial layer is a lightly doped semiconductor epitaxial layer of a first conductivity type; the first dielectric layer is specifically a silicon nitride layer, and the second dielectric layer is specifically a silicon dioxide layer.
Further, in the first step, a trench position is defined in the dielectric layer by photoresist, and then a trench reaching the epitaxial layer is etched, specifically: coating photoresist on the dielectric layer, defining a groove pattern through the photoresist, and determining the position of the groove; removing the dielectric layer which is not protected by the photoresist by dry etching to expose the epitaxial layer, etching a groove window immediately, removing the photoresist, and taking the remained dielectric layer as a hard mask; and taking the hard mask as protection, adopting dry etching, and etching the exposed epitaxial layer by utilizing the groove window to form a groove in the epitaxial layer.
Further, the depositing polysilicon in the fourth step and filling the trench specifically includes: and depositing doped polysilicon in the groove and filling the doped polysilicon to cover the gate oxide layer in the groove and the doped region of the second conductivity type, and removing the doped polysilicon by adopting dry etching if the polysilicon overflows the groove.
Further, in the fifth step, a barrier region is etched on the isolation layer, specifically: coating photoresist on the isolation layer, defining an opening position through the photoresist, and etching an opening window to form a potential barrier region; wherein the isolation layer is made of insulating materials.
The invention has the advantages that:
1. The electric field distribution at the bottom of the groove is effectively improved, and because the P-type doped region is formed at the bottom of the groove, which is equivalent to adding a PN structure at the bottom of the groove, the purposes of expanding the electric field and improving the peak electric field at the right-angle corner of the bottom of the groove are achieved when the device is reversely depleted, and the reverse breakdown voltage is improved;
2. the P-type doped region is formed on two sides of the potential barrier source region in an ion implantation mode, so that reverse leakage current is reduced;
3. And a P-type lightly doped region is formed in the ion implantation mode of the potential barrier source region, so that reverse leakage and forward voltage drop are reduced.
Drawings
FIG. 1 is a schematic cross-sectional view of a trench formed after an epitaxial layer and two dielectric layers are sequentially grown on a substrate in step one in an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of a second embodiment of the present invention after performing a lateral wet etching on a silicon nitride layer on both sides of a trench opening;
FIG. 3 is a schematic cross-sectional view of a third embodiment of the present invention after removing the silicon dioxide layer and implanting P-type ions to form a P-type doped region;
FIG. 4 is a schematic cross-sectional view of a gate oxide layer grown entirely after removal of a silicon nitride layer in step four according to an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of a P-type lightly doped region formed by growing an isolation layer and implanting P-type ions into the formed barrier region in step five according to an embodiment of the present invention;
Fig. 6 is a schematic cross-sectional view of an embodiment of the present invention after sequentially depositing a schottky barrier metal layer and an anode metal layer in step six;
FIG. 7 is a schematic cross-sectional view of a substrate having a cathode metal layer deposited on the bottom surface thereof after a seventh step in an embodiment of the present invention;
In the figure, a 1-substrate, a 2-epitaxial layer, a 3-silicon nitride layer, a 4-silicon dioxide layer, a 5-trench, a 6-P type doped region, a 7-gate oxide layer, 8-polysilicon, a 9-isolation layer, a 10-P type lightly doped region, a 11-Schottky barrier metal layer, a 12-anode metal layer and a 13-cathode metal layer.
Detailed Description
In order to make the objects, technical solutions and technical effects of the present invention more apparent, the present invention will be further described in detail with reference to the drawings and examples of the specification.
The preparation method of the novel groove Schottky diode provided by the embodiment of the invention comprises the following steps:
Step one, providing an N-type heavily doped semiconductor substrate 1, and growing an N-type lightly doped epitaxial layer 2 on the substrate 1; sequentially growing two dielectric layers on the epitaxial layer 2, namely a silicon nitride layer 3 of a first dielectric layer and a silicon dioxide layer 4 of a second dielectric layer; then coating photoresist on the dielectric layer, defining a groove pattern on the dielectric by the photoresist, and determining the position of the groove etched in the subsequent step; then selectively removing the dielectric layer which is not protected by the photoresist through dry etching, immediately etching a groove window, removing the photoresist, and taking the remained dielectric layer as a hard mask; with the hard mask as protection, dry etching is adopted, and the exposed epitaxial layer 2 is etched by using the trench window, so that a trench 5 is formed in the epitaxial layer 2, as shown in fig. 1.
And step two, wet etching is adopted, and the silicon nitride layers 3 at the two sides of the opening of the groove 5 are etched by utilizing the transverse etching action of the wet etching, so that the table tops of the epitaxial layers 2 at the two sides of the opening are exposed, as shown in fig. 2.
Step three, removing the silicon dioxide layer 4 by wet etching; the ion implantation method is adopted to implant the exposed mesa and the bottom of the trench 5, and P-type ions are implanted to form a P-type doped region 6, so that the reverse leakage current can be reduced, as shown in fig. 3.
Removing the silicon nitride layer 3 by wet etching, and then growing a gate oxide layer 7 on the whole structure, specifically on the surface of the epitaxial layer 2, the bottom surface and the side wall of the groove 5 to form the gate oxide layer 7;
doped polysilicon 8 is then deposited in the trench 5 and filled to cover the gate oxide 7 in the trench 5 and the P-doped region 6, and if there is an overflow, is selectively removed by dry etching, as shown in fig. 4.
Step five, growing an isolation layer 9 on the gate oxide layer 7, wherein the isolation layer 9 is made of an insulating material;
coating photoresist on the isolation layer 9, defining an opening position through the photoresist to form a potential barrier region; the barrier region is implanted, P-type ions are implanted, and a low-doped P-type lightly doped region 10 is formed in the barrier region after annealing, so that reverse leakage and forward voltage drop can be reduced, as shown in fig. 5.
Step six, a schottky barrier metal layer 11 is deposited on the isolation layer 9 and the barrier region, and an anode metal layer 12 is deposited on the top surface of the schottky barrier metal layer 11, as shown in fig. 6.
Step seven, grinding the bottom surface of the substrate 1, and completing the preparation after depositing the cathode metal layer 13 on the bottom surface of the substrate 1, as shown in fig. 7.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the foregoing detailed description of the invention has been provided, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing examples, and that certain features may be substituted for those illustrated and described herein. Modifications, equivalents, and alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (4)
1. The preparation method of the trench Schottky diode is characterized by comprising the following steps of:
step one, providing a substrate of a first conductivity type, sequentially growing an epitaxial layer and a dielectric layer on the substrate, defining a groove position on the dielectric layer through photoresist, and etching a groove reaching the epitaxial layer;
The dielectric layers comprise a first dielectric layer and a second dielectric layer;
Step two, adopting wet etching, and transversely etching the first dielectric layers at the two sides of the opening of the groove to expose the table-boards of the epitaxial layers at the two sides of the opening;
Removing the second dielectric layer by wet etching, and implanting ions of a second conductivity type into the table surface and the bottom of the groove by an ion implantation method to form a doped region of the second conductivity type;
step four, after removing the first dielectric layer by wet etching, a gate oxide layer grows on the surface of the epitaxial layer, the bottom surface and the side wall of the groove, and then polysilicon is deposited and the groove is filled;
Step five, growing an isolation layer on the gate oxide layer, etching the isolation layer to form a barrier region, injecting second conductivity type ions into the barrier region, and forming a second conductivity type lightly doped region after annealing; forming a barrier region on the isolation layer by etching, specifically: coating photoresist on the isolation layer, defining an opening position through the photoresist, and etching an opening window to form a potential barrier region; wherein the isolation layer is made of insulating materials;
step six, depositing a Schottky barrier metal layer on the isolation layer and the barrier region, and depositing an anode metal layer on the top surface of the Schottky barrier metal layer;
And step seven, grinding the bottom surface of the substrate, and completing the preparation of the groove Schottky diode after depositing the cathode metal layer on the bottom surface of the substrate.
2. The method of fabricating a trench schottky diode of claim 1 wherein said first conductivity type is N-type and said second conductivity type is P-type; the substrate is a heavily doped semiconductor substrate, and the epitaxial layer is a lightly doped semiconductor epitaxial layer of a first conductivity type; the first dielectric layer is specifically a silicon nitride layer, and the second dielectric layer is specifically a silicon dioxide layer.
3. The method for manufacturing a trench schottky diode according to claim 1, wherein in the first step, a trench position is defined in a dielectric layer by photoresist, and then a trench reaching an epitaxial layer is etched, specifically: coating photoresist on the dielectric layer, defining a groove pattern through the photoresist, and determining the position of the groove; removing the dielectric layer which is not protected by the photoresist by dry etching to expose the epitaxial layer, etching a groove window immediately, removing the photoresist, and taking the remained dielectric layer as a hard mask; and taking the hard mask as protection, adopting dry etching, and etching the exposed epitaxial layer by utilizing the groove window to form a groove in the epitaxial layer.
4. The method of manufacturing a trench schottky diode of claim 1, wherein the depositing polysilicon in the fourth step fills the trench, specifically: and depositing doped polysilicon in the groove and filling the doped polysilicon to cover the gate oxide layer in the groove and the doped region of the second conductivity type, and removing the doped polysilicon by adopting dry etching if the polysilicon overflows the groove.
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| CN202310449929.1A CN116631867B (en) | 2023-04-25 | 2023-04-25 | Preparation method of groove Schottky diode |
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| CN202310449929.1A CN116631867B (en) | 2023-04-25 | 2023-04-25 | Preparation method of groove Schottky diode |
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| CN116631867B true CN116631867B (en) | 2024-07-30 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9059147B1 (en) * | 2014-03-22 | 2015-06-16 | Alpha And Omega Semiconductor Incorporated | Junction barrier schottky (JBS) with floating islands |
| CN111081754A (en) * | 2018-10-19 | 2020-04-28 | 宁波比亚迪半导体有限公司 | Groove type MOS structure Schottky diode and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7238976B1 (en) * | 2004-06-15 | 2007-07-03 | Qspeed Semiconductor Inc. | Schottky barrier rectifier and method of manufacturing the same |
| US8502336B2 (en) * | 2011-05-17 | 2013-08-06 | Semiconductor Components Industries, Llc | Semiconductor diode and method of manufacture |
| DE102013204701A1 (en) * | 2013-03-18 | 2014-10-02 | Robert Bosch Gmbh | Pseudo-Schottky diode |
| KR101737966B1 (en) * | 2015-12-24 | 2017-05-29 | 주식회사 시지트로닉스 | Semiconductor element and method thereof using hetero tunneling junction |
| US10680095B2 (en) * | 2018-06-15 | 2020-06-09 | Semiconductor Components Industries, Llc | Power device having super junction and schottky diode |
| US20200321477A1 (en) * | 2019-04-04 | 2020-10-08 | AZ Power, Inc | Multi-schottky-layer trench junction barrier schottky diode and manufacturing method thereof |
| US20200321478A1 (en) * | 2019-04-05 | 2020-10-08 | AZ Power, Inc | Trench junction barrier schottky diode with voltage reducing layer and manufacturing method thereof |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9059147B1 (en) * | 2014-03-22 | 2015-06-16 | Alpha And Omega Semiconductor Incorporated | Junction barrier schottky (JBS) with floating islands |
| CN111081754A (en) * | 2018-10-19 | 2020-04-28 | 宁波比亚迪半导体有限公司 | Groove type MOS structure Schottky diode and preparation method thereof |
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