CN107359209B - Semiconductor device and corresponding manufacturing method - Google Patents
Semiconductor device and corresponding manufacturing method Download PDFInfo
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- CN107359209B CN107359209B CN201710623403.5A CN201710623403A CN107359209B CN 107359209 B CN107359209 B CN 107359209B CN 201710623403 A CN201710623403 A CN 201710623403A CN 107359209 B CN107359209 B CN 107359209B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000009792 diffusion process Methods 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000002513 implantation Methods 0.000 claims abstract description 15
- 238000005468 ion implantation Methods 0.000 claims description 52
- 238000005530 etching Methods 0.000 claims description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 10
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 238000009826 distribution Methods 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims 2
- 238000007254 oxidation reaction Methods 0.000 claims 2
- 238000005516 engineering process Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910000070 arsenic hydride Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- IYYIVELXUANFED-UHFFFAOYSA-N bromo(trimethyl)silane Chemical compound C[Si](C)(C)Br IYYIVELXUANFED-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
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- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
Abstract
The invention discloses a semiconductor device and a corresponding manufacturing method, which are used for solving the problem of reducing the conduction voltage drop of the semiconductor device under the condition of not improving the electric leakage of the semiconductor device. The method comprises the following steps: implanting an ion source in a predetermined implantation region of a semiconductor substrate; enabling the ion source to enter a preset JFET area through thermal diffusion; a trench structure is etched in the semiconductor substrate where the thermal diffusion is completed, thereby forming a semiconductor device.
Description
Technical Field
The present invention relates to semiconductor technology, and more particularly, to a semiconductor device and a corresponding manufacturing method.
Background
Schottky diodes are unipolar carrier devices that use electrons as carriers and are widely used in switching power supplies and other devices requiring high-speed power switching due to their lower turn-on voltage drop and faster switching frequency.
The conventional TMBS (trench gate Schottky diode) device is widely applied, the characteristics of the Schottky device are improved, and the phenomenon that the Schottky generates larger leakage current at high voltage due to the barrier reduction effect of the Schottky is particularly improved. However, the bulk silicon resistivity of the conventional high-voltage trench gate schottky diode is very large, the higher the withstand voltage of the device is, the larger the required bulk silicon resistivity is, and thus, the forward conduction voltage drop of the device is larger. How to make the schottky diode obtain higher voltage and have lower forward voltage drop is a problem that needs to be solved at present.
Disclosure of Invention
In order to overcome the above-mentioned drawbacks, the present invention provides a semiconductor device and a corresponding manufacturing method, so as to solve the problem of reducing the turn-on voltage drop of the semiconductor device without increasing the leakage current of the semiconductor device.
In order to solve the above technical problem, a method for manufacturing a semiconductor device in the present invention includes:
implanting an ion source in a predetermined implantation region of a semiconductor substrate;
enabling the ion source to enter a preset JFET area through thermal diffusion;
a trench structure is etched in the semiconductor substrate where the thermal diffusion is completed, thereby forming a semiconductor device.
In order to solve the technical problem, the semiconductor device provided by the invention is provided with a trench structure, and a body silicon region between any adjacent trenches in the trench structure forms a JFET region; the JFET region has ion source doping.
The invention has the following beneficial effects:
the method and the semiconductor device can reduce the conduction voltage drop of the semiconductor device under the condition of not improving the electric leakage of the semiconductor device.
Drawings
Fig. 1 is a flowchart of a method of manufacturing a semiconductor device in an embodiment of the present invention;
FIGS. 2-9 are schematic structural views of stages in the fabrication of a semiconductor device in an embodiment of the present invention;
FIG. 10 is a schematic illustration of a lateral doping profile of the doped N layer 5 in an embodiment of the present invention;
fig. 11 is a schematic diagram of electrical characteristics of a conventional semiconductor device, a globally ion-implanted semiconductor device, and a semiconductor device according to an embodiment of the present invention.
Detailed Description
In order to solve the problem of reducing the turn-on voltage drop of a semiconductor device without increasing the leakage current of the semiconductor device, the present invention provides a semiconductor device and a corresponding manufacturing method, and the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
Example one
As shown in fig. 1, an embodiment of the present invention provides a method for manufacturing a semiconductor device, the method including:
s101, implanting an ion source into a preset implantation area of a semiconductor substrate;
s102, enabling the ion source to enter a preset JFET area through thermal diffusion;
and S103, etching a groove structure on the semiconductor substrate subjected to the thermal diffusion to form the semiconductor device.
According to the embodiment of the invention, an ion source is injected into a preset injection region of a semiconductor substrate; enabling the ion source to enter a preset JFET area through thermal diffusion; a trench structure is etched in a semiconductor substrate on which thermal diffusion is performed, thereby reducing the turn-on voltage drop of the semiconductor device without increasing the leakage current of the semiconductor device.
Wherein the semiconductor substrate is a basic material for manufacturing a semiconductor device.
That is to say, the embodiment of the invention adopts the local ion implantation technology, and adopts the ion implantation technology in the non-metal and silicon contact area, namely the groove area, so that the doped impurities enter the JFET area through thermal diffusion, the purpose of adjusting the resistance of the JFET area is achieved, and the conduction voltage drop of the device is further reduced.
For example, when the trench gate schottky diode is in forward conduction, the whole bulk silicon in the MESA region participates in current transmission, and the high-concentration ion implantation technology is adopted in the JFET region, so that the on-resistance of the region can be remarkably reduced, and the on-voltage drop of the device is further reduced.
On the basis of the above-described embodiment, a modified embodiment of the above-described embodiment is further proposed, and it is to be noted herein that, in order to make the description brief, only the differences from the above-described embodiment are described in each modified embodiment.
Prefixes such as "first", "second", and the like for distinguishing components used in the embodiments of the present invention are used only for facilitating the description of the present invention, and have no specific meaning in themselves.
Optionally, the implanting an ion source in a predetermined implantation region of a semiconductor substrate includes:
as shown in fig. 2, a first oxide layer 1 is grown on an epitaxial layer 2 of the semiconductor substrate;
as shown in fig. 3, according to the implantation region, performing photolithography on the first oxide layer 1 to form a barrier layer 20;
and implanting an ion source in the implantation region according to the barrier layer.
Further, the enabling the ion source to enter the preset JFET area through thermal diffusion comprises the following steps:
as shown in fig. 4, a semiconductor substrate implanted with an ion source is subjected to thermal annealing and junction pushing, a second oxide layer 4 is grown in the junction pushing process, and an N-doped layer 5 is formed between the second oxide layer 4 and the epitaxial layer 2, so that the ion source enters the JFET region.
Wherein the doped N layer has a doping source with Gaussian distribution in both longitudinal and transverse directions; the doping concentration of the N-doped layer is greater than that of the epitaxial layer; the ion source comprises an N-type doping source and a P-type doping source; the injection energy of the ion source is between 30 and 120KEV, and the injection dose of the ion source is 1011～1013cm-2To (c) to (d); the thickness of the second oxide layer is greater than the thickness of the first oxide layer.
Optionally, the implantation region comprises at least one ion implantation window;
further, the etching of the trench structure on the semiconductor substrate where the thermal diffusion is completed includes:
determining the central position and the window area of each ion implantation window;
etching a trench structure on the semiconductor substrate on which the thermal diffusion is completed, based on the central position of each ion implantation window and the window region; and the body silicon region between any adjacent trenches in the trench structure forms the JFET region.
Further, the etching of a trench structure in a semiconductor substrate subjected to thermal diffusion in accordance with the center position of each ion implantation window and the window region includes:
for each ion implantation window:
taking the central position of the ion implantation window as the central position of a groove etching window of a corresponding groove;
determining a window area of a groove etching window of the corresponding groove according to the window area of the ion implantation window;
corresponding trenches are etched in the semiconductor substrate where the thermal diffusion is completed, based on the central position of the trench etching window and the window area.
Wherein the width of the window area of the trench etching window is larger than that of the window area of the ion implantation window.
Examples of the present invention are illustrated.
The embodiment of the invention provides a method for manufacturing an optional low-voltage-drop trench gate Schottky diode, which comprises the following steps:
And 3, performing thermal annealing and pushing, and growing a layer of thick oxide layer 4 in the junction pushing process at the same time, as shown in fig. 4. And forming a medium doped N layer 5 on the low doped epitaxial layer 2, wherein the longitudinal doping distribution of the medium doped N layer 5 is Gaussian distribution, and as a local ion implantation process is adopted, the peak point of the transverse doping concentration of the doped N layer 5 appears in the middle of an ion implantation window, and the middle part of an unimplanted area appears at the bottom of the peak value.
And 4, photoetching a first-time groove structure on the semiconductor substrate, taking the thick oxide layer 4 as an etching barrier layer, wherein the etched groove structure is shown in fig. 5, an etching window of the semiconductor groove is overlapped with the center of the ion implantation window as shown in fig. 6, the width of the etching window of the groove is larger than that of the ion implantation window, and the depth of the groove of the semiconductor substrate is not necessarily larger than that of the highly-doped N layer 5.
And 5, growing a gate oxide layer 6 on the semiconductor substrate, wherein the thickness of the gate oxide layer is determined by the withstand voltage of the device, then carrying out polysilicon deposition and reverse etching to form a polysilicon layer 7 which is shown in figure 7 and is remained in the groove after the reverse etching.
A passivation layer 8, which may be silicon nitride or silicon dioxide, is deposited on the semiconductor structure, and then an active region 12 is etched by hole lithography, as shown in fig. 8, where the passivation layer 8 still covers the termination region 11.
And sputtering a metal layer 9 on the semiconductor structure, then photoetching and etching, and finally forming the semiconductor device with the shape as shown in FIG. 9.
Wherein, the lateral doping profile of the N-doped layer 5 in step 3 is shown in fig. 10.
The method of the embodiment of the invention is to carry out a layer of ion implantation on the surface before the etching process of the wafer groove.
In the embodiment of the invention, the photoresist is used as the ion implantation barrier layer of the non-implantation area.
In the embodiment of the invention, the ion source can be an N-type doping source PH3、AsH3Or can be a P-type doping source BF3、BCl3The ion implantation energy is 30-120 KEV, and the ion implantation dosage is 1011～1013cm-2In the meantime.
In the embodiment of the invention, the center position of the groove etching window is superposed with the center position of the ion implantation photoetching window, and the groove etching window is larger than the ion implantation window, so that the ion implantation surface can be effectively ensured to be etched.
The embodiment of the invention mainly carries out ion implantation in the edge area of the chip, forms a medium-doped N-type area with Gaussian distribution doping in the longitudinal direction and the transverse direction on the surface of the N-area of the epitaxial layer, simultaneously enables the center position of the groove etching window to be superposed with the center position of the ion implantation window, etches away the ion implantation area part when carrying out groove etching, and thus completely removes the lattice damage caused by the ion implantation to the silicon surface.
Taking 100V trench gate Schottky diode as an example, the electrical characteristics of a conventional device, a global ion implantation device and the local ion implantation device of the invention are simulated by device simulation software, and the global ion implantation dosage is 1013cm-2The implantation energy is 80KEV, and the local ion implantation dose is 2.5 x 10 in the embodiment of the invention13cm-2Energy 80KEV is injected. FIG. 11 is a plot of VF characteristics for three devices, from which it can be seen that a global ion implantation device andthe device provided by the invention has lower forward voltage drop, and meanwhile, the local ion implantation technology provided by the embodiment of the invention can effectively reduce the leakage current of the device.
Example two
As shown in fig. 2 to 9, the embodiment of the present invention provides a semiconductor device having a trench structure, in which a body silicon region between any adjacent trenches in the trench structure constitutes a JFET region; the JFET region has ion source doping.
Optionally, the semiconductor device comprises an epitaxial layer and a doped N layer 5 grown on the epitaxial layer 2; the trench structure is arranged in the epitaxial layer 2 and the N-doped layer 5.
The JFET area is provided with ion source doping with Gaussian distribution in the longitudinal direction and the transverse direction; the doping concentration of the N-doped layer is greater than that of the epitaxial layer; the ion source comprises an N-type doping source and a P-type doping source.
Further, a gate oxide layer 6 is grown on each trench of the trench structure and/or the doped N layer.
Wherein, the thickness of the gate oxide layer 6 is determined by the preset withstand voltage value of the semiconductor device.
Specifically, a polysilicon layer 7 is provided on the gate oxide layer 6 of each trench.
Optionally, the trench structure constitutes an active region 10 and a termination region 11.
Wherein the active region 10 is further provided with a passivation layer.
Wherein, the passivation layer is made of one or combination of the following materials: silicon nitride and silicon dioxide.
Optionally, the semiconductor device further comprises a metal layer 9.
According to the embodiment of the invention, the conduction voltage drop of the semiconductor device is effectively reduced under the condition that the electric leakage of the semiconductor device is not improved.
In the embodiment of the present invention, the semiconductor device may be manufactured by the method in the first embodiment, and thus the specific structure thereof may be described with reference to the first embodiment, which is not described herein again.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (4)
1. A method of manufacturing a semiconductor device, the method comprising:
implanting an ion source in a predetermined implantation region of a semiconductor substrate;
enabling the ion source to enter a preset JFET area through thermal diffusion;
etching a trench structure on the semiconductor substrate subjected to the thermal diffusion to form a semiconductor device;
the ion source is implanted into a preset implantation area of a semiconductor substrate, and comprises:
growing a first oxide layer on the epitaxial layer of the semiconductor substrate;
according to the injection region, photoetching is carried out on the first oxidation layer to form a barrier layer;
implanting an ion source in the implantation region according to the barrier layer;
the method for enabling the ion source to enter the preset JFET area through thermal diffusion comprises the following steps:
carrying out thermal annealing and junction pushing on the semiconductor substrate implanted with the ion source, growing a second oxide layer in the junction pushing process, and forming a doped N layer between the second oxide layer and the epitaxial layer so as to enable the ion source to enter the JFET region;
the implantation region comprises at least one ion implantation window;
the etching of a trench structure in a semiconductor substrate where thermal diffusion is completed includes:
determining the central position and the window area of each ion implantation window;
etching a trench structure on the semiconductor substrate on which the thermal diffusion is completed, based on the central position of each ion implantation window and the window region; the body silicon area between any adjacent grooves in the groove structure forms the JFET area;
the method for etching a trench structure in a semiconductor substrate on which thermal diffusion is completed, based on a central position of each ion implantation window and a window region, includes:
for each ion implantation window:
taking the central position of the ion implantation window as the central position of a groove etching window of a corresponding groove;
determining a window area of a groove etching window of the corresponding groove according to the window area of the ion implantation window;
etching a corresponding trench on the semiconductor substrate subjected to the thermal diffusion, based on the central position of the trench etching window and the window area;
wherein, the width of the window area of the groove etching window is larger than that of the window area of the ion implantation window;
the doped N layer is provided with a doping source with Gaussian distribution in the longitudinal direction and the transverse direction; the doping concentration of the N-doped layer is greater than that of the epitaxial layer; the ion source of the N-type device comprises an N-type doping source; the injection energy of the ion source is between 30 and 120KEV, and the injection dose of the ion source is 1011～1013cm-2To (c) to (d); the thickness of the second oxide layer is greater than the thickness of the first oxide layer.
2. A semiconductor device is characterized in that the semiconductor device is provided with trench structures, and bulk silicon regions between any adjacent trenches in the trench structures form JFET regions; the JFET region has ion source doping;
the JFET area doped with the ion source is prepared by the following steps:
growing a first oxide layer on the epitaxial layer of the semiconductor substrate;
photoetching the first oxidation layer according to a preset injection area to form a barrier layer;
implanting an ion source in the implantation region according to the barrier layer;
carrying out thermal annealing and junction pushing on the semiconductor substrate implanted with the ion source, growing a second oxide layer in the junction pushing process, and forming a doped N layer between the second oxide layer and the epitaxial layer so as to enable the ion source to enter the JFET region;
the implantation region comprises at least one ion implantation window;
etching a trench structure in a semiconductor substrate on which thermal diffusion is completed is made by: determining the central position and the window area of each ion implantation window; etching a trench structure on the semiconductor substrate on which the thermal diffusion is completed, based on the central position of each ion implantation window and the window region; the body silicon area between any adjacent grooves in the groove structure forms the JFET area;
the etching of the trench structure on the semiconductor substrate subjected to thermal diffusion according to the central position of each ion implantation window and the window region is made by: for each ion implantation window: taking the central position of the ion implantation window as the central position of a groove etching window of a corresponding groove; determining a window area of a groove etching window of the corresponding groove according to the window area of the ion implantation window; etching a corresponding trench on the semiconductor substrate subjected to the thermal diffusion, based on the central position of the trench etching window and the window area;
wherein, the width of the window area of the groove etching window is larger than that of the window area of the ion implantation window;
the doped N layer is provided with a doping source with Gaussian distribution in the longitudinal direction and the transverse direction; the doping concentration of the N-doped layer is greater than that of the epitaxial layer; the ion source of the N-type device comprises an N-type doping source; the injection energy of the ion source is between 30 and 120KEV, and the injection dose of the ion source is 1011～1013cm-2To (c) to (d); the thickness of the second oxide layer is greater than the thickness of the first oxide layer.
3. The semiconductor device of claim 2, wherein the semiconductor device comprises an epitaxial layer and a doped N layer grown on the epitaxial layer; the groove structure is arranged on the epitaxial layer and the N-doped layer.
4. The semiconductor device of claim 2, wherein the trench structure constitutes an active region and a termination region.
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| US8058685B2 (en) * | 2009-07-08 | 2011-11-15 | Force Mos Technology Co., Ltd. | Trench MOSFET structures using three masks process |
| CN103887168B (en) * | 2012-12-19 | 2017-03-01 | 竹懋科技股份有限公司 | The manufacture method of Schottky rectifier cell and forming method |
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Effective date of registration: 20240407 Address after: 323000, No. 122 Qibaiyang Street, Nanmingshan Street, Liandu District, Lishui City, Zhejiang Province Patentee after: Zhejiang Guangxin Microelectronics Co.,Ltd. Country or region after: China Address before: 518054 6A02, maikelon building, 6 Gaoxin South Road, Nanshan District, Shenzhen City, Guangdong Province Patentee before: GUANGWEI INTEGRATION TECHNOLOGY (SHENZHEN) CO.,LTD. Country or region before: China |