JPH11274521A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce forward direction loss and backward direction loss while restraining chip size, by forming trench parts turning Schottky junction parts between first diffusion layers of a second conductivity type into recessed forms. SOLUTION: In this diode, an N<-> epitaxial Si layer 12 is grown on, e.g. an N<+> Si substrate 11, and barrier metal 22 is formed on the layer 12. An ohmic electrode 23 is formed on the opposite surface of the substrate 11. A plurality of recessed parts 15 are formed in the N<-> epitaxial Si layer 12. P<+> diffusion layers 17 are formed around the recessed parts 15. Poly crystalline Si is buried in the recessed parts 15. Trench parts 19 are formed in the N<-> type semiconductor region between the P<+> regions 17. The barrier metal layer 22 is formed on the trench part 19. Around the lower end portions of the trench parts 19, P<+> diffusion regions 21 are formed and protrude from the bottom end portions to the N<-> epitaxial Si layer 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device comprising a Schottky junction device comprising a semiconductor and a barrier metal, and a method of manufacturing the same. More particularly, the present invention relates to a method for reducing a power loss by suppressing a forward voltage drop. The present invention relates to a semiconductor device capable of reducing a reverse current and a method of manufacturing the same.

[0002]

2. Description of the Related Art It is generally known that when a metal and a semiconductor are brought into contact, a potential barrier is generated to exhibit a rectifying action. A Schottky barrier diode that utilizes this property has a very high response speed because only a majority carrier of a semiconductor is involved in a current flowing through this diode. Therefore, the diode is suitable for high-speed switching and high-frequency operation.

FIG. 7A is a basic sectional structural view of a Schottky barrier diode, which is a basic structure of a Schottky barrier diode in which a barrier metal layer 102 is bonded on an N− type semiconductor 101.

As a structure for reducing the reverse leakage current of such a Schottky barrier diode, for example, FIG.
(B) and FIG. 7 (c).

FIG. 7B is a cross-sectional structural view of a first conventional Schottky barrier diode, in which an acceptor is diffused from the surface of an N− type semiconductor 101 to form a P + type region 103. is there.

In this diode, a plurality of P + diffusion layers 103 are formed in a stripe shape at predetermined intervals on an N-epitaxial Si layer 101 grown on an N + Si substrate (not shown). Furthermore, N-epitaxial Si
A Schottky barrier electrode 102 (anode side) is provided on the layer 101, and an ohmic electrode (cathode side) is provided below the N + Si substrate.

In the diode having such a structure, the Schottky barrier electrode 102 and the N-epitaxial Si
The Schottky barrier generated at the contact portion with the layer 101 causes the Schottky barrier electrode 102 and the ohmic electrode 7
When a forward voltage is applied during this time, electrons in the N-epitaxial Si layer 101 having a high energy level are injected toward the Schottky barrier electrode 102 and a forward current flows, but a reverse voltage is applied. In this case, the Schottky barrier electrode 102
-Electrons are prevented from moving to the epitaxial Si layer 101, and the reverse current becomes a small and small amount regardless of the applied voltage. Thus, this diode has a rectifying action.

Next, a method of manufacturing the diode shown in FIG. 7B will be described.

N-epitaxial Si on an N + Si substrate
After growing the layer 101, a Si oxide film is formed to a thickness of about 100 nm. Subsequently, after a stripe-shaped opening having a width of about 1 μm is formed in the Si oxide film by photolithography, impurities are ion-implanted at a depth of about 200 nm so that the impurity distribution has a peak. Then, after forming a P + diffusion layer 103 having a depth of 2 μm on the N-epitaxial Si layer 101 by heat treatment, the Si oxide film is removed and N + S
A Schottky barrier electrode 102 is formed on an i-substrate by N + Si
An ohmic electrode is formed below the substrate.

However, when a diode is manufactured by the above-described manufacturing method, the diffusion of impurities into Si usually occurs in the lateral direction at a rate of about 0.8 times the depth direction regardless of the type of impurities to be ion-implanted. To proceed, P + diffusion layer 1
When the impurity is diffused to a depth of 2 μm at the time of forming 03, the impurity is diffused to the left and right by 1.6 μm in the horizontal direction, and as a result, the diffusion width in the horizontal direction is 3.2 μm.
In other words, when the opening width of 1 μm is combined, the diffusion width in the horizontal direction is 4.2 μm as a whole, and the diffusion proceeds 4.2 times the ideal value of 1 μm, and the lateral width of the P + diffusion layer 103 becomes too large. was there.

To solve this problem, a Schottky barrier diode having a structure as shown in FIG. 7C has been proposed.

FIG. 7C is a cross-sectional view of a Schottky barrier diode according to a second conventional example. After a trench 110 is formed on the surface of an N- type semiconductor 101, polysilicon containing an acceptor is buried. P + type region 1 around it
11 is formed. According to this structure, the width of the P + diffusion layer can be reduced.

According to the structures shown in FIGS. 7 (b) and 7 (c), N-epitaxial Si
The depletion layer extending to the layer 101 side is closer to a pinch-off state than the structure in FIG. 7A, and as shown in FIG. 8, an effect of reducing the reverse leakage current is obtained as compared with the structure in FIG.

FIG. 8 is a graph showing the reverse leakage current characteristics of the above conventional example.

The horizontal axis is the reverse voltage V, and the vertical axis is the leak current I. In the figure, Q1 is a characteristic curve of the diode having the structure of FIG. 7A, and Q2 is a characteristic curve of the diode having the structure of FIGS. 7B and 7C (first and second conventional examples).

As is apparent from FIG. 7, when the reverse voltage is increased, the structure shown in FIG.
In the structures (b) and (c), the current I is suppressed, and the reverse leakage current is reduced.

As a Schottky barrier diode showing a specific example of the above-mentioned first and second conventional examples, there is one disclosed in, for example, JP-A-3-105975.

FIG. 9 is a sectional structural view of the Schottky barrier diode disclosed in the above publication.

In this diode, for the purpose of reducing the loss, a P + type region 204 is formed in the Schottky junction at the interval and depth at which the depletion layer is pinched off to reduce the reverse leakage current. That is, the distance between the P + -type regions 204 is W, the depth of the P + -type regions 204 is D,
When the width of the depletion layer that spreads to the N− semiconductor layer 202 due to the diffusion potential of the PN junction formed between the P + type region 02 and the P + type region 204 is Wo, P + satisfies the relationship of 2Wo <W ≦ 3D. A mold region 204 is formed. In the figure, 201 is an ohmic electrode, 202 is an N + semiconductor substrate, 2
05 is a Schottky barrier electrode.

[0020]

However, in the Schottky barrier diodes (FIG. 9) of the above-mentioned prior art including the first and second prior arts, the Schottky junction area within the same chip area is reduced. The forward voltage loss increases. In order to suppress this, it is conceivable to extend the joint area in the horizontal direction, but this will increase the chip size and increase the price, and it will be installed in small envelopes where needs are growing Becomes difficult.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor device which realizes a reduction in forward loss and reverse loss while suppressing a chip size, and a method of manufacturing the same. Is to provide a way.

[0022]

According to a first aspect of the present invention, there is provided a semiconductor device having a semiconductor layer of a first conductivity type and electrodes sandwiching the semiconductor layer. Forming a recess in the plurality of regions, and forming a second portion inside the plurality of recesses.
In a semiconductor device having a buried layer of conductivity type and a first diffusion layer of second conductivity type formed around the buried layer, a Schottky junction between the first diffusion layers of each second conductivity type is recessed. That is, a trench portion to be formed is provided.

According to the first aspect of the invention, the Schottky junction area is increased by forming the flat Schottky junction into a concave shape. As a result, the forward loss is reduced.

According to a second aspect of the present invention, in the first aspect, a second conductive type second diffusion layer is provided on the first conductive type semiconductor layer around a bottom end of the trench. is there.

According to the second aspect, the electric field intensity is reduced, and the reverse loss is reduced.

A feature of the third invention is that the first invention is characterized in that the first
A first step of forming a conductive semiconductor layer, a second step of removing a plurality of predetermined regions of the first conductive semiconductor layer to form a plurality of first concave portions, A buried layer having a higher impurity diffusion rate than the semiconductor layer is formed in each of the first layers.
Forming a second conductive type semiconductor layer around each first concave portion by performing impurity diffusion after forming the second conductive type diffusion layer, and forming the first conductive layer between the second conductive type diffusion layers. A fourth step of forming a second recess in the conductive semiconductor layer region;
A step of forming a barrier metal on the surface of the semiconductor layer of the first conductivity type so as to fill the second concave portion.

According to a fourth aspect of the present invention, in the third aspect, the sixth step of diffusing impurities into the bottom end of each of the second recesses is performed between the fourth step and the fifth step. To run.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described.

FIG. 1 is a sectional view of a Schottky barrier diode according to a first embodiment of the present invention.

This diode is, for example, an N + Si substrate 1
1 has an N-epitaxial Si layer 12 grown epitaxially thereon, and a barrier metal 22 (anode side) is formed on the N-epitaxial Si layer 12.

On the opposite surface side of the N + Si substrate 11, an ohmic electrode 23 (cathode side) is formed.
Further, a plurality of recesses 15 are provided in the N-epitaxial Si layer 12, and a P + diffusion layer 17 is
Is formed, and poly-Si is embedded in the recess 15.

Further, a trench portion 19 is formed in the N- type semiconductor region between the P + type regions 17, and a barrier metal layer 22 is provided thereon. A P + diffusion region 21 is formed around the lower end of the trench 19 so as to project from the bottom end of the trench 19 to the N-epitaxial Si layer 12.

As described above, in the present embodiment, the N− type semiconductor region between the P + type regions 17 is made concave by forming a trench structure, thereby increasing the Schottky junction area. As shown in (1), the forward voltage drop can be reduced.

On the other hand, the bottom end of the trench portion 19 is formed at a relatively acute angle, and there is a possibility that the electric field may be concentrated in the reverse bias state. In order to avoid this, a structure is formed in which the P + type region 21 is formed to reduce the electric field intensity.
Incidentally, the depth of the trench portion 19 is made shallower (for example, ２) than each of the P + -type regions 17 so as to prevent the reverse leakage current from increasing.

According to the diode of this embodiment,
N-type epitaxial Si layer 12 at Schottky junction
At the interval and depth at which the depletion layer pinches off.
In the Schottky barrier diode having the + type region 17, the Schottky junction between the P + type regions 17 is formed in a concave shape (trench portion 19) to increase the junction area, so that the forward loss is reduced. be able to.

Further, P + is also applied to the bottom end of the trench 19.
Forming the mold region 21 to alleviate the electric field strength at the time of reverse bias and reducing the depth of the trench portion 19 to each P + region 17
Since it is formed shallower, the reverse leakage current can be reduced.

Next, a method of manufacturing the diode shown in FIG. 1 will be described with reference to FIGS. 2, 3 and 4.

First, as shown in FIG. 2A, N + Si
An N-epitaxial Si layer 12 is grown on a substrate 11.

Next, as shown in FIG. 2B, the oxide film 13 formed on the N-epitaxial Si layer 12 is patterned by photolithography, and further the N-epitaxial Si layer is 12
Is dry-etched to form a trench portion 14. Here, the depth of the trench portion 14 is 4 μm and the width is 1 μm.
μm, the distance from the bottom of the trench 14 to the upper surface of the N + Si substrate is 4 μm, and the interval between the trenches 14 is 5 μm.
And

Next, as shown in FIG. 2C, the poly-Si layer 15 is formed by CVD (Che) so that the trench 14 formed in the N-epitaxial Si layer 12 is completely buried.
Deposition is performed by a physical vapor deposition method or the like.

Next, as shown in FIG. 3D, until the surface of the poly-Si layer 15 buried in the trench portion 14 and the surface of the N￣ epitaxial Si layer 12 coincide with each other and are planarized, the poly-S
The i-layer 15 is dry-etched, and a P-type impurity 16 such as boron (B) is
It is implanted near the surface of the i buried layer 15. At this time, the oxide film 13 serves as a mask for ion implantation.
Is implanted only in the poly-Si buried layer 15.

Next, as shown in FIG.
P-type impurity 16 implanted near the surface of buried layer 15
Is diffused into the poly-Si buried layer 15 by heat treatment,
A P + diffusion layer 17 is formed. At this time, since poly-Si has a higher impurity diffusion rate than Si, most of the implanted P-type impurities 16 first
5, and then diffused into the N-epitaxial Si layer 12 around the trench 14 to form the P + diffusion layer 17.

Thereafter, as shown in FIG. 3F, the oxide film 13 is removed and an oxide film 18 is newly formed on the wafer.
Further, as shown in FIG. 4 (g), a concave portion (trench groove) 19 is formed between each of the P + diffusion regions 17 by a photography technique. Then, using the oxide film 18 as a mask, a P-type impurity 20 is implanted to form a P + diffusion region 21 at the bottom of each recess 19.

Finally, a Schottky diode having the structure shown in FIG. 1 can be obtained by forming a barrier metal 22 so that the recesses 19 are buried in the upper surface of the wafer and depositing an ohmic electrode 23 on the bottom surface of the wafer. .

FIG. 5 is a graph showing a forward voltage drop characteristic comparing the conventional structure of FIGS. 7B and 7C with the structure of FIG. 1 of the present embodiment.

The vertical axis represents the forward current I and the horizontal axis represents the forward voltage V. P1 in the figure is a characteristic curve of the present embodiment,
P2 is a characteristic curve of the conventional example. As is apparent from FIG. 5, when the voltage is increased in the forward direction, the forward current I is increased in the present embodiment and the forward voltage drop is reduced compared to the conventional example. .

FIG. 6 is a sectional view of a Schottky barrier diode according to a second embodiment of the present invention.

The diode of this embodiment is different from the first embodiment in that a plurality of trenches 31 are formed in the N− type semiconductor region between the P + type regions 17, and the bottom end of each trench 31 is formed. Peripheral N-epitaxial S
The P + type regions 32 are formed in the i layer 12 respectively.

Thus, the area of the Schottky junction can be further increased, and the forward voltage drop can be greatly reduced.

In the present invention, a material that forms a barrier for majority carriers on a semiconductor substrate, for example, Al, Mo, Au, Ti, V, or the like is used as the barrier metal electrode 22, as shown in FIG. Such a single-layer structure or two or more types of structures made of different types of materials may be used. Here, in the case of two or more types of structures,
Since materials having different barrier heights are used, desired characteristics, particularly forward characteristics, can be easily obtained as compared with a single-layer structure.

[0051]

As described above in detail, according to the first aspect, the trench portion is provided to make the Schottky junction between the first diffusion layers of each second conductivity type concave. The Schottky junction area increases by making the flat Schottky junction a concave shape. This makes it possible to reduce the forward loss.

According to the second invention, in the first invention, the second conductivity type second diffusion layer is provided in the first conductivity type semiconductor layer around the bottom end of the trench. The strength is reduced, and the reverse loss can be reduced. Therefore, it is possible to reduce both the forward loss and the backward loss, and it is possible to realize a semiconductor device having a lower loss than the conventional technology.

According to the third and fourth aspects of the present invention, the semiconductor devices of the first and second aspects of the present invention can be easily and accurately manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view of a Schottky barrier diode according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the diode of FIG. 1;

FIG. 3 is a continuation of FIG. 2;

FIG. 4 is a continuation of FIG. 3;

FIG. 5 is a graph showing a forward voltage drop characteristic comparing the conventional structure of FIGS. 7B and 7C with the structure of FIG. 1 of the present embodiment.

FIG. 6 is a sectional view of a Schottky barrier diode according to a second embodiment of the present invention.

FIG. 7 is a sectional structural view of a conventional Schottky barrier diode.

FIG. 8 is a graph showing a reverse leakage current characteristic of a conventional example.

FIG. 9 is a sectional structural view of a Schottky barrier diode disclosed in the above publication.

[Explanation of symbols]

 Reference Signs List 11 N + Si substrate 12 N-epitaxial Si layer 15 Concave portion 17 P + diffusion layer 19, 31 Trench portion 21, 32 P + diffusion region 22 Barrier metal 23 Ohmic electrode

Claims (4)

[Claims] 1. A semiconductor device comprising: a first conductivity type semiconductor layer; and electrodes sandwiching the semiconductor layer. A recess is formed in a plurality of predetermined regions of the semiconductor layer, and a second conductive layer is formed inside the plurality of recesses. A semiconductor device in which a buried layer of a second conductivity type and a first diffusion layer of a second conductivity type are formed around the buried layer, wherein the Schottky junction between the first diffusion layers of each second conductivity type is concave. A semiconductor device comprising: a trench portion; 2. The semiconductor device according to claim 1, wherein a second diffusion layer of a second conductivity type is provided in the semiconductor layer of the first conductivity type around a bottom end of the trench portion. 3. A first step of forming a semiconductor layer of a first conductivity type on a semiconductor substrate; and removing a plurality of predetermined regions of the semiconductor layer of the first conductivity type to form a plurality of first recesses. Forming a buried layer having an impurity diffusion rate higher than that of the semiconductor layer of the first conductivity type in each of the first recesses, and then performing impurity diffusion to form a second conductive layer around each of the first recesses; A third step of forming a semiconductor layer of a first conductivity type; a fourth step of forming a second recess in the semiconductor layer region of the first conductivity type between the diffusion layers of the second conductivity type; Forming a barrier metal in such a manner that the second concave portion is buried in the surface of the semiconductor layer of the mold. 4. The method according to claim 3, wherein a sixth step of diffusing an impurity into a bottom end of each of the second recesses is performed between the fourth step and the fifth step. A method for manufacturing a semiconductor device.