CN109768075B - FCE diode and manufacturing method thereof - Google Patents
FCE diode and manufacturing method thereof Download PDFInfo
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- CN109768075B CN109768075B CN201711097975.0A CN201711097975A CN109768075B CN 109768075 B CN109768075 B CN 109768075B CN 201711097975 A CN201711097975 A CN 201711097975A CN 109768075 B CN109768075 B CN 109768075B
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Abstract
The invention discloses an FCE diode and a manufacturing method thereof. The FCE diode includes: a drift layer; a P-type layer on the first surface of the drift layer; an N-buffer layer on the second surface of the drift layer; an N + + doping layer formed by injecting N-type ions into the N-buffer layer, wherein the thickness of the N + + doping layer is less than that of the N-buffer layer; a plurality of N + + doped regions formed by etching the N + + doped layer and a trench between every two adjacent N + + doped regions, wherein the bottom 10 of the trench contacts the N-buffer layer; and a P + + doped region formed by implanting P-type ions into the N-buffer layer through the trench and not contacting the N + + doped region, wherein the thickness of the P + + doped region is less than that of the N-buffer layer. By adopting the invention, the contact effect of the P + + doped region is improved while the better soft recovery characteristic is ensured, and the contact resistance of the cathode surface of the FCE diode is further reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to an FCE diode and a manufacturing method thereof.
Background
As shown in fig. 1, a conventional FRD (Fast recovery diode) includes a drift layer 101, a P-type layer 102 on a first surface of the drift layer 101, an N-buffer layer 103 on a second surface of the drift layer 101, an N + + doped layer 104 formed by implanting N-type ions into the N-buffer layer 103, a first metal layer 105 on the P-type layer 102, and a second metal layer 106 on the N + + doped layer 104, wherein a thickness of the N + + doped layer 104 is less than a thickness of the N-buffer layer 103.
An ideal FRD must have the characteristics of low on-state voltage drop, low reverse recovery loss, and high soft recovery factor at the same time. However, the FRD shown in fig. 1 is required to have a sufficiently high total carrier concentration in the body when it is forward-conducting so as to ensure sufficient conductivity modulation in the drift region, if it has a low on-state voltage drop characteristic. If it has a low reverse recovery loss characteristic, on the one hand, it is required that the total carrier in the body is as low as possible when it is turned on in the forward direction so that the reverse recovery charge is small, and on the other hand, it is also required that the carrier concentration near the anode junction is as low as possible so that a low reverse recovery peak current is obtained. If it has good soft recovery characteristics, it is required that the cathode side carrier concentration is high when it is turned on in the forward direction to obtain a smooth and continuous current tail. It can be seen that there are inherent contradictory relationships between these characteristics that are difficult to achieve simultaneously.
In order to improve the soft recovery characteristics of the FRD shown in fig. 1, P + + doped regions 201 are formed by implanting high-concentration P-type ions into the middle regions of the N + + doped layers 104, so as to obtain FCE (Field-extraction-charge-diode) diodes as shown in fig. 2. The N-type ion concentration of N + + doped layer 104 must be very high to ensure good contact between N + + doped layer 104 and second metal layer 106 and sufficient electrons for the FCE diode to recover in reverse direction, so that the FCE diode does not suffer from current-voltage oscillation during reverse recovery and has good soft recovery characteristics.
Since the N-type ions of the N + + doped layer 104 and the P-type ions of the P + + doped region 201 in fig. 2 have very high concentrations, the N-type ions of the N + + doped layer 104 and the P-type ions of the P + + doped region 201 are easily compensated with each other at the P + + doped region, so that the contact effect between the P + + doped region 201 and the second metal layer 106 is reduced. If the concentration of N-type ions in N + + doped layer 104 is reduced, the soft recovery characteristics of the FCE diode are impaired.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides an FCE diode and a method for manufacturing the same.
According to an aspect of the present invention, there is provided an FCE diode comprising:
a drift layer;
a P-type layer on the first surface of the drift layer;
an N-buffer layer on a second surface of the drift layer;
an N + + doping layer formed by implanting N-type ions into the N-buffer layer, wherein a thickness of the N + + doping layer is less than a thickness of the N-buffer layer;
a plurality of N + + doped regions formed by etching the N + + doped layer and a trench between every two adjacent N + + doped regions, wherein the bottom of the trench contacts the N-buffer layer;
a P + + doped region formed by implanting P-type ions into the N-buffer layer through the trench without contacting the N + + doped region, wherein the P + + doped region has a thickness less than a thickness of the N-buffer layer.
In one embodiment, an included angle between the trench sidewall and the trench bottom is determined according to a ratio of an area of the P + + doped region to an area of the N + + doped region and a thickness of the N + + doped layer.
In one embodiment, the included angle between the side wall of the groove and the bottom of the groove is 90-150 degrees.
In one embodiment, further comprising:
a first metal layer on the P-type layer, wherein an ohmic contact is formed between the first metal layer and the P-type layer;
a second metal layer on the sidewalls and bottom of each of the trenches and on the bottom surface of the N + + doped region, wherein the second metal layer forms an ohmic contact with the sidewalls and bottom of each of the trenches and the N + + doped region thereunder.
According to another aspect of the present invention, there is provided a method of manufacturing an FCE diode, comprising the steps of:
forming a P-type layer on the first surface of the drift layer;
forming an N-buffer layer on the second surface of the drift layer;
injecting N-type ions into the N-buffer layer to form an N + + doped layer, wherein the thickness of the N + + doped layer is smaller than that of the N-buffer layer;
etching the N + + doped layer to form a plurality of N + + doped regions and a groove between every two adjacent N + + doped regions, wherein the bottom of the groove is in contact with the N-buffer layer;
and injecting P-type ions into the N-buffer layer through the groove to form a P + + doped region which is not in contact with the N + + doped region, wherein the thickness of the P + + doped region is less than that of the N-buffer layer.
In one embodiment, a mask for etching the N + + doped layer is formed by:
coating a layer of photoresist on the lower surface of the N + + doped layer;
and developing and exposing the photoresist to form a mask for etching the groove.
In one embodiment, the N + + doped layer is etched using a wet etch.
In one embodiment, an included angle between the trench sidewall and the trench bottom is determined according to a ratio of an area of the P + + doped region to an area of the N + + doped region and a thickness of the N + + doped layer.
In one embodiment, the included angle between the side wall of the groove and the bottom of the groove is 90-150 degrees.
In one embodiment, the method further comprises the following steps:
forming a first metal layer on the P-type layer;
carrying out first annealing to form ohmic contact between the first metal layer and the P-type layer;
forming a second metal layer on the side wall and the bottom of each groove and on the lower surface of the N + + doped region;
and carrying out second annealing to form ohmic contact between the second metal layer and the side wall and the bottom of each groove below the second metal layer and the N + + doped region.
Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects:
in the invention, the N + + doped region with high doping concentration and the P + + doped region are spatially separated without reducing the doping concentration of N type ions of the N + + doped layer, so that the problem of mutual compensation of the N type ions of the N + + doped layer and the P type ions of the P + + doped region is avoided, the contact effect between the P + + doped region and the second metal layer is improved while the good soft recovery characteristic of the FCE diode is ensured, and the contact resistance of the cathode surface of the FCE diode is further reduced.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 illustrates a cross-sectional view of a prior art FRD;
FIG. 2 shows a cross-sectional view of a prior art FCE diode;
fig. 3 shows a cross-sectional view of a FCE diode according to a first embodiment of the invention;
fig. 4 shows a flow chart of a method of manufacturing an FCE diode according to a second embodiment of the invention;
FIG. 5 is a cross-sectional view of a wafer formed through steps S410 and S420 according to a second embodiment of the present invention;
fig. 6 is a cross-sectional view showing a wafer formed by step S430 according to a second embodiment of the present invention;
fig. 7 is a cross-sectional view showing a wafer formed by step S440 according to a second embodiment of the present invention;
fig. 8 is a cross-sectional view showing a wafer formed in step S450 according to a second embodiment of the present invention.
Detailed Description
The following detailed description of the embodiments of the present invention will be provided with reference to the drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
First embodiment
Fig. 3 is a cross-sectional view of an FCE diode according to a first embodiment of the present invention, as shown in fig. 3, which may include: drift layer 301, P-type layer 302, N-buffer layer 303, N + + doped layer 304, and P + + doped region 305.
Specifically, the P-type layer 302 is located on the first surface of the drift layer 301. An N-buffer layer 303 is located on the second surface of the drift layer 301. The N + + doped layer 304 is formed by implanting N-type ions into the N-buffer layer 303, wherein the thickness of the N + + doped layer 304 is less than the thickness of the N-buffer layer 303.
The N + + doped layer 304 is etched to form a plurality of N + + doped regions 3041 and trenches 3042 between every two adjacent N + + doped regions 3041. Wherein the bottom 10 of the trench 3042 contacts the N-buffer layer 303, i.e., the bottom 10 of the trench 3042 exposes a portion of the N-buffer layer 303 that is not implanted with N-type ions. The angle between the sidewalls of the trench 3042 and the bottom 10 of the trench 3042 is related to the particular method of etching the trench 3042 and the crystal orientation of the wafer substrate. If the trench 3042 is etched by a common wet etching method, an included angle between the sidewall of the trench 3042 and the bottom 10 of the trench 3042 is preferably 90 degrees to 150 degrees, and a specific value of the included angle may be determined according to a ratio of an area of the P + + doping region 3041 to an area of the N + + doping region 3041 and a thickness of the N + + doping layer 304.
The P + + doped region 305 is formed by implanting P-type ions into the N-buffer layer 303 through the trench 3042, wherein the P + + doped region 305 is not in contact with the N + + doped region 3041, and the thickness of the P + + doped region 305 is less than that of the N-buffer layer 303.
The FCE diode of this embodiment may further include a first metal layer 306 and a second metal layer 307. The first metal layer 306 is located on the P-type layer 302, wherein the first metal layer 306 forms an ohmic contact with the P-type layer 302. A second metal layer 307 is disposed on the sidewalls and bottom 10 of each trench 3042 and the bottom surface of the N + + doped region 3041, wherein the second metal layer 307 forms an ohmic contact with the sidewalls and bottom 10 of each trench 3042 and the N + + doped region 3041 therebelow.
In this embodiment, the doping concentration of N type ions of the N + + doping layer 304 does not need to be reduced, but the N + + doping region 3041 with a high doping concentration is spatially separated from the P + + doping region 305, so that the problem of mutual compensation between N type ions of the N + + doping layer 304 and P type ions of the P + + doping region 305 is avoided, and thus the contact effect between the P + + doping region 305 and the second metal layer 307 is improved while the good soft recovery characteristic of the FCE diode is ensured, and the contact resistance of the cathode surface of the FCE diode is reduced.
Second embodiment
Fig. 4 is a flowchart of a method for manufacturing an FCE diode according to a second embodiment of the present invention, and as shown in fig. 4, the method may include the following steps S410 to S450.
In step S410, a P-type layer 302 is formed on the first surface of the drift layer 301. The dopant dose of the P-type layer 302 may be 1012cm-2To 1013cm-2The junction depth is 2 to 10 um.
In step S420, an N-buffer layer 303 is formed on the second surface of the drift layer 301, so as to obtain a wafer as shown in fig. 5. The dopant amount of the N-buffer layer 303 may be 1013cm-2To 1014cm-2The junction depth is 5 to 20 um.
In step S430, N-type ions are implanted into the N-buffer layer 303 shown in fig. 5 to form an N + + doped layer 304, wherein the thickness of the N + + doped layer 304 is smaller than that of the N-buffer layer 303, so as to obtain a wafer shown in fig. 6. The dopant dose of the N + + doped layer 304 may be 1015cm-2To 1016cm-2. After ion diffusion and activation annealing, the peak doping concentration of the surface of the N + + doped layer 304 reaches 1019cm-3To 1020cm-3。
In step S440, the N + + doped layer 304 is etched to form a plurality of N + + doped regions 3041 and trenches 3042 between each two adjacent N + + doped regions 3041, wherein the bottom 10 of the trench 3041 contacts the N-buffer layer 303.
In this embodiment, a layer of photoresist is first applied to the bottom surface of the N + + doped layer 304 as shown in fig. 6. Next, the photoresist is developed and exposed to form a mask 308 for etching the trench. The N + + doped layer 304 is etched using a mask 308 to form a wafer as shown in fig. 7. Preferably, a wet etch is used to etch the N + + doped layer 304.
In etching the trench 3042, the angle between the sidewall of the trench 3042 and the bottom 10 of the trench 3042 is related to the specific method of etching the trench 3042 and the crystal orientation of the wafer substrate. If the trench 3042 is etched by a common wet etching method, an included angle between the sidewall of the trench 3042 and the bottom 10 of the trench 3042 is preferably 90 degrees to 150 degrees, and a specific value of the included angle may be determined according to a ratio of an area of the P + + doping region 3041 to an area of the N + + doping region 3041 and a thickness of the N + + doping layer 304.
In step S450, P-type ions are implanted into the N-buffer layer 303 through the trenches 3042 as shown in fig. 7 to form P + + doped regions 305 not contacting the N + + doped regions 304, wherein the thickness of the P + + doped regions 305 is smaller than that of the N-buffer layer 303, so as to obtain a wafer as shown in fig. 8. As shown in fig. 8, the N + + doped region 3041 is spatially separated from the P + + doped region 305, thereby avoiding the problem of mutual compensation between N-type ions of the N + + doped layer 304 and P-type ions of the P + + doped region 305.
In this embodiment, after P-type ions are implanted into the N-buffer layer 303 through the trench 3042, the photoresist used for etching the trench is removed.
After step S450, the following steps may be further included:
first, a first metal layer 306 is formed on the P-type layer 302 shown in fig. 8, and a first annealing is performed, so that an ohmic contact is formed between the first metal layer 306 and the P-type layer 302; next, a second metal layer 307 is formed on the sidewall and bottom 10 of each trench 3042 and the lower surface of the N + + doped region 3041, and a second annealing is performed, so that an ohmic contact is formed between the second metal layer 307 and the sidewall and bottom 10 of each trench 3042 and the N + + doped region 3041 therebelow, thereby obtaining a final diode (see fig. 3 for a specific structure thereof).
In this embodiment, without reducing the doping concentration of N type ions of the N + + doping layer 304, the N + + doping layer 304 is etched in step S440 to form a plurality of N + + doping regions 3041 and trenches 3042, and then P type ions are implanted into the N-buffer layer 303 through the trenches 3042 in step S450 to form the P + + doping region 305 that is not in contact with the N + + doping region 304, so that the N + + doping region 3041 with a high doping concentration is spatially separated from the P + + doping region 305, thereby avoiding the problem of mutual compensation between N type ions of the N + + doping layer 304 and P type ions of the P + + doping region 305, improving the contact effect between the P + + doping region 305 and the second metal layer 307 while ensuring better soft recovery characteristics of the FCE diode, and further reducing the contact resistance of the cathode surface of the FCE diode.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (5)
1. A method of manufacturing an FCE diode, comprising the steps of:
forming a P-type layer on the first surface of the drift layer;
forming an N-buffer layer on the second surface of the drift layer;
injecting N-type ions into the N-buffer layer to form an N + + doped layer, wherein the thickness of the N + + doped layer is smaller than that of the N-buffer layer;
wet etching is carried out on the N + + doped layer through a photoresist mask to form a plurality of N + + doped regions and a groove between every two adjacent N + + doped regions, and the bottom of the groove is in contact with the N-buffer layer;
implanting P-type ions into the N-buffer layer through the trench to form a P + + doped region not in contact with the N + + doped region, wherein the P + + doped region has a thickness less than a thickness of the N-buffer layer; the mask for injecting P-type ions into the N-buffer layer and the mask for etching the N + + doped layer are the same mask;
and removing the photoresist mask used for etching the groove.
2. The method of manufacturing according to claim 1, wherein a mask for etching the N + + doped layer is formed by:
coating a layer of photoresist on the lower surface of the N + + doped layer;
and developing and exposing the photoresist to form a mask for etching the groove.
3. The method according to claim 1, wherein an angle between the trench sidewall and the trench bottom is determined according to a ratio of an area of the P + + doped region to an area of the N + + doped region and a thickness of the N + + doped layer.
4. The method of claim 3, wherein the trench sidewalls are angled from 90 degrees to 150 degrees from the trench bottom.
5. The manufacturing method according to claim 1, further comprising the steps of:
forming a first metal layer on the P-type layer;
carrying out first annealing to form ohmic contact between the first metal layer and the P-type layer;
forming a second metal layer on the side wall and the bottom of each groove and on the lower surface of the N + + doped region;
and carrying out second annealing to form ohmic contact between the second metal layer and the side wall and the bottom of each groove below the second metal layer and the N + + doped region.
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| CN101952968A (en) * | 2007-12-19 | 2011-01-19 | Abb技术有限公司 | Reverse-conducting semiconductor device and method for manufacturing such a reverse-conducting semiconductor device |
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| CN106298970A (en) * | 2016-08-12 | 2017-01-04 | 无锡橙芯微电子股份有限公司 | A kind of high-voltage high-speed soft-recovery diode and manufacture method thereof |
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