CN114038905A - Schottky diode and manufacturing method thereof - Google Patents
Schottky diode and manufacturing method thereof Download PDFInfo
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- CN114038905A CN114038905A CN202111489484.7A CN202111489484A CN114038905A CN 114038905 A CN114038905 A CN 114038905A CN 202111489484 A CN202111489484 A CN 202111489484A CN 114038905 A CN114038905 A CN 114038905A
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- 230000004888 barrier function Effects 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 238000005468 ion implantation Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 239000000969 carrier Substances 0.000 description 5
- 230000001052 transient effect Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
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- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
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- 238000002360 preparation method Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
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- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
Abstract
The invention discloses a Schottky diode and a manufacturing method thereof, wherein the Schottky diode comprises an N-type epitaxial layer and a barrier metal layer which are sequentially stacked from bottom to top, a groove extending in the front-back direction is formed on the upper side of the N-type epitaxial layer, a channel structure is filled in the groove, the channel structure comprises a gate oxide layer, two polycrystalline silicon layers positioned on two sides of the gate oxide layer and two P-type lightly doped layers positioned on two sides of the two polycrystalline silicon layers, a P-type heavily doped layer connected with the P-type lightly doped layer is arranged on the upper side of the N-type epitaxial layer, and the P-type heavily doped layer is in contact with the barrier metal layer. The Schottky diode provided by the invention utilizes the P-type heavily doped layer to form ohmic contact with the barrier metal layer, and the P-type lightly doped layer is used as a conductance modulation layer, so that the anti-surge capacity of the device is greatly improved on the premise of not influencing the switching characteristic of the Schottky diode.
Description
Technical Field
The invention relates to the technical field of diodes, in particular to a Schottky diode and a manufacturing method thereof.
Background
The Schottky diode is widely applied in the field of fast charging power supplies, but the anti-surge capability of the Schottky diode is poor, in order to improve the anti-surge capability of the Schottky diode, a PN junction and a Schottky junction are integrated together in the conventional method, but the switching frequency of a device is reduced by the method, so that the manufacturing of the Schottky diode which can not reduce the switching frequency of the device but also improve the anti-surge capability is very important.
Disclosure of Invention
The invention mainly aims to provide a Schottky diode and a manufacturing method thereof, and aims to provide the Schottky diode which can not reduce the switching frequency of a device but also improve the anti-surge capacity.
In order to achieve the purpose, the invention provides a schottky diode which comprises an N-type epitaxial layer and a barrier metal layer which are sequentially stacked from bottom to top, wherein a groove extending in the front-back direction is formed in the upper side of the N-type epitaxial layer, a channel structure is filled in the groove, the channel structure comprises a gate oxide layer, two polycrystalline silicon layers positioned on two sides of the gate oxide layer and two P-type lightly doped layers positioned on two sides of the two polycrystalline silicon layers, a P-type heavily doped layer connected with the P-type lightly doped layer is arranged on the upper side of the N-type epitaxial layer, and the P-type heavily doped layer is in contact with the barrier metal layer.
Optionally, the P-type heavily doped layer is disposed corresponding to the channel structure, and two ends of the P-type heavily doped layer are respectively connected to the two P-type lightly doped layers of the channel structure.
Optionally, a plurality of channel structures are provided, and the plurality of channel structures are arranged at intervals along the width direction of the channel structures;
in any two adjacent channel structures, the P-type heavily doped layer is correspondingly arranged between the two adjacent P-type lightly doped layers, and two ends of the P-type heavily doped layer are respectively connected with the two P-type lightly doped layers.
Optionally, the P-type heavily doped layer is provided in plurality, and the P-type heavily doped layers are arranged at intervals along the length direction of the channel structure.
Optionally, the P-type heavily doped layer is provided in plurality, and the P-type heavily doped layers are arranged at intervals along the width direction of the channel structure.
Optionally, the distances between two adjacent P-type heavily doped layers and the front side surface of the N-type epitaxial layer are equal; and/or the presence of a gas in the gas,
and in two adjacent P-type heavily doped layers, the distance between one of the two P-type heavily doped layers and the front side surface of the N-type epitaxial layer is greater than the distance between the other one of the two P-type heavily doped layers and the front side surface of the N-type epitaxial layer.
Optionally, the doping concentration of the P-type heavily doped layer is 1011～1013cm-2。
Optionally, the junction depth of the P-type heavily doped layer is smaller than the junction depth of the P-type lightly doped layer.
The invention also provides a manufacturing method of the Schottky diode, which comprises the following steps:
preparing a P-type ring region on the upper side of the N-type epitaxial layer;
etching the P-type ring region to form a groove, wherein the etched residual part of the P-type ring region forms a P-type lightly doped layer;
preparing a gate oxide layer in the groove and then preparing a polysilicon layer;
preparing a P-type heavily doped layer on the upper side of the N-type epitaxial layer corresponding to the P-type lightly doped layer;
and preparing a barrier metal layer on the upper side of the P-type heavily doped layer.
Optionally, the step of preparing the P-type heavily doped layer on the upper side of the N-type epitaxial layer includes:
and coating photoresist on the upper side of the N-type epitaxial layer, exposing, developing, then carrying out ion implantation, and removing the photoresist after implantation to form a P-type heavily doped layer.
In the technical scheme of the invention, a barrier metal layer and a P-type lightly doped layer are connected through a P-type heavily doped layer to form a P + P-N type device structure, wherein P + refers to P-type heavily doped, P-refers to P-type lightly doped, and N refers to an N-type epitaxial layer. When the device is conducted in the forward direction, under the conditions of small current and medium current, the current of the Schottky diode is dominant, and because the potential barrier of the PN junction is high, minority carriers injected through the PN junction are few, the influence on the switching characteristic of the device is weak; under the condition of large current, particularly surge, the nominal current value of the device is usually more than 20 times, under the transient condition, the PN junction is conducted, the P + P-N type region can inject minority carriers into the epitaxial layer to play a role in conducting modulation, the resistance of the epitaxial layer is reduced, the conducting voltage drop and the transient power consumption of the device are further reduced, and the anti-surge capacity of the device is improved. Compared with the situation that the P-type heavy doping layer is not arranged and the P-type light doping layer is in direct contact with the barrier metal layer, the Schottky diode provided by the invention has smaller influence on the switching characteristic and stronger surge resistance. The invention uses the P-type heavily doped layer and the barrier metal layer to form ohmic contact, and the P-type lightly doped layer is used as a conductance modulation layer, thereby greatly improving the anti-surge capability of the device on the premise of not influencing the switching characteristic of the Schottky diode.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other related drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a schottky diode according to an embodiment of the present invention;
FIG. 2 is a top view of FIG. 1;
fig. 3 is a schematic structural diagram of a schottky diode according to another embodiment of the present invention;
fig. 4 is a schematic view of a manufacturing process of a method for manufacturing a schottky diode according to an embodiment of the present invention.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 1 | N-type substrate | 6 | P-type lightly doped layer |
| 2 | N-type epitaxial layer | 7 | P-type heavily doped |
| 3 | |
8 | |
| 4 | Gate oxide layer | 9 | P- |
| 5 | Polycrystalline silicon layer |
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include a plurality of such features. In addition, the meaning of "and/or" appearing throughout includes three juxtapositions, exemplified by "A and/or B" including either A or B or both A and B. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The Schottky diode is widely applied in the field of fast charging power supplies, but the anti-surge capability of the Schottky diode is poor, in order to improve the anti-surge capability of the Schottky diode, a PN junction and a Schottky junction are integrated together in the conventional method, but the switching frequency of a device is reduced by the method, so that the manufacturing of the Schottky diode which can not reduce the switching frequency of the device but also improve the anti-surge capability is very important.
In view of the above, fig. 1 to 3 illustrate an embodiment of a schottky diode according to the present invention, the schottky diode includes an N-type substrate 1 and an N-type epitaxial layer 2 formed on an upper side of the N-type substrate 1, and the present invention is improved by the N-type epitaxial layer 2, so that the structure of the N-type epitaxial layer 2 will be described in detail with reference to fig. 1 to 3.
As shown in fig. 1 to 3, the schottky diode includes an N-type epitaxial layer 2 and a barrier metal layer (not shown) stacked in sequence from bottom to top, a trench 3 extending in the front-rear direction is formed on the upper side of the N-type epitaxial layer 2, a channel structure is filled in the trench 3, the channel structure includes a gate oxide layer 4, two polysilicon layers 5 located on both sides of the gate oxide layer 4 and two P-type lightly doped layers 6 located on both sides of the two polysilicon layers 5, a P-type heavily doped layer 7 connected to the P-type lightly doped layer 6 is disposed on the upper side of the N-type epitaxial layer 2, and the P-type heavily doped layer 7 contacts with the barrier metal layer.
It should be noted that the lower ends of the two polysilicon layers 5 are connected to each other, and the two polysilicon layers 5 are filled between the inner side wall of the trench 3 and the gate oxide layer 4.
In the technical scheme of the invention, a barrier metal layer and a P-type lightly doped layer 6 are connected through a P-type heavily doped layer 7 to form a P + P-N type device structure, wherein P + refers to P-type heavily doped, P-refers to P-type lightly doped, and N refers to an N-type epitaxial layer 2. When the device is conducted in the forward direction, under the conditions of small current and medium current, the current of the Schottky diode is dominant, and because the potential barrier of the PN junction is high, minority carriers injected through the PN junction are few, the influence on the switching characteristic of the device is weak; under the condition of large current, particularly surge, the nominal current value of the device is usually more than 20 times, under the transient condition, the PN junction is conducted, the P + P-N type region can inject minority carriers into the epitaxial layer to play a role in conducting modulation, the resistance of the epitaxial layer is reduced, the conducting voltage drop and the transient power consumption of the device are further reduced, and the anti-surge capacity of the device is improved. Compared with the situation that the P-type heavily doped layer 7 is not arranged and the P-type lightly doped layer 6 is in direct contact with the barrier metal layer, the Schottky diode provided by the invention has smaller influence on the switching characteristic and stronger surge resistance. The invention uses the P-type heavily doped layer 7 to form ohmic contact with the barrier metal layer, and the P-type lightly doped layer 6 as a conductance modulation layer, thereby greatly improving the anti-surge capability of the device on the premise of not influencing the switching characteristic of the Schottky diode.
Further, the P-type heavily doped layer 7 is disposed corresponding to the channel structure, and two ends of the P-type heavily doped layer 7 are respectively connected to the two P-type lightly doped layers 6 of the channel structure. It should be noted that, since a plurality of channel structures are generally provided, two ends of the P-type heavily doped layer 7 are respectively connected to the two P-type lightly doped layers 6 of the channel structure, one of which is that two ends of the P-type heavily doped layer 7 are connected to the two P-type lightly doped layers 6 of one channel structure, and the other of which is that two ends of the P-type heavily doped layer 7 are connected to the two P-type lightly doped layers 6, and the two P-type lightly doped layers 6 belong to two channel structures, which is not limited herein.
Specifically, a description will be given of a manner that "both ends of the P-type heavily doped layer 7 are connected to the two P-type lightly doped layers 6, and the two P-type lightly doped layers 6 belong to two channel structures", where the number of the channel structures is plural, and the plural channel structures are arranged at intervals in the width direction thereof; in any two adjacent channel structures, the P-type heavily doped layer 7 is correspondingly arranged between two adjacent P-type lightly doped layers 6, and two ends of the P-type heavily doped layer 7 are respectively connected with the two P-type lightly doped layers 6. At this time, ions are implanted into the N-type epitaxial layer 2 corresponding to the P-type lightly doped layer 6 to form the P-type heavily doped layer 7, which facilitates the preparation and formation of the P-type heavily doped layer 7 and improves the preparation efficiency. It should be noted that two adjacent P-type lightly doped layers 6 belong to two adjacent channel structures.
Furthermore, a plurality of P-type heavily doped layers 7 are provided, and the P-type heavily doped layers 7 are arranged at intervals along the length direction of the channel structure. Therefore, the P-type heavily doped layers 7 and the P-type lightly doped layers 6 which are arranged at intervals along the length direction of the channel structure form a trapezoidal structure, and minority carriers flow into the P-type lightly doped layers 6 through the P-type heavily doped layers 7 when the P + P-N structure works and finally enter the N-type epitaxial layer 2. Therefore, the region of the P-type lightly doped layer 6 closer to the P-type heavily doped layer 7 has higher voltage, and when the surge occurs, the conductivity modulation effect is stronger, while the region of the P-type lightly doped layer 6 farther from the P-type heavily doped layer 7 has lower voltage, and when the surge occurs, the conductivity modulation effect is weaker. Therefore, the device conductance modulation working mechanism can be controlled by controlling the distance between the P-type heavily doped layers 7, so that the relationship between the switching frequency and the surge capacity of the device is coordinated. In addition, the width and the spacing of the P-type heavily doped layer 7 are not limited by the present invention, which is related to the specific design requirements of the device, such as static parameters and dynamic characteristics.
The P-type heavily doped layers 7 are arranged in a plurality, and the P-type heavily doped layers 7 are arranged at intervals along the width direction of the channel structure. By arranging a plurality of the P-type heavily doped layers 7, the surge resistance of the device is further optimized. Preferably, "the P-type heavily doped layers 7 are spaced apart along the width direction of the channel structure" may be combined with "the P-type heavily doped layers 7 are spaced apart along the length direction of the channel structure", that is, a plurality of trapezoid structures composed of the P-type heavily doped layers 7 and the P-type lightly doped layers 6 are formed on the upper side of the N-type epitaxial layer 2, specifically referring to fig. 2 and 3.
In addition, as shown in fig. 2, the distances between two adjacent P-type heavily doped layers 7 and the front side surface of the N-type epitaxial layer 2 are equal, that is, the P-type heavily doped layers 7 in two adjacent ladder structures are aligned one to one.
Of course, the P-type heavily doped layers 7 in two adjacent ladder structures may be alternately disposed, as shown in fig. 3, a distance between one of the two adjacent P-type heavily doped layers 7 and the front side surface of the N-type epitaxial layer 2 is greater than a distance between the other one of the two adjacent P-type heavily doped layers 7 and the front side surface of the N-type epitaxial layer 2.
Further, the doping concentration of the P-type heavily doped layer 7 is 1011～1013cm-2Therefore, the doped impurity quantity of the P-type heavily doped layer 7 is enough, and the ohmic contact between the P-type heavily doped layer 7 and the barrier metal layer is ensured.
The junction depth of the P-type heavily doped layer 7 is smaller than that of the P-type lightly doped layer 6, so that the surge resistance of the Schottky diode is better.
In addition, the present invention further provides a method for manufacturing the schottky diode, referring to fig. 4, including the following steps:
step S10 is to prepare a P-type ring region 9 on the upper side of the N-type epitaxial layer 2.
Specifically, first, a layer is deposited on the N-type epitaxial layer 2
The left and right silicon nitride layers 8 serve as a barrier layer for silicon etching of the trench 3, as shown in fig. 4 (a). The thickness of the silicon nitride layer 8 is preferably set to
Left and right, wherein the unit
Is in the range of angstroms (a) and,
with the thickness, the blocking effect is good.
Then, a first photolithography is performed on the upper side of the silicon nitride layer 8 to etch an ion implantation window, as shown in fig. 4 (b). Ion implantation is performed, and for N-type Schottky, the ion source may be BF3、BCL3The ion implantation energy is 30-120 KEV, and the ion implantation dosage is 1011～1013cm-2In the meantime.
Finally, a rapid thermal annealing process is performed to form a P-type ring region 9 on the upper side of the N-type epitaxial layer 2, as shown in fig. 4 (c). The temperature of the rapid thermal annealing process is between 900 ℃ and 1150 ℃, and the rapid thermal annealing process ensures that the lateral diffusion of the P-shaped ring region 9 is low.
Step S20, etching a trench 3 on the P-type ring region 9, and forming a P-type lightly doped layer 6 in the etched remaining portion of the P-type ring region 9.
Specifically, the trench 3 is etched on the P-type ring region 9, the silicon nitride layer 8 is used as an etching barrier layer, and the structure of the etched trench 3 and the formed P-type lightly doped layer 6 are as shown in fig. 4 (d). The ion implantation window and the etching window are respectively made of a silicon nitride layer 8 serving as an ion implantation shielding layer and an etching barrier layer, and only the part of the P-type ring region 9 left after the groove 3 is etched is reserved to serve as the P-type lightly doped layer 6, and the doping concentration of the part is low. In addition, to ensure the smooth formation of the P-type lightly doped layer 6, it is necessary to ensure that the width of the P-type ring region 9 is greater than the width of the trench 3.
And step S30, preparing a gate oxide layer 4 in the groove 3, and then preparing a polysilicon layer 5.
Specifically, a gate oxide layer 4 is prepared in the trench 3, the thickness of the gate oxide layer 4 is determined by the device withstand voltage, then polysilicon deposition and etching back are carried out, the silicon nitride layer 8 is removed, as shown in fig. 4(e), the top view is shown in fig. 4(f), and the polysilicon layer 5 remaining after etching back is arranged in the trench 3.
Step S40, preparing a P-type heavily doped layer 7 on the upper side of the N-type epitaxial layer 2 corresponding to the P-type lightly doped layer 6.
Specifically, step S40 includes: step S41, applying photoresist on the upper side of the N-type epitaxial layer 2, exposing, developing, then performing ion implantation, and removing the photoresist after implantation to form the P-type heavily doped layer 7.
More specifically, photoresist is coated on the upper side of the N-type epitaxial layer 2, exposure and development are carried out, P-type impurities are implanted by taking the photoresist as a barrier layer, and the ion source can be BF3、BCL3Plasma, ion implantation energy is between 30KEV and 60KEV, and ion implantation dosage is 1015～1017cm-2And then removing the photoresist, and finally performing ion implantation annealing to form the P-type heavily doped layer 7. As shown in fig. 4(g), the P-type heavily doped layer 7 and the P-type lightly doped layer 6 formed in this time are distributed in a trapezoidal shape in fig. 4(g), and form a trapezoidal structure.
Step S50, preparing a barrier metal layer on the upper side of the P-type heavily doped layer 7.
The above is only a preferred embodiment of the present invention, and it is not intended to limit the scope of the invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall be included in the scope of the present invention.
Claims (10)
1. The Schottky diode is characterized by comprising an N-type epitaxial layer and a barrier metal layer which are sequentially stacked from bottom to top, wherein a groove extending forwards and backwards is formed in the upper side of the N-type epitaxial layer, a channel structure is filled in the groove, the channel structure comprises a gate oxide layer, two polycrystalline silicon layers positioned on two sides of the gate oxide layer and two P-type lightly doped layers positioned on two sides of the two polycrystalline silicon layers, a P-type heavily doped layer connected with the P-type lightly doped layer is arranged on the upper side of the N-type epitaxial layer, and the P-type heavily doped layer is in contact with the barrier metal layer.
2. The schottky diode of claim 1 wherein said P-type heavily doped layer is disposed corresponding to said channel structure, and both ends of said P-type heavily doped layer are connected to two of said P-type lightly doped layers of said channel structure, respectively.
3. The schottky diode of claim 2 wherein a plurality of said channel structures are provided, a plurality of said channel structures being spaced apart along a width thereof;
in any two adjacent channel structures, the P-type heavily doped layer is correspondingly arranged between the two adjacent P-type lightly doped layers, and two ends of the P-type heavily doped layer are respectively connected with the two P-type lightly doped layers.
4. The schottky diode of claim 3 wherein a plurality of the P-type heavily doped layers are provided, the plurality of P-type heavily doped layers being spaced apart along the length of the channel structure.
5. The schottky diode of claim 3 wherein a plurality of the P-type heavily doped layers are provided, the plurality of P-type heavily doped layers being spaced apart along a width direction of the channel structure.
6. The schottky diode of claim 5 wherein two adjacent heavily P-doped layers are equidistant from the front side of the N-epi layer; and/or the presence of a gas in the gas,
and in two adjacent P-type heavily doped layers, the distance between one of the two P-type heavily doped layers and the front side surface of the N-type epitaxial layer is greater than the distance between the other one of the two P-type heavily doped layers and the front side surface of the N-type epitaxial layer.
7. The schottky diode of claim 1 wherein said heavily P-doped layer has a doping concentration of 1011～1013cm-2。
8. The schottky diode of claim 1 wherein the junction depth of the heavily P-doped layer is less than the junction depth of the lightly P-doped layer.
9. A method of forming a schottky diode as described in any one of claims 1 to 8, comprising the steps of:
preparing a P-type ring region on the upper side of the N-type epitaxial layer;
etching the P-type ring region to form a groove, wherein the etched residual part of the P-type ring region forms a P-type lightly doped layer;
preparing a gate oxide layer in the groove and then preparing a polysilicon layer;
preparing a P-type heavily doped layer on the upper side of the N-type epitaxial layer corresponding to the P-type lightly doped layer;
and preparing a barrier metal layer on the upper side of the P-type heavily doped layer.
10. The method of claim 9, wherein the step of forming the P-type heavily doped layer on the top side of the N-type epitaxial layer comprises:
and coating photoresist on the upper side of the N-type epitaxial layer, exposing, developing, then carrying out ion implantation, and removing the photoresist after implantation to form a P-type heavily doped layer.
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