CN216871977U - Schottky diode - Google Patents

Abstract

The utility model discloses a Schottky diode, which comprises a substrate; the middle layer is arranged on the upper side of the substrate and comprises an epitaxial layer and an oxide layer, a plurality of grooves are formed in the upper portion of the middle layer and comprise a plurality of terminal region grooves located in a terminal region, each groove is provided with a first inner wall corresponding to the epitaxial layer, a gate oxide layer is arranged on each first inner wall, and a channel is defined by the gate oxide layer; a plurality of first polysilicon structures are correspondingly filled in the channels; the second polysilicon structures are arranged corresponding to the area between two adjacent first polysilicon structures, two ends of each second polysilicon structure are respectively contacted with the two first polysilicon structures to form polysilicon PN junctions which are connected in series, and the breakdown voltage of the polysilicon PN junctions is less than that of the epitaxial layer. The utility model clamps the potential of the first polysilicon structure in the terminal region groove through the polysilicon PN junction connected in series, thereby stabilizing the breakdown voltage of the whole device and further ensuring the high reliability of the device.

Description

Schottky diode

Technical Field

The utility model relates to the technical field of semiconductor devices, in particular to a Schottky diode.

Background

The schottky diode is manufactured by utilizing a metal-semiconductor barrier principle formed by contacting metal and a semiconductor, and has lower conduction voltage drop and faster switching frequency as a power rectifying device to be widely applied to a switching power supply and other power switching equipment requiring high speed. The characteristics of the schottky diode are mainly influenced by the schottky contact barrier, such as the reverse breakdown voltage, the reverse leakage current, and the forward conduction voltage drop, which are all related to the size of the barrier of the schottky metal.

The barrier lowering effect of the schottky itself can enable the schottky to generate larger leakage current when the schottky is under high voltage, and due to the asymmetry of the edge structure of the active region, when the device is in reverse blocking, the electric field at the edge of the device is concentrated, so that the device is broken down in advance at the edge, namely, the schottky diode device is lower than the withstand voltage of the active region due to the withstand voltage of the terminal region, and therefore the withstand voltage and the reliability of the device are reduced. The conventional terminal structures of the Schottky diode comprise field limiting rings, wide groove terminals, floating groove rings and other terminal structures, the structures realize the consistency of the withstand voltage of the terminal of the device and the withstand voltage of the active region by expanding the boundary of the active region, namely adding the terminal structures of a chip, and further realize the reverse blocking capability of the device.

The floating groove ring terminal structure is relatively consistent with the active area groove structure, so that the terminal groove depth is easily controlled to be consistent with the active area groove depth when the groove is etched in the first step through photoetching, and the process is simple and convenient and can be widely applied. However, such a conventional floating trench ring termination structure has low voltage stability, thereby degrading reliability of the schottky diode.

SUMMERY OF THE UTILITY MODEL

The utility model mainly aims to provide a Schottky diode, and aims to provide a Schottky diode with high voltage resistance and high reliability.

In order to achieve the above object, the present invention provides a schottky diode, including:

a substrate;

the middle layer is arranged on the upper side of the substrate and comprises an epitaxial layer and an oxide layer located on the upper side of the epitaxial layer, a plurality of grooves are formed in the upper portion of the middle layer, the grooves comprise at least one active region groove located in an active region and a plurality of terminal region grooves located in a terminal region, each groove is provided with a first inner wall corresponding to the epitaxial layer, a gate oxide layer is arranged on the first inner wall, and a channel is defined by the gate oxide layer;

a plurality of first polysilicon structures correspondingly filled in the channels;

the second polycrystalline silicon structures are arranged on the middle layer of the terminal area at intervals, each second polycrystalline silicon structure is arranged corresponding to the area between two adjacent first polycrystalline silicon structures, two ends of each second polycrystalline silicon structure are respectively contacted with the two first polycrystalline silicon structures to form a polycrystalline silicon PN junction in series, and the breakdown voltage of the polycrystalline silicon PN junction is smaller than that of the epitaxial layer.

Optionally, the epitaxial layer is an N-type lightly doped monocrystalline silicon layer with a doping concentration of 10¹³～10¹⁸cm^-3。

Optionally, the first polysilicon structure is an N-type heavily doped polysilicon with a doping concentration of 10¹⁷～10²⁰cm^-3。

Optionally, the second polysilicon structure is P-type lightly doped polysilicon with a doping concentration of 10¹³～10¹⁵cm^-3。

Optionally, the gate oxide layer has a thickness of

Optionally, in the plurality of terminal region trenches, one of the terminal region trenches farthest from the active region is a stop ring trench, and the rest are first terminal trenches, and a distance between every two first terminal trenches is 0.5 to 2 μm.

Optionally, the schottky diode further comprises:

the passivation layer is arranged on the upper sides of the first polycrystalline silicon structure and the second polycrystalline silicon structure, and two ends of the passivation layer expose part of the first polycrystalline silicon structure;

and the barrier metal layer is arranged on the upper sides of the middle layer and the passivation layer and is provided with a first metal layer unit corresponding to the passivation layer, and the first metal layer unit is provided with a groove penetrating to the upper surface of the passivation layer.

According to the technical scheme, the second polycrystalline silicon structures are arranged on the upper sides of the plurality of first polycrystalline silicon structures, two ends of each second polycrystalline silicon structure are respectively contacted with the two first polycrystalline silicon structures to form the polycrystalline silicon PN junctions which are connected in series, and the breakdown voltage of the polycrystalline silicon PN junctions is smaller than that of the epitaxial layer; meanwhile, the added second polysilicon terminal structure also improves the terminal withstand voltage of the device due to the uniform distribution of the surface potential, so that the Schottky diode provided by the utility model has high withstand voltage and reliability.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a conventional schottky diode;

fig. 2 is a schematic structural diagram of a schottky diode according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a portion of the schottky diode of fig. 2;

fig. 4 is a schematic diagram of a portion of the schottky diode of fig. 2.

The reference numbers illustrate:

reference numerals	Name (R)	Reference numerals	Name (R)
				1	Substrate	8	Barrier metal layer
2	Epitaxial layer	91	Active region trench
				3	Oxide layer	92	Termination region trench
4	Gate oxide layer	921	First terminal slot
				5	First polysilicon structure	921a	Floating terminal slot
6	Second polysilicon structure	922	Stop ring groove
				7	Passivation layer

The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.

In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the meaning of "and/or" appearing throughout includes three juxtapositions, exemplified by "A and/or B" including either A or B or both A and B. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.

The structure of the conventional schottky diode having a floating trench ring termination structure is shown in fig. 1, wherein the left side of the dotted line is an active region, and the right side thereof is a termination region, the schottky diode includes a substrate 1, an epitaxial layer 2, an oxide layer 3, a gate oxide layer 4, a first polysilicon structure 5, a passivation layer 7, and a barrier metal layer 8, which are sequentially disposed from bottom to top, wherein the 2 nd and 3 rd trenches from left to right in a termination region trench 92 are floating and named as floating termination trenches 921a, and the floating termination trenches 921a are not in contact with the epitaxial layer 2 or the barrier metal layer 8, so that the potential thereof is uncertain (i.e., no potential). When the schottky diode device is in reverse blocking, the electric field at the bottom of the floating terminal slot 921a is concentrated, hot carriers in the bulk silicon (i.e. the epitaxial layer 2) easily enter the gate oxide layer 4 in the floating terminal slot 921a under the action of a strong electric field, so that the potential of the first polycrystalline silicon electrode in the floating terminal slot 921a can be influenced, the distribution of the electric field of the device is further influenced, the breakdown voltage of the device is increased or reduced, namely, the breakdown voltage is changed, and the reliability of the device is reduced.

In view of this, the present invention provides a schottky diode, which clamps the potential of the first polysilicon structure 5 in the termination trench 92 by the polysilicon PN junction connected in series, so as to stabilize the breakdown voltage of the whole device, and further improve the reliability of the device. Fig. 2 to 4 are diagrams of an embodiment of a schottky diode according to the present invention, in which the left side of the dotted line is an active region, the right side of the dotted line is a termination region, N + refers to N-type heavy doping, N-refers to N-type light doping, and P-refers to P-type light doping. Referring to fig. 2 to 4 in combination, in the present embodiment, the schottky diode includes a substrate 1, an intermediate layer, a plurality of first polysilicon structures 5, and at least two second polysilicon structures 6 arranged at intervals, wherein the intermediate layer is arranged on an upper side of the substrate 1, the intermediate layer includes an epitaxial layer 2 and an oxide layer 3 arranged on an upper side of the epitaxial layer 2, a plurality of trenches are formed on an upper portion of the intermediate layer, the plurality of trenches include at least one active region trench 91 arranged in an active region and a plurality of terminal region trenches 92 arranged in a terminal region, each trench has a first inner wall corresponding to the epitaxial layer 2, a gate oxide layer 4 is arranged on the first inner wall, and the gate oxide layer 4 defines a channel; a plurality of first polysilicon structures 5 are correspondingly filled in the channels; the second polycrystalline silicon structures 6 are arranged on the middle layer of the terminal area, each second polycrystalline silicon structure 6 is arranged corresponding to the area between two adjacent first polycrystalline silicon structures 5, two ends of each second polycrystalline silicon structure 6 are respectively contacted with the two first polycrystalline silicon structures 5 to form a polycrystalline silicon PN junction in series, and the breakdown voltage of the polycrystalline silicon PN junction is smaller than that of the epitaxial layer 2.

In the technical scheme of the utility model, the second polysilicon structures 6 are arranged on the upper sides of the plurality of first polysilicon structures 5, two ends of each second polysilicon structure 6 are respectively contacted with the two first polysilicon structures 5 to form polysilicon PN junctions which are connected in series, and the breakdown voltage of the polysilicon PN junctions is less than that of the epitaxial layer 2, so that when the Schottky diode device is reversely broken down, the polysilicon PN junctions are broken down before the epitaxial layer 2, the first polysilicon structures 5 in the terminal region groove 92 are clamped, the breakdown voltage of the whole Schottky diode device is stable, and the reliability of the device is high; meanwhile, the added second polysilicon terminal structure also improves the terminal withstand voltage of the device due to the uniform distribution of the surface potential, so that the Schottky diode provided by the utility model has high withstand voltage and reliability.

That is, according to the utility model, through the design of the second polysilicon structure 6, the second polysilicon structure is connected in series with the first polysilicon structure 5 to form a polysilicon PN junction, and the polysilicon PN junction is punctured earlier than the epitaxial layer 2, so that the potential of the first polysilicon structure 5 in the terminal region trench 92 and the electric field distribution of the epitaxial layer 2 are prevented from being influenced after hot carriers enter the gate oxide layer 4 from the bottom of the terminal region trench 92 when the bulk silicon of the epitaxial layer 2 is punctured, and the breakdown voltage of the device is unstable.

In the present embodiment, an N-type lightly doped epitaxial layer 2 is formed on an N + substrate 1, and preferably, the epitaxial layer 2 is an N-type lightly doped monocrystalline silicon layer with a doping concentration of 10¹³～10¹⁸cm^-3。

The first polysilicon structure 5 and the second polysilicon structure 6 are in contact to form a polysilicon PN junction connected in series, that is, one of the first polysilicon structure 5 and the second polysilicon structure 6 is N-type polysilicon, and the other is P-type polysilicon. Preferably, one of the first polysilicon structure 5 and the second polysilicon structure 6 is heavily doped polysilicon, and the other is lightly doped polysilicon. The utility model does not limit the specific kind of the first polysilicon structure 5, and the first polysilicon structure 5 may be heavily doped N-type (the corresponding second polysilicon structure 6 is lightly doped P-type), heavily doped P-type (the corresponding second polysilicon structure 6 is lightly doped N-type), lightly doped N-type (the corresponding second polysilicon structure 6 is heavily doped P-type), and the like.

Since the epitaxial layer 2 is an N-type lightly doped monocrystalline silicon layer in the present embodiment, the first polysilicon structure 5 is preferably an N-type heavily doped polysilicon structure. Further, the doping concentration of the N-type heavily doped polysilicon structure is 10¹⁷～10²⁰cm^-3。

By adjusting the doping concentration of the second polysilicon structure 6, the breakdown voltage of the polysilicon PN junctions connected in series can be adjusted, so that the potential of the first polysilicon structure 5 in the terminal region trench 92 can be adjusted, and the potential of the first polysilicon structure 5 originally affected by the hot carriers can be fixed. In this embodiment, the second polysilicon layer is a P-type lightly doped polysilicon layer with a doping concentration of 10¹³～10¹⁵cm^-3。

Of the plurality of termination region trenches 92, 1 farthest from the active region is a stop ring trench 921a (i.e., the trench on the rightmost side of the termination region), and the rest are first termination trenches 921. Both ends of the rightmost second polysilicon structure 6 are respectively in contact with the first terminal groove 921 and the stop ring groove 922, and it can be understood that the middle of the rightmost second polysilicon structure 6 is disconnected, which would otherwise cause a short circuit, and thus, the first terminal groove 921 is mainly used to form a polysilicon PN junction with the second polysilicon structure 6. The present invention does not limit the specific number of the first termination slots 921, which is related to the required breakdown voltage of the polysilicon PN junction diode, but at least two, so as to form serial PN junctions, thereby clamping the potential of the first polysilicon structure 5 (i.e., the first polysilicon electrode) in the termination region trench 92. That is, the number of the second polysilicon structures 6 is at least 2, two ends of one of the second polysilicon structures are respectively in contact with the two first terminal slots 921, and two ends of the other of the second polysilicon structures are respectively in contact with the first terminal slots 921 and the stop ring grooves 922. In this embodiment, there are 3 first terminal slots 921, forming an NPNPN type structure. Under the doping concentration and the number of the first terminal grooves 921, the breakdown voltage of the epitaxial layer 2 is smaller than that of the polysilicon PN junction, so that the polysilicon PN junction is broken down before the epitaxial layer 2.

It is to be understood that, of the termination region trenches 92, the 2 nd and 3 rd trenches from left to right are floating and named as floating termination trenches 921a, and the floating termination trenches 921a are not in contact with the epitaxial layer 2 or the barrier metal layer 8, and thus, the potential thereof is indeterminate (i.e., no potential). According to the utility model, the polysilicon PN junctions connected in series are formed, and the breakdown voltage of the polysilicon PN junctions is slightly smaller than that of the epitaxial layer 2, so that the polysilicon PN junctions are broken down earlier than the epitaxial layer 2, and the potential of the first polysilicon electrode in the floating terminal groove 921a is fixed. That is, in the present invention, the electric field is not changed by fixing the electric potential of the floating terminal groove 921a, so that the electric potential of the terminal region groove 92 is fixed, the breakdown voltage of the schottky diode device is fixed, and the reliability of the device is improved.

The present invention is also not limited to the width of the MESA in the termination region (the spacing between every 2 first termination slots 921), and the specific width is related to the depth of the trench, and the deeper the trench, the larger the MESA width needs to be. In this embodiment, the distance between every two first terminal slots 921 is 0.5-2 μm, so the physical performance of the terminal region structure is good.

The thickness of the gate oxide layer 44 is not limited by the present invention, and preferably, the thickness of the gate oxide layer 44 is

Wherein, the unit

Is in the range of angstroms (a) and,

the thickness is 0.1 nm, and the reliability of the device is good under the thickness.

Further, the schottky diode further includes a passivation layer 7 and a barrier metal layer 8, the passivation layer 7 is disposed on the first polysilicon structure 5 and the second polysilicon structure 6, two ends of the passivation layer 7 are exposed out of a portion of the first polysilicon structure 5, the barrier metal layer 8 is disposed on the middle layer and the passivation layer 7, the barrier metal layer 8 has a first metal layer unit corresponding to the passivation layer 7, and the first metal layer unit is provided with a groove penetrating to an upper surface of the passivation layer 7. In this way, the 1 st termination region trench 92 on the left side is in contact with the barrier metal layer 8, the stop-ring trench 922 is in contact with the epitaxial layer 2 through the metal layer, and the middle of the second polysilicon structure 6 on the rightmost side is open, which may cause a short circuit.

Referring to fig. 3 and 4, in the present embodiment, the schottky diode is manufactured by the following steps (fig. 3a → 3b → 3c → 4d → 4e → 4f → 4 g):

step S10 provides substrate 1, and epitaxial layer 2 is prepared on the upper side of substrate 1.

Wherein, the substrate 1 is provided as N + type monocrystalline silicon. The epitaxial layer 2 is N-type single crystal silicon and has a doping concentration of 10¹³～10¹⁸cm^-3。

Step S20, preparing an oxide layer 3 on the upper side of the epitaxial layer 2 to form an intermediate layer.

Specifically, referring to fig. 3a, an oxide layer 3 is grown on the epitaxial layer 2 as a barrier layer for the subsequent trench etching. Among them, the thickness of the oxide layer 3 is preferably

Under the thickness, the blocking effect is good. More preferably, the thickness of the oxide layer 3 is

Step S30, performing photolithography and etching on the intermediate layer to form a plurality of trenches, each trench having a first inner wall corresponding to the epitaxial layer 2.

For the method of forming the trench by photolithography and etching, the conventional steps in the art can be adopted. The topography after processing in step S30 is shown in fig. 3b, where the left side of the dotted line is the active region and the right side of the dotted line is the termination region.

Step S40, preparing a gate oxide layer 4 on the first inner wall, the gate oxide layer 4 defining a channel.

Forming a gate oxide layer 4 by thermal oxidation process, wherein the thickness of the gate oxide layer 4 is

The profile processed in step S40 is shown in fig. 3 c.

Step S50, correspondingly preparing a plurality of first polysilicon structures 5 in the plurality of channels.

Depositing polysilicon in the trench, and in-situ doping with a doping ion concentration of 10¹⁷～10²⁰cm^-3Doping element is phosphorus or arsenic to form N-type heavily doped polysilicon, and then reverse etching is carried out to remove muchThe remaining N-type heavily doped polysilicon results in a first polysilicon structure 5 disposed only in the channel, the topography of which is shown in fig. 4 d. Among them, the reverse etching is a process employed when it is desired to reduce the total thickness of a certain layer.

Step S60, preparing at least two second polysilicon structures 6 spaced apart on the upper side of the intermediate layer in the termination region.

In one embodiment, step S60 includes:

and step S61, performing polysilicon deposition on the upper side of the middle layer, and doping boron in situ in the polysilicon deposition process to form P-type polysilicon.

Specifically, polysilicon deposition is performed on the structure depicted in FIG. 4d, and boron is doped in situ during the polysilicon deposition process, with a dopant ion concentration of 10¹³～10¹⁵cm^-3And obtaining the P-type lightly doped polysilicon.

Step S62, performing photolithography and etching on the P-type polysilicon to remove the P-type polysilicon on the upper side of the active region and a part of the P-type polysilicon on the upper side of the termination region, so as to obtain at least two second polysilicon structures 6.

The second polysilicon structures 6 processed in step S62 are separated from each other as shown in fig. 4 e.

In another embodiment, step S60 includes:

step S61, depositing polycrystalline silicon on the upper side of the middle layer to obtain polycrystalline silicon, doping boron on the polycrystalline silicon in an ion implantation mode, and annealing to form P-type polycrystalline silicon;

specifically, polysilicon deposition is performed on the structure shown in fig. 4d to obtain polysilicon, and then boron is doped by ion implantation and re-annealing, wherein the concentration of doped ions is 10¹³～10¹⁵cm^-3And obtaining the P-type lightly doped polysilicon.

Step S62, performing photolithography and etching on the P-type polysilicon to remove the P-type polysilicon on the upper side of the active region and a part of the P-type polysilicon on the upper side of the termination region, so as to obtain at least two second polysilicon structures 6.

Further, the following steps are also included after step S60:

step S70, preparing a passivation layer 7 on the first polysilicon structure 5 and the second polysilicon structure 6.

Specifically, a passivation layer 7 is deposited on the structure shown in fig. 4e, and then an active region and contact hole (not shown) etching of the termination ring are performed, the topography of which is shown in fig. 4 f. The prepared passivation layer 7 wraps the polysilicon PN junction diodes connected in series, wherein the number of N-type and P-type regions is determined by the number of the termination region trenches 92, and in the present embodiment, an NPNPN-type structure is formed. The utility model does not limit the concrete material for preparing the passivation layer 7, and the passivation layer can be BPSG (boron phosphorus silicon glass), TEOS (tetraethyl orthosilicate) and the like.

Step S80, preparing a barrier metal layer 8 on the intermediate layer.

Specifically, a barrier metal is sputtered on the structure shown in fig. 4f, the barrier metal layer 8 has a first metal layer unit corresponding to the passivation layer 7, and then the first metal layer unit is subjected to photolithography etching to obtain a groove penetrating through the upper surface of the passivation layer 7, and the topography of the groove is shown in fig. 4 g.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent structural changes made by using the contents of the present specification and the drawings, or any other related technical fields, which are directly or indirectly applied to the present invention, are included in the scope of the present invention.

Claims (4)

1. A schottky diode, comprising:

a substrate;

the middle layer is arranged on the upper side of the substrate and comprises an epitaxial layer and an oxide layer located on the upper side of the epitaxial layer, a plurality of grooves are formed in the upper portion of the middle layer, the grooves comprise at least one active region groove located in an active region and a plurality of terminal region grooves located in a terminal region, each groove is provided with a first inner wall corresponding to the epitaxial layer, a gate oxide layer is arranged on the first inner wall, and a channel is defined by the gate oxide layer;

a plurality of first polysilicon structures correspondingly filled in the channels;

the second polycrystalline silicon structures are arranged on the middle layer of the terminal area at intervals, each second polycrystalline silicon structure is arranged corresponding to the area between two adjacent first polycrystalline silicon structures, two ends of each second polycrystalline silicon structure are respectively contacted with the two first polycrystalline silicon structures to form a polycrystalline silicon PN junction in series, and the breakdown voltage of the polycrystalline silicon PN junction is smaller than that of the epitaxial layer.

2. The schottky diode of claim 1 wherein said gate oxide layer has a thickness of

3. The schottky diode of claim 1 wherein one of the termination trenches farthest from the active region is a stop ring trench and the others are first termination trenches, and the spacing between every two first termination trenches is 0.5 to 2 μm.

4. The schottky diode of claim 1 further comprising:

the passivation layer is arranged on the upper sides of the first polycrystalline silicon structure and the second polycrystalline silicon structure, and two ends of the passivation layer expose part of the first polycrystalline silicon structure;

and the barrier metal layer is arranged on the upper sides of the middle layer and the passivation layer, the barrier metal layer is provided with a first metal layer unit corresponding to the passivation layer, and the first metal layer unit is provided with a groove penetrating to the upper surface of the passivation layer.

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